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WO2005111640A1 - Systeme de surveillance dans un circuit integre - Google Patents

Systeme de surveillance dans un circuit integre Download PDF

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Publication number
WO2005111640A1
WO2005111640A1 PCT/US2005/012732 US2005012732W WO2005111640A1 WO 2005111640 A1 WO2005111640 A1 WO 2005111640A1 US 2005012732 W US2005012732 W US 2005012732W WO 2005111640 A1 WO2005111640 A1 WO 2005111640A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
system monitor
adc
output
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/012732
Other languages
English (en)
Inventor
F. Erich Goetting
John K. Jennings
Anthony J. Collins
Patrick J. Quinn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/837,330 external-priority patent/US7599299B2/en
Priority claimed from US10/837,171 external-priority patent/US7102555B2/en
Priority claimed from US10/837,135 external-priority patent/US7138820B2/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of WO2005111640A1 publication Critical patent/WO2005111640A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/3167—Testing of combined analog and digital circuits

Definitions

  • One or more aspects of the invention relate generally to testing an integrated circuit having a system monitor and, more particularly, to a system monitor embedded in a programmable logic device.
  • Configuration interface 14 can be, for example, a select map interface, an IEEE 1149.1 TAP interface, or a master serial interface.
  • FPGA 10 may be internally reconfigured through use of ICAP 16 or a dynamic reconfiguration port ("DRP") 201 (shown in FIG. 2).
  • Configuration data is conventionally divided out into data frames. Configuration data may be loaded into the configuration memory array one frame at a time via configuration interface 14 or ICAP 16, or in sub-frame increments (e.g., one or more words, bytes, and/or bits) via a dynamic reconfiguration port.
  • FIG. 2 is a high-level schematic/block diagram depicting an exemplary embodiment of a pin-out for System Monitor 20.
  • inverted signals are indicated with “_b" in the signal identifier.
  • inverted signals are referred to as “signals” elsewhere herein.
  • Input pin 151 may be for a scan memory clock signal. Input pin 152 may be for a scan memory write enable signal. Accordingly, pins 141 through 152 are for scan test signals 276 and are connected to host FPGA through programmable interconnects.
  • Dedicated external pins 153 through 156 may be used as external reference inputs for an ADC external reference inputs and analog supply 275. For example, pin 153 may be for a positive reference voltage.
  • Pin 154 may be used for a negative reference voltage.
  • Pin 155 may be for an ADC supply voltage, AV DD - Pin 156 may be for an ADC ground reference, AV S s- With continuing reference to FIG. 2, and additional reference to FIG. 3A, an exemplary embodiment of the System Monitor 20 is further described.
  • System Monitor 20 is coupled to FPGA intemal sensors 203-1 to 203-M
  • Analog inputs 124 through 127 may use differential digital input/output pairs in a selected input output portion of a bank of input/output blocks of an FPGA. For example, fourteen local digital inputs/outputs of an FPGA may be used to provide seven differential analog channels. Notably, analog input channels 124 through 127 may be used to monitor FPGA external environmental conditions or physical characteristics, such including without limitation power supply, voltages, currents, temperature of transducers, and chassis integrity. Additionally, dedicated analog inputs 122 and 123 may be provided as inputs to multiplexer Outputs of intemal sensors/detectors 203 are provided as inputs to multiplexer 217, and one or more of such inputs to multiplexer 217 may be provided as output for input to multiplexer 216. Control signals, such as from a channel sequencer 222, for multiplexers
  • ADC 200 has one differential input channel provided by inputss 211 and 213, by having output of multiplexer 216 coupled to such inputs 211 and 213, any of the input channels of multiplexer tree 220 may be selected for output from multiplexer 216 as input to ADC 200. Though three multiplexers are shown for multiplexer tree 220, fewer or more multiplexers may be used.
  • ADC clock signal 219 may be provided from control logic 221. Control0 logic 221 is coupled to receive oscillator signal 215 and DRP clock signal 108. Control logic 221 may use a clock source from DRP clock signal 108 or an internal FPGA oscillator signal 215, which is defined by internal FPGA configuration.
  • Control registers 206 may be dynamically reconfigured, such as to select a System Monitor channel and to store alarm threshold values for parameters being monitored, via DRP interface 205.
  • Control registers 206 may be part of a random access memory block, such as a static random access memory block of memory of an FPGA. This block of memory may be dedicated memory of a function block, such as System Monitor 20, or may be dual ported configuration memory of an FPGA.
  • default settings for control registers 206 may be set to default values as part of a configuration bit stream used to initialize an FPGA. This initialization allows System Monitor 20 to start operation in known condition, and facilitates alarm values to be stored and downloaded from FPGA configuration memory.
  • System Monitor 20 may provide a digital averaging function allowing the user to average a number of samples, for example 256 individual temperature sensor samples to produce a reading. Averaging may be used to help reduce the effects of noise and to improve repeatability of measurement.
  • a result of a temperature reading may be placed in a register of output data registers 209. Notably, a full ADC transfer function may be greater than a temperature operating range of an FPGA.
  • voltage such as supply voltage
  • conditions may be monitored for any potential problems.
  • monitoring internal power supplies involves selecting a channel via control registers 206. A transfer function for an on-chip voltage being monitored would be similar to that of FIG.
  • FIG. 7A is a signal diagram depicting an exemplary embodiment of
  • channel sequencer 222 which forms part of control logic 221 of FIG. 3A.
  • Channel sequencer 222 allows a user to set up a sequence of channels and their associated operating conditions for automatic monitoring.
  • a sequencer function is made up of a number of channels, including calibration channels. For example, there may be approximately 20 channels. These channels are associated with registers as previously described. Each sequence register may have the same bit definitions as configuration register 310-0. Accordingly, as well as selecting a channel, sequence registers may be used to select unipolar or differential input operation for that selected channel. Notably, internal channels may be unipolar only. Sequencer 222 may be used to select whether a channel result is averaged, and may be used to provide a longer acquisition time for such a channel.
  • a user can reset System Monitor 20 with reset signal 199. This reset may be done dynamically via DRP 201.
  • Continuous mode operation is the same as single pass mode operation, except at the end of a singled pass through a sequence, an EOS signal 134 pulse is issued, such as pulse 809, and the sequence automatically starts over again. Conversion or average results from each selected channel in a sequence are loaded into a corresponding data register of data registers 209 when a conversion is finished.
  • These registers may be read during operation via DRP 201. For example, results from channel 0 may be written to data register 0 and results from channel 5 may be written to data register 5, where 0 and 5 refer to address locations of such registers.
  • Capture data register signal 1604 pulses high during that first full cycle 1675 that clock data register signal 1606 goes from an idle logic high state to cycling.
  • Enable signal 1605 in response to pulse 1631 goes to a logic high level on the falling edge of that first full cycle 1675 of clock data register signal 1606.
  • FIG. 17A is a block/schematic diagram depicting an exemplary embodiment of an analog-to-digital TAP interface 1700 for capturing data.
  • Control logic 1701 is configured to provide TDO signals 1602 and to receive captured data register signal 1604, clock data register signal 1606 and Test Data Input ("TDI") signals 1702.
  • Signals 1604, 1606, 1602 and 1702 are to or from JTAG controller 1517 of FIG. 15B.
  • a single DAC may be used to test multiple circuits.
  • Output of DAC 1712 may be a reference voltage, frequency or waveform for testing analog functions of circuit under test 1713.
  • control logic 1711 and 1702 may be formed of configurable logic. However, control logic 1711 and 1702 may be hardwired logic.
  • multiplexer 216 and demultiplexer 1716 are formed of hardwired logic.
  • an analog input may be provided via DAC 1712 to a circuit under test 1713, and the response to such analog input stimulus may be an analog voltage or other analog information. This information may be collected using a TAP of TAP controller 1517 of FIG. 15B.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un appareil destiné à un système de surveillance (20) incorporé dans un circuit intégré. Le système de surveillance (20) comprend une interface (205) de port à reconfiguration dynamique, destinée à configurer ou à reconfigurer le système de surveillance (20) lors du fonctionnement de celui-ci. Le système de surveillance (20) comprend un convertisseur analogique à numérique (200) qui est reconfigurable en réponse à une entrée via un port à reconfiguration dynamique (201).
PCT/US2005/012732 2004-04-30 2005-04-14 Systeme de surveillance dans un circuit integre Ceased WO2005111640A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US10/837,135 2004-04-30
US10/837,330 US7599299B2 (en) 2004-04-30 2004-04-30 Dynamic reconfiguration of a system monitor (DRPORT)
US10/837,330 2004-04-30
US10/837,171 2004-04-30
US10/837,171 US7102555B2 (en) 2004-04-30 2004-04-30 Boundary-scan circuit used for analog and digital testing of an integrated circuit
US10/837,135 US7138820B2 (en) 2004-04-30 2004-04-30 System monitor in a programmable logic device

Publications (1)

Publication Number Publication Date
WO2005111640A1 true WO2005111640A1 (fr) 2005-11-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/012732 Ceased WO2005111640A1 (fr) 2004-04-30 2005-04-14 Systeme de surveillance dans un circuit integre

Country Status (1)

Country Link
WO (1) WO2005111640A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011119936A3 (fr) * 2010-03-25 2012-07-19 Qualcomm Incorporated Capteur de température basse tension et utilisation associée pour dispositif de mesure autonome à sondes multiples
CN103376757A (zh) * 2012-04-13 2013-10-30 阿尔特拉公司 用于校准集成电路中的模拟电路系统的装置和方法
US20180019517A1 (en) * 2016-07-18 2018-01-18 Anokiwave, Inc. Phased Array Burst Sampler
US10018675B1 (en) 2014-03-14 2018-07-10 Altera Corporation Testing an integrated circuit in user mode using partial reconfiguration
CN113422916A (zh) * 2021-06-08 2021-09-21 天津大学 消除抖动的数字累加器及抖动消除方法
CN114421962A (zh) * 2021-12-28 2022-04-29 广东纳睿雷达科技股份有限公司 采样通道异常诊断方法、装置、设备和存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305003A (en) * 1991-05-13 1994-04-19 Goldstar Electron Co., Ltd. Test device of analog/digital converter
JP2001085622A (ja) * 1999-09-13 2001-03-30 Hitachi Ltd 半導体集積回路およびその検査方法並びに製造方法
US20020149972A1 (en) * 2001-04-10 2002-10-17 International Business Machines Corporation Analog-to-digital converter for monitoring vddq and dynamically updating programmable vref when using high-frequency receiver and driver circuits for commercial memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305003A (en) * 1991-05-13 1994-04-19 Goldstar Electron Co., Ltd. Test device of analog/digital converter
JP2001085622A (ja) * 1999-09-13 2001-03-30 Hitachi Ltd 半導体集積回路およびその検査方法並びに製造方法
US20020149972A1 (en) * 2001-04-10 2002-10-17 International Business Machines Corporation Analog-to-digital converter for monitoring vddq and dynamically updating programmable vref when using high-frequency receiver and driver circuits for commercial memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 20 10 July 2001 (2001-07-10) *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011119936A3 (fr) * 2010-03-25 2012-07-19 Qualcomm Incorporated Capteur de température basse tension et utilisation associée pour dispositif de mesure autonome à sondes multiples
US8354875B2 (en) 2010-03-25 2013-01-15 Qualcomm Incorporated Low voltage temperature sensor and use thereof for autonomous multiprobe measurement device
US8451048B2 (en) 2010-03-25 2013-05-28 Qualcomm Incorporated Low voltage temperature sensor and use thereof for autonomous multiprobe measurement device
US10911164B2 (en) 2012-04-13 2021-02-02 Altera Corporation Apparatus and methods for calibrating analog circuitry in an integrated circuit
EP2650789A3 (fr) * 2012-04-13 2014-05-14 Altera Corporation Appareil et procédés d'étalonnage d'un ensemble de circuits analogiques dans un circuit intégré
US10110328B2 (en) 2012-04-13 2018-10-23 Altera Corporation Apparatus and methods for calibrating analog circuitry in an integrated circuit
CN103376757A (zh) * 2012-04-13 2013-10-30 阿尔特拉公司 用于校准集成电路中的模拟电路系统的装置和方法
US10018675B1 (en) 2014-03-14 2018-07-10 Altera Corporation Testing an integrated circuit in user mode using partial reconfiguration
US20180019517A1 (en) * 2016-07-18 2018-01-18 Anokiwave, Inc. Phased Array Burst Sampler
US10559879B2 (en) * 2016-07-18 2020-02-11 Anokiwave, Inc. Phased array burst sampler
CN113422916A (zh) * 2021-06-08 2021-09-21 天津大学 消除抖动的数字累加器及抖动消除方法
CN113422916B (zh) * 2021-06-08 2022-10-11 天津大学 消除抖动的数字累加器及抖动消除方法
CN114421962A (zh) * 2021-12-28 2022-04-29 广东纳睿雷达科技股份有限公司 采样通道异常诊断方法、装置、设备和存储介质

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