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WO2005038929A1 - Procede de fabrication d'un dispositif semi-conducteur - Google Patents

Procede de fabrication d'un dispositif semi-conducteur Download PDF

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Publication number
WO2005038929A1
WO2005038929A1 PCT/JP2004/015128 JP2004015128W WO2005038929A1 WO 2005038929 A1 WO2005038929 A1 WO 2005038929A1 JP 2004015128 W JP2004015128 W JP 2004015128W WO 2005038929 A1 WO2005038929 A1 WO 2005038929A1
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Prior art keywords
metal
metal compound
compound layer
gate insulating
insulating film
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English (en)
Japanese (ja)
Inventor
Heiji Watanabe
Masayuki Terai
Hirohito Watanabe
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NEC Corp
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NEC Corp
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Publication of WO2005038929A1 publication Critical patent/WO2005038929A1/fr
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    • H10D64/0134—
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H10D64/01306—
    • H10D64/01342—
    • H10D64/01344—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H10P14/6328—
    • H10P14/6309—
    • H10P14/69433—

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device provided with a high-dielectric-constant thin film, and more particularly to a high-performance and low-power gate insulating film constituting a MOSFET (Meta-Oxide-Semiconductor Field Effect Transistor). And a method of manufacturing a semiconductor device.
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • a semiconductor device in which a gate insulating film is formed between a silicon substrate and a gate electrode for example, a semiconductor device including a MOSFET is known.
  • Silicon oxide films have excellent process stability and excellent insulating properties and are therefore widely used as materials for forming gate insulating films of MOSFETs.
  • the thickness of the gate insulating film is becoming thinner.For devices with a gate length of less than 100 nm, the silicon oxide that is the gate insulating film is It is necessary that the thickness of the film is 1.5 nm or less.
  • One of the research and developments is that by adding nitrogen to a silicon oxide film to form a silicon oxynitride film, the dielectric constant is increased compared to a pure silicon oxide film, and a gate is formed.
  • a silicon oxynitride film is formed by forming a silicon oxide film on the surface of a silicon substrate and then performing a high-temperature heat treatment in a gas containing nitrogen such as ammonia (NH 3).
  • the silicon oxide film is formed by introducing nitrogen.
  • the relative dielectric constant of the pure silicon nitride film is about twice that of the silicon oxide film
  • the relative dielectric constant of the silicon oxynitride film is lower than that of the silicon oxide film. It is less than twice. Therefore, there is a limit to high dielectric constant by adding nitrogen to the silicon oxide film, and it is theoretically impossible to form a gate insulating film having a relative dielectric constant of 10 or more.
  • a thin film material made of a metal oxide having a relative dielectric constant of 10 or more instead of a silicon oxide film and a silicon oxynitride film, a thin film material made of a metal oxide having a relative dielectric constant of 10 or more, Attempts have been made to use a silicate thin film material, which is a composite material of silicon and a thin film material, for a gate insulating film.
  • Such high dielectric constant materials include Al O, ZrO, HfO and
  • Is considered as a candidate material Is considered as a candidate material.
  • these films with a high dielectric constant as the gate insulating film even if the gate length is reduced, the thickness of the gate insulating film can be maintained while maintaining the gate insulating film capacitance in accordance with the scaling rule.
  • the film thickness can suppress the tunnel current within an allowable range.
  • the gate insulating film material is a silicon oxide film, and the electrical film thickness of the insulating film obtained by reverse calculation from the gate capacitance. This is called EOT Equivalent Oxide Thickness. That is, when the relative permittivity of the insulating film is ⁇ h, the relative permittivity of the silicon oxide film is ⁇ ⁇ , and the thickness of the insulating film is dh, the equivalent thickness de of the silicon oxide film is expressed by the following equation 1. expressed.
  • Equation 1 above indicates that when a material having a dielectric constant ⁇ h greater than the relative dielectric constant ⁇ ⁇ of the silicon oxide film is used for the gate insulating film, the equivalent silicon oxide film thickness Indicates that the thickness becomes equal to that of the silicon oxide film which is thinner than the thickness of the gate insulating film.
  • the relative permittivity ⁇ of the silicon oxide film is about 3.9.
  • the relative dielectric constant is lower than that of the gate insulating film made of the metal oxide film, but the thermal stability is low. And the electrical characteristics of the interface can be improved as compared with the case where the metal oxide is directly bonded on the silicon substrate.
  • the common feature of these gate insulating film forming methods is that the surface of the silicon substrate has a high dielectric constant whose composition matches the stoichiometric composition (or the silicate composition with sufficient or insufficient oxygen concentration). Is to deposit a rate film. In particular, structural defects such as oxygen vacancies in the gate insulating film deteriorate electrical characteristics and increase leak current.
  • the characteristics of various high dielectric constant films manufactured by the above-described thin film deposition method have been studied.
  • the biggest technical challenge for the development of next-generation MOSFETs is to improve interfacial electrical characteristics. That is, as in the case of the silicon oxynitride film described above, the interface defect density between the high dielectric constant thin film and the silicon substrate is 10 to 100 times the interface defect density between the silicon oxide film and the silicon substrate. About high. Therefore, the mobility of the trapped charge significantly deteriorates, the current driving capability of the MOSFET is reduced, and the effect of thinning the gate insulating film is offset.
  • the interface structure that determines the electrical characteristics is closely related to the method of manufacturing the high dielectric constant thin film.
  • the silicon substrate is oxidized simultaneously with the deposition of the thin film, and an interface layer mainly composed of the silicon oxidized film is formed. For this reason, it is difficult to control the growth of the interface layer and the high dielectric constant thin film independently of each other, and it is not possible to independently design a structure that optimizes the interfacial electrical characteristics.
  • means for intentionally inserting a silicon oxide film as an interfacial oxide film include (1) forming an ultra-thin silicon oxide film on the surface of a silicon substrate and then forming a high dielectric (See, for example, Patent Document 1), (2) a method of depositing a high dielectric constant thin film and then performing a heat treatment to grow a silicon oxide film, and (3) a method of depositing silicon on a silicon substrate surface.
  • Shape an acid film A method is known in which at least one kind of metal is ion-implanted into the silicon oxide film and then the metal is diffused into the silicon oxide film by heat treatment (for example, see Patent Document 2). I have.
  • Patent Document 1 JP-A-2002-289844
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2002-314074
  • the conventional technique described above has the following problems.
  • the silicon oxide film has an effect of improving interfacial thermal stability, but since the silicon oxide film has a low relative dielectric constant, the initial silicon oxide film formed on the surface of the silicon substrate is reduced. It is necessary to make the film thickness of the film so thin as 0.6 nm or less, and it is difficult to control the film thickness.
  • the silicon oxide film since the silicon oxide film is extremely thin, the underlying silicon oxide film may be altered during the step of depositing the high dielectric constant thin film on the silicon oxide film, The interface characteristics between the silicon oxide film and the silicon substrate may deteriorate.
  • the method (2) above utilizes a phenomenon in which oxygen easily diffuses in a high dielectric constant film to form an interface layer.
  • the metal element in the high dielectric constant film may diffuse into the interface layer in the heat treatment step.
  • an ideal silicon oxide film having excellent electrical characteristics is obtained.
  • the interface between the silicon and the silicon substrate cannot be formed.
  • a defect occurs immediately upon ion implantation of a metal into the silicon oxide film, and diffusion of a metal element cannot be controlled during heat treatment.
  • the present invention has been made in view of a powerful problem, and has a high dielectric constant on a silicon substrate.
  • a high-quality silicon oxide / silicon interface is formed at the interface between the gate insulating film and the silicon substrate, and the electrical interface between the gate insulating film and the silicon substrate is formed. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving characteristics and forming a high-quality high dielectric constant film.
  • a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a gate insulating film for electrically insulating a gate electrode from a substrate, wherein the base layer contains silicon on the substrate.
  • Forming an underlayer forming a metal compound layer made of a metal compound on the underlayer, and heat treating the underlayer and the metal compound layer to form the underlayer.
  • a step of forming a gate insulating film from the metal compound layer is a method of manufacturing a semiconductor device having a gate insulating film for electrically insulating a gate electrode from a substrate, wherein the base layer contains silicon on the substrate.
  • a base layer containing silicon is formed on a substrate, and a metal contained in a metal compound layer is introduced from the surface side of the base layer to form a gate insulating film.
  • a good-quality gate insulating film can be obtained while maintaining a good-quality silicon oxide / silicon interface at the interface between the gate insulating film and the silicon substrate.
  • a metal element contained in the metal compound layer is not diffused at an interface between the base layer and the substrate.
  • the underlayer and the metal compound layer are subjected to a heat treatment in a state where the surface of the metal compound layer is exposed.
  • a silicon substrate, a germanium substrate, or a semiconductor substrate made of silicon and germanium may be used as the substrate.
  • the method for manufacturing a semiconductor device according to the present invention may include a step of forming a gate electrode after the step of forming a gate insulating film.
  • the step of forming the gate insulating film may be a step of diffusing a metal element contained in the metal compound layer into the underlayer, and the step of forming the gate insulating film is included in the underlayer in the metal compound layer. It may be a step of diffusing a silicon element.
  • the underlayer is made of silicon nitride or silicon oxynitride. Further, the thickness of the underlayer is preferably not less than 1. Onm, more preferably not less than 1.5 nm.
  • the metal compound layer is made of Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb And one or more metal elements selected from the group consisting of Lu.
  • the metal compound may be a metal oxide containing the metal element and oxygen or a metal nitride containing the metal element and nitrogen.
  • the metal oxide is A compound comprising only a metal element and oxygen, a metal oxynitride comprising the metal element, oxygen and nitrogen, a metal silicon oxide comprising the metal element, oxygen and silicon, and a metal silicon oxide comprising the metal element, oxygen, nitrogen and silicon Metal oxynitride, metal aluminum oxynitride comprising the above metal element other than aluminum, oxygen and aluminum, or metal aluminum oxynitride comprising the above metal element other than aluminum, aluminum, oxygen and nitrogen It may be.
  • the thickness of the metal compound layer is preferably 2.Onm or less, more preferably 1.5 nm or less. At this time, the metal compound layer preferably has a thickness of 0.5 nm or more.
  • the value of the ratio of the film thickness of the metal compound layer to the film thickness of the underlayer is It is preferably 1.5 or less, more preferably 1.0 or less.
  • the metal compound layer is made of the metal oxide, and the composition of the metal compound layer is a composition in which oxygen is deficient in a stoichiometric composition.
  • oxygen in the gate insulating film made of the metal compound layer be compensated by an oxidation reaction during heat treatment.
  • the metal oxide is the metal silicon oxide, the metal silicon oxynitride, the metal aluminum oxide or the metal aluminum oxynitride, and among the silicon and aluminum in the metal oxide.
  • the content of at least one of the metal oxides is preferably 20 to 40 atomic% with respect to the value obtained by removing oxygen and nitrogen from the metal oxide.
  • the metal compound layer is the metal nitride
  • the metal compound layer preferably has a thickness of 1. Onm or less, more preferably 0.6 nm or less.
  • the equivalent oxide film thickness of the gate insulating film is smaller than the equivalent oxide film thickness of the underlayer before the metal compound layer deposition step. Preferably.
  • the metal compound layer deposition step may be a step of depositing hafdium nitride as the metal compound on the underlayer to a thickness of 1. Onm or less, or hafnium silicon It may be a step of depositing an oxide or hafnium silicon oxynitride to a thickness of 1.5 nm or less.
  • the step of forming a gate insulating film includes a low-temperature heat treatment step of performing a heat treatment at a temperature lower than a crystallization temperature of a metal compound constituting the metal compound layer.
  • a high-temperature heat treatment step of performing heat treatment at a temperature higher than the crystallization temperature is more preferable to have a high-temperature heat treatment step of performing heat treatment at a temperature higher than the crystallization temperature.
  • the step of forming a gate insulating film it is preferable that at least a part of the heat treatment is performed in a reducing atmosphere.
  • the reducing atmosphere may be a hydrogen atmosphere or an ammonia atmosphere.
  • the gate insulating film forming step it is preferable to perform a heat treatment until the composition of the uppermost part of the metal compound layer is different from the composition after the metal compound layer depositing step.
  • an unreacted region peeling step of peeling off the unreacted region is further provided.
  • This unreacted region peeling step may be a step of peeling off the unreacted region using a hydrofluoric acid solution or an aqueous solution of ammonium hydrogen peroxide. It is preferable that the method further includes a step of performing a heat treatment after the unreacted region peeling step.
  • the present invention by optimizing the film forming conditions, it is possible to form a structure in which a good quality silicon oxide film Z silicon interface is preserved at the interface between the gate insulating film and the silicon substrate. . Therefore, it is possible to improve the interfacial electrical characteristics, which has been a problem in the practical use of a gate insulating film having a high dielectric constant.
  • the metal element is diffused only on the surface side of the silicon oxide film, and the silicon oxide film is diffused. Dangeon Z series This makes it easy to optimize the conditions under which the metal element does not reach the interface of the capacitor substrate, and makes it possible to form a high dielectric constant gate insulating film having excellent interfacial electrical characteristics.
  • FIG. 1 (a) to (d) are cross-sectional views showing the steps of forming a gate insulating film in the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of the steps.
  • FIG. 2 is a cross-sectional view showing a semiconductor device manufactured according to the present embodiment, and the horizontal axis represents the metal element concentration, and the vertical axis represents the position in the thickness direction of the gate insulating film. It is a graph which shows a metal element concentration distribution.
  • 3 (a) and 3 (b) are cross-sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.
  • FIGS. 4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first example in the order of steps.
  • FIG. 5A is a graph showing the characteristics of an N-type MOSFET
  • FIG. 5B is a graph showing the characteristics of a P-type MOSFET.
  • FIG. 6 (a) and (b) show the values of the HfSiO film thickness before the thermal diffusion treatment plotted on the horizontal axis and the transistor on-current (Ion) normalized by the inversion capacitance on the vertical axis.
  • Fig. 3 is a graph showing the characteristics of a MOSFET provided with a gate insulating film that also has a Hf SiO force, where (a) shows the characteristics of an N-type MOSFET and (b) shows the characteristics of a P-type MOSFET. .
  • FIGS. 7A to 7D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a fifth embodiment in the order of steps.
  • FIG. 1A to 1D are cross-sectional views showing the steps of forming a gate insulating film in the method of manufacturing a semiconductor device according to the present embodiment in the order of steps
  • FIG. 2 is a cross-sectional view showing a semiconductor device manufactured according to the present embodiment
  • FIG. 3 is a cross-sectional view showing the device, and a graph showing the distribution of the metal element concentration in the gate insulating film by taking the metal element concentration on the horizontal axis and the position in the thickness direction of the gate insulating film on the vertical axis.
  • a silicon substrate 101 having a silicon force is prepared. Then, wet etching or the like using a hydrofluoric acid solution is performed on the silicon substrate 101. Thus, the silicon oxide film and the like formed on the surface of the silicon substrate 101 are washed and removed. In addition, this cleaning allows the surface-terminated hydrogen 102 to appear on the surface of the silicon substrate 101.
  • a hydrogen atom is indicated by a symbol “H”.
  • an underlayer 103 having silicon oxide properties is formed by an RTO (Rapid Thermal Oxidation) method (underlayer formation step).
  • the underlayer 103 may be formed of silicon oxynitride in which a very small amount (several%) of nitrogen is introduced into the silicon oxide film.
  • the thickness of the underlayer 103 is set to be thicker than, for example, a conventional interface insertion layer (normally 0.6 nm or less).
  • the thickness is preferably equal to or more than the finally required electric film thickness (equivalent film thickness of silicon oxide film).
  • the silicon oxide equivalent film thickness is defined by the above equation (1).
  • it is required to reduce the initial thickness of the underlying silicon oxide film in order to reduce the equivalent oxide film thickness.
  • the physical thickness of the underlayer 103 is, for example, not less than 1. Onm, and preferably not less than 1.5 nm in order to maintain the interface.
  • a metal compound layer 104 is deposited on the underlayer 103 by a CVD method or a nottering method (metal compound layer deposition step).
  • the metal compound forming the metal compound layer 104 include a metal oxide, a metal oxynitride, a metal silicate, a metal aluminate, and a metal nitride. These metal compounds diffuse a metal element into the underlayer 103 by heat treatment in a gate insulating film forming step described later, and form a part of the underlayer 103, particularly an underlayer other than the interface with the silicon substrate 101.
  • the upper layer portion of 103 is a gate insulating film 106 of high dielectric constant converted into silicate.
  • the metal compound includes a metal oxide containing a metal element and oxygen, and a metal nitride containing a metal element and nitrogen.
  • metal oxides are compounds consisting only of a metal element and oxygen, metal oxynitrides consisting of a metal element, oxygen and nitrogen, metal silicon oxides consisting of a metal element, oxygen and silicon, and metal elements.
  • a metal silicon oxynitride composed of oxygen, nitrogen and silicon, a metal aluminum oxide composed of a metal element other than aluminum, oxygen and aluminum, and a metal aluminum oxynitride composed of a metal element other than aluminum, aluminum, oxygen and nitrogen Contains metal aluminum oxynitride.
  • metal oxide when simply referred to as a metal oxide, it indicates a compound having only a metal element and oxygen.
  • metal silicon oxide and metal silicon oxynitride are collectively referred to as metal silicate.
  • metal aluminum oxide and metal aluminum oxynitride are collectively referred to as metal aluminate.
  • This metal compound preferably contains oxygen, nitrogen, and the like, and does not contain a compound capable of acting only as a metal.
  • the metal element contained in the metal compound layer 104 includes Zr, Hf, Ta, Al, T i and Nb, selected from the group consisting of rare earth elements Sc and Y, and lanthanoid elements La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu
  • the method of manufacturing a semiconductor device proposed in the present invention that is, the method of forming a gate insulating film having a high dielectric constant can be applied.
  • the metal compound layer 104 containing these metal elements can be formed by a CVD method or a sputtering method using various kinds of source gases.
  • the physical thickness of the metal compound layer 104 is relatively thin, for example, 2. Onm or less, preferably 1 mm, when a metal oxide, metal oxynitride, metal silicate or metal aluminate is used. .5 nm or less and 0.5 nm or more. Specifically, it is preferable that the metal compound layer 104 is formed of a metal oxide or a nitride of silicon, and the physical thickness thereof is set to 1. Onm or less. Alternatively, it is preferable that the metal compound layer 104 be formed of a metal oxide, a silicon oxynitride, or a hafnium silicon oxynitride, and have a physical thickness of 1.5 nm or less.
  • the film thickness of the base layer 103 and the metal compound layer 104 is preferably 1.5 or less. It is more preferably set to 1.0 or less.
  • the composition of the metal compound layer 104 is preferably a composition in which oxygen is less than the stoichiometric ratio. This is to increase the metal diffusion rate, as described later.
  • the metal element is diffused from the metal compound layer 104 to the underlayer 103 to form a gate insulating film 106 (gate insulating film forming step).
  • the reducing atmosphere is, for example, a hydrogen atmosphere or an ammonia atmosphere.
  • the metal compound layer 10 Since oxygen atoms are deprived from 4, oxygen deficiency occurs in the metal compound layer 104, and metal diffusion into the underlayer 103 is promoted. As a result, the metal element can be effectively diffused from the metal compound layer 104 to the base layer 103.
  • the heat treatment temperature is a temperature lower than the crystallization temperature of the metal compound (metal oxide, metal oxynitride, metal silicate, metal aluminate, or metal nitride) forming metal compound layer 104. It is preferred to carry out. This is because, when the metal is diffused by heat treatment at a high temperature, the silicate reaction between the metal compound layer 104 and the underlayer 103 progresses, and the crystallization of the upper part of the metal compound layer 104 progresses. This is because the in-plane uniformity may be reduced only by suppressing the metal diffusion to 103.
  • the metal compound metal oxide, metal oxynitride, metal silicate, metal aluminate, or metal nitride
  • a high-temperature heat treatment is performed at a temperature equal to or higher than the crystallization temperature for the purpose of improving the film quality.
  • the heat treatment described above allows the silicate reaction between the metal compound layer 104 and the underlayer 103 to sufficiently proceed, and the silicon compound contained in the underlayer 103 over the entire metal compound layer 104 The process is performed until atoms diffuse and the composition of the uppermost part of the gold compound layer 104 differs from the composition at the time of deposition of the metal compound layer 104.
  • the heat treatment in the reducing atmosphere and the heat treatment in the oxidizing atmosphere as described above are desirably performed in a state where the surface of the metal compound layer before the formation of the gate electrode is exposed.
  • oxygen vacancies remain in the gate insulating film 106, its electrical characteristics are significantly deteriorated.
  • the composition of the metal compound layer 104 at the time of deposition is a composition in which oxygen is insufficient than the composition determined by the stoichiometric ratio
  • the heat treatment in the dunning atmosphere be a step in which oxygen deficiency in the film is compensated for by supplying oxygen in a gaseous phase with the surface of the metal compound layer 104 exposed.
  • the oxygen deficiency in the gate insulating film can be sufficiently reduced while the oxidation reaction at the substrate interface is suppressed to about several angstroms. Can be reduced.
  • the metal element diffused from the metal compound layer 104 is formed at the interface between the base layer 103 and the silicon substrate 101. Can be reached. That is, the metal element contained in the metal compound layer 104 does not diffuse into the interface between the underlayer 103 and the silicon substrate 101.
  • a gate electrode 107 is formed on the gate insulating film 106. After that, using the gate electrode 107 as a mask, impurity ions are implanted into the surface of the silicon substrate 101 to form a source region and a drain region. Thus, a MOS FET is manufactured on the surface of the silicon substrate 101. As a result, a semiconductor device having a MOSFET can be manufactured.
  • a gate insulating film 106 that electrically insulates the gate electrode 107 from the silicon substrate 101 is formed.
  • the vicinity of the interface with the silicon substrate 101 is a silicon oxide film region 106a containing no metal element, and the interface between the gate insulating film 106 and the silicon substrate 101 is the initial underlying layer 103. A good interface structure similar to that immediately after formation is maintained.
  • the outermost surface portion of the gate insulating film 106 becomes a metal-rich region 106c containing almost no silicon.
  • a silicate region 106b in which a force silicate reaction between the silicon oxide film region 106a and the metal-rich region 106c has progressed is formed.
  • the metal concentration continuously increases toward the upper portion, and the silicon concentration continuously increases toward the lower portion. That is, as shown in FIG. 2, the distribution of the metal element in the gate insulating film 106 is such that the silicon substrate 101 side force is also in the order of the silicon oxide film region 106a and the silicate region 106b ⁇ the metal rich region 106c.
  • a clear interface is not formed between the silicon oxide film region 106a, the silicate region 106b, and the metal-rich region 106c, and the composition change is continuous.
  • the underlayer (oxide film or oxynitride film) 103 containing silicon is formed on the surface of the silicon substrate 101 (underlayer formation step). ), Depositing a metal compound layer 104 made of a metal compound on the surface of the underlayer 103 as a metal supply source or a metal diffusion source (metal compound layer deposition step).
  • a gate insulating film 106 is formed from the base layer 103 and the metal compound layer 104 (gate insulating film forming step).
  • the gate insulating film 106 is formed by diffusing a metal element from the metal compound 104 into the base layer 103.
  • the metal compound layer 104 is formed on the underlayer 103 in the step shown in FIG. 1 (c), and thereafter, a heat treatment is performed in the step shown in FIG.
  • the gate insulating film 106 made of a silicate thin film can be formed.
  • the gate insulating film 106 can have a high dielectric constant.
  • the electric film thickness of the gate insulating film 106 made of a silicate film is changed to the initial electric film of the underlayer 103. It can be thinner than the film thickness (equivalent oxide film thickness).
  • the silicon substrate 10 1 A high-quality interface can be formed between the silicon substrate and the base layer 103 containing silicon, and the electrical characteristics of the interface between the silicon substrate and the gate insulating film can be improved.
  • a defect occurs in the gate insulating film 106.
  • the diffusion distance of the metal element can be controlled at the time of heat treatment, so that a high-quality gate insulating film 106 can be formed.
  • a high dielectric constant gate insulating film made of silicate is not deposited directly on the silicon substrate 101, but rather is formed by an interface reaction between the underlayer 103 and the metal compound layer 104.
  • a high-quality silicate film is used as the gate insulating film 106.
  • the thickness of the gate insulating film 106 where the dielectric constant is high can be made extremely thin.
  • the region when a region that has not reacted with the underlayer 103 is left in the metal compound layer 104, the region becomes an unreacted metal oxide region having inferior film quality and has a characteristic as a gate insulating film. Deteriorates.
  • the metal compound layer 104 serving as a metal diffusion source has a film thickness such that the silicate reaction completely proceeds with the underlayer 103 while ensuring a leak reducing effect.
  • the film thickness is As described above.
  • the metal compound layer 104 As a material of the metal compound layer 104, a metal nitride may be used. In this case, the physical thickness of the metal compound layer 104 is preferably 1. Onm or less, more preferably 0.6 nm or less.
  • 3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present embodiment in the order of steps.
  • the steps of forming the underlayer and the metal compound layer on the silicon substrate are the same as those in the first embodiment. That is, as shown in FIGS. 1A to 1C, the silicon substrate 101 is wet-etched with a hydrofluoric acid solution, the surface of the silicon substrate 101 is oxidized by RTO to form an underlayer 103, and thereafter, For example, the metal compound layer 104 is formed by a CVD method.
  • the unreacted metal compound layer 108 when the unreacted metal compound layer 108 remains, the characteristics of the gate insulating film 106 are degraded. For this reason, in this embodiment, as shown in FIG. 3B, the unreacted metal compound layer 108 is peeled off, and the metal compound layer 104 is silicified by an interface reaction with the underlayer 103. Only the gated portion is used as the gate insulating film 106.
  • the step of removing the unreacted metal compound layer 108 is performed by, for example, wet etching. For this wet etching, for example, a solution based on a dilute hydrofluoric acid solution or an aqueous solution of ammonia and hydrogen peroxide can be used.
  • an additional heat treatment may be performed. With this additional heat treatment, the electrical characteristics of the gate insulating film 106 can be improved.
  • the configuration, operation, and effects of the present embodiment other than those described above are the same as those of the above-described first embodiment.
  • the metal compound used for the metal compound layer 104 as described above preferably has a stoichiometric composition and a composition lacking oxygen. This is because when the metal compound contains a large amount of oxygen vacancies, the diffusion reaction of the metal element proceeds more rapidly. However, even when the metal compound used for the metal compound layer 104 satisfies the stoichiometric composition and the oxygen deficiency in the film is small, the heat treatment at a high temperature or the heat treatment for a long time at a low temperature can reduce Diffusion of metal into the formation 103 can be promoted.
  • silicon (silicon) in the metal compound layer 104 is used in order to obtain an effect as a metal diffusion source. or it has to desirable aluminum concentration is 20-40 atoms 0/0.
  • the unit of atomic% indicates the proportion of silicon atoms or aluminum atoms when the number of all atoms excluding oxygen and nitrogen in each metal compound is 100%. The same applies to the case where the unit of atomic% is used below.
  • nitrogen may be introduced into the gate insulating film.
  • the nitriding step include a heat treatment in an ammonia atmosphere, a nitrogen plasma treatment, and the like. Thereby, the heat resistance of the gate insulating film 106 can be improved.
  • the metal compound layer 104 serves as a metal diffusion source and the metal element is diffused from the metal compound layer 104 to the base layer 103 by the heat treatment in the gate insulating film forming step.
  • the semiconductor device of the present invention The method of manufacturing the device is not limited to this.
  • the silicon element is diffused from the underlayer 103 to the metal compound layer 104 by the heat treatment in the gate insulating film forming step, for example, the underlying layer 103 containing the silicon element serving as a silicon diffusion source.
  • the silicon element is diffused from the underlayer 103 to the metal compound layer 104 by the heat treatment in the gate insulating film forming step, for example, the underlying layer 103 containing the silicon element serving as a silicon diffusion source.
  • the step of forming the gate electrode 107 is preferably provided after the heat treatment for forming the gate insulating film 106. Furthermore, in each of the above-described embodiments, the process of manufacturing a semiconductor device on a silicon substrate has been described, but a germanium substrate or a semiconductor substrate made of silicon and germanium may be used instead of the silicon substrate. .
  • FIGS. 4A to 4C are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment in the order of steps.
  • a high-quality gate insulating film 406 made of a HfSiO (hafnium silicate) film is formed.
  • a silicon thermal oxidation film or a silicon thermal oxynitride film having a thickness of 0.6 to 1.8 nm is formed.
  • a base layer 402. a plurality of samples having different thicknesses of the underlayer 402 were prepared.
  • an HfSiO film 403 to be a metal compound layer was deposited on the surface of the underlayer 402 by MOCVD.
  • Ht Tetiary Butoxy Halhium
  • silane or disilane was used as the Si source
  • an HfSiO film 403 having a physical thickness of 1.5 to 3. Onm was deposited.
  • a plurality of samples were manufactured by making the thicknesses of the HfSiO films 403 different from each other.
  • a heat treatment at a temperature of 600 to 800 ° C. was performed in an ammonia atmosphere and an oxygen atmosphere, and the underlayer 402 and the HfSiO film deposited by CVD were formed.
  • a gate insulating film 406 having HfSiO force was formed.
  • the upper portion becomes the Hf-rich region 404 having a high Hf concentration
  • the lower portion that is, the silicon substrate 401 side becomes the Si-rich region 405 having a high Si concentration.
  • a gate electrode (not shown) capable of forming a polysilicon force is formed on the gate insulating film 406, ions are implanted, and an N-type MOS FET and an N-type MOS FET are formed through a normal transistor manufacturing process such as activation annealing.
  • a P-type MOSFET was fabricated. Since these manufacturing steps are the same as those of the conventionally known steps, detailed description thereof will be omitted.
  • the gate insulating film 406 having HfSiO force produced under these conditions had an equivalent oxide film thickness of 1.5 to 1.9 nm. Also, the leakage current of the gate insulating film 406 made of HfSiO is lower by about 2 to 3.5 digits than that of the conventional silicon oxide film.
  • FIG. 4 is a graph showing characteristics, in which (a) shows the characteristics of an N-type MOSFET and (b) shows the characteristics of a P-type MOSFET.
  • FIGS. 5A and 5B show the results of the measurement of the hysteresis in terms of the thickness of various underlayers 402 and the thickness of the initial HfSiO film 403.
  • FIGS. 5A and 5B when the silicon thermal oxide film is used as the underlayer 402, it is shown as “RTO”, and when the silicon oxynitride film is used, it is shown as “SiON”. Indicated. After the notation “RTO” or “SiON”, the film thickness of the underlayer 402 is shown. This is the same in FIG. 6 described later.
  • V Sweep voltage sweep width
  • the increase in hysteresis corresponds to the phenomenon that charges are trapped in the gate insulating film when a voltage is applied.
  • the characteristics of the transistor decrease.
  • the transistor characteristics can be improved by suppressing the hysteresis by setting the thickness of the HfSiO film 403 to 2.Onm or less, preferably 1.5 nm or less.
  • the thickness of the HfSiO film 403 is less than 0.5 nm, the effect of reducing the leak current is drastically reduced (to less than one digit). Therefore, the deposition thickness of the HfSiO film 403 had to be 0.5 nm or more.
  • the thickness of the HfSiO film 403 was the same, the hysteresis under each voltage sweep condition decreased as the thickness of the underlayer 402 increased.
  • the difference in the hysteresis is remarkable, and when the thickness of the underlayer 402 is 1.6 nm and 1.8 nm, the hysteresis is small.
  • the film thickness reached 1.4 nm, the hysteresis increased rapidly.
  • the thickness of the underlayer 402 was 0.6 nm, the hysteresis was further increased. Note that the measurement results when the thickness of the underlayer 402 is 0.6 nm are not plotted in FIGS. 5A and 5B. From these results, in order to improve the transistor characteristics, the thickness of the base layer 402 needs to be 1. Onm or more, and preferably 1.5 nm or more.
  • FIGS. 6 (a) and 6 (b) the horizontal axis indicates the thickness of the HfSiO film 403 before the thermal diffusion treatment, and the vertical axis indicates the on-current (Ion) of the transistor in terms of the inversion capacity.
  • FIG. 4 is a graph showing the characteristics of a MOSFET having a gate insulating film that also has an HfSiO force by taking a ratio of the values, where (a) shows the characteristics of an N-type MOSFET and (b) shows the characteristics of a P-type MOSFET. Show.
  • 6 (a) and 6 (b) indicates the magnitude of the on-state current of the transistor provided with the SiON gate insulating film for reference as 100, and each sample in the first embodiment is based on this value.
  • 3 shows the ratio (%) of the value obtained by standardizing the magnitude of the on-current of FIG.
  • the characteristics of the transistor were improved as the HfSiO film 403 became thinner. Specifically, even with an N-type MOSFET, by setting the thickness of the HfSiO film 403 to 2.Onm or less, about 90% of the characteristics of a transistor using a SiON film as a gate insulating film are realized. The best properties were obtained when the film thickness was 1.5 nm. Regarding the thickness dependence of the underlayer 402, when the thickness of the underlayer 402 was 1.5 nm or more, the on-state current was significantly increased.
  • a silicon thermal oxidation film having a physical thickness of 0.6 to 1.8 nm was mainly produced as the underlayer 402, but in the second embodiment, the underlayer 402 was used.
  • the underlayer 402 was used.
  • a silicon thermal oxide film was formed. By exposing these silicon oxide films to nitrogen plasma, about 5% of nitrogen was introduced into the silicon thermal oxide films to form an underlayer 402 which was a silicon oxynitride film. Thereafter, an HfSiO layer 403 was deposited under the same conditions as in the first embodiment, and a heat treatment was performed to produce a gate insulating film 406 having a high dielectric constant.
  • the equivalent oxide film thickness was about 0.05 nm on average compared to the case where the underlayer 402 without introducing nitrogen was used. It's thin. Furthermore, there was no difference in the hysteresis and Ion characteristics of the CV characteristics with the introduction of nitrogen, and the same results as those shown in Figs. 5 (a) and (b) and Figs. 6 (a) and (b) were obtained. .
  • a gold layer is formed on the underlayer 402 made of a silicon oxide film.
  • cross section As a result of TEM structural analysis, it was confirmed that HfSiO forming the HfSiO film 403 does not crystallize by heat treatment at 800 ° C or lower, but crystallizes by heat treatment at 1000 ° C.
  • the temperature is raised to a temperature of 600 ° C. for 30 to 60 ° C. in an ammonia or hydrogen atmosphere.
  • a long-term heat treatment was performed for a period of 1 minute, followed by a short-time heat treatment for 1 second at a temperature of 1000 ° C.
  • the HfSiO film 403 is used as a metal diffusion source.
  • Zr, Hf is used as a metal element constituting the silicate film as the gate insulating film 406.
  • Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu Even when used as a diffusion source, a high-quality gate insulating film could be produced.
  • the metal compound layer contains the A1 element
  • the gate insulating film is made of metal aluminate.
  • a metal oxide film composed only of the above-described metal element and oxygen can be used as a metal supply source.
  • an Hf nitride (HfN) film was used as a metal diffusion layer as a metal diffusion source.
  • a thermal oxidation treatment was performed to form a silicon thermal oxidation film having a physical film thickness of 1.8 nm as an underlayer.
  • An HfN film was deposited to a thickness of 0.5 nm or 1.
  • the HfN film was formed using a metal Hf target as a target and a mixed gas of argon and nitrogen as a sputtering gas (reaction gas). Thereafter, a heat treatment at a temperature of 500 ° C.
  • the equivalent oxide thickness was evaluated. As a result, when the HfN film thickness was 0.5 nm, the equivalent oxide film thickness was 1.6 nm, and when the HfN film thickness was 1. On m, the equivalent oxide film thickness was 1.8 nm. Was. In particular, under the condition that the HfN film thickness is 0.5 nm, since the Hf metal element diffused into the underlayer and the dielectric constant was increased, the electrical film thickness of the initial silicon thermal oxide film (oxidation The equivalent film thickness of the HfSiON film after the heat treatment was smaller than the equivalent film thickness).
  • the element lifetime (insulating film reliability) estimated from the electrical defects (interface defect density) existing at the interface between the gate insulating film made of HfSiON and the silicon substrate, and the threshold voltage shift accompanying device operation was evaluated.
  • the interface defect density can be reduced to less than 1Z2 compared to devices fabricated with an HfN film thickness of 1.Onm, and the device lifetime (reliability) ) was improved more than 10 times.
  • the hysteresis of the capacitance-voltage characteristics (CV characteristics) within the operating voltage of the transistor could be reduced to 5 mV or less.
  • the physical film thickness is set to 2 By setting it to Onm or less, preferably 1.5 nm or less, it was possible to prevent the metal compound layer 403 from leaving unreacted portions with the underlayer 402.
  • the metal compound layer 403 has a metal nitride property
  • the unreacted portion of the metal compound layer 403 with the underlayer 402 is set by setting the physical film thickness to 1.Onm or less, preferably 0.6 nm or less. I could not leave it.
  • FIGS. 7A to 7D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the fifth embodiment in the order of steps.
  • a silicon thermal oxide film having a physical film thickness of 1.8 nm was formed on a silicon substrate 701 to form an underlayer 702.
  • an HfSiO film 703 having a physical thickness of 4. Onm was deposited on the underlayer 702 by a CVD method.
  • a heat treatment was performed at a temperature of 900 ° C. in a nitrogen atmosphere, and an interface silicate reaction was allowed to proceed to form a gate insulating film 704.
  • the lower portion of the HfSiO film 703 reacts with the underlying layer 702 made of a silicon thermal oxidation film to form a gate insulating film 704, but the upper portion of the HfSiO film 703 does not react. It remained.
  • this remaining portion is referred to as unreacted Hf SiO region 705 !!
  • the physical thickness of the unreacted Hf SiO region 705 was 3 nm.
  • the unreacted HfSiO region 705 was peeled off and removed by wet etching using a diluted hydrofluoric acid solution or an aqueous ammonia hydrogen peroxide solution.
  • a heat treatment was performed in a diluted oxygen atmosphere at a temperature of 850 ° C. for 30 seconds.
  • the hysteresis was about 100 mV in the Hf SiO film in which the unreacted Hf SiO region 705 remained.
  • the hysteresis was about 5 mV.

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  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

L'invention a trait à un procédé, qui consiste : à former, à l'aide d'un procédé RTO, une couche de base (103) constituée d'un oxyde de silicium sur un substrat de silicium (101), ladite couche de base (103) étant formée de manière à présenter une épaisseur d'au moins 1,5 nm ; à former ensuite une couche d'un composé métallique (104), en déposant une épaisseur de 0,5-1,0 nm de nitrure de hafnium sur la couche de base (103), à l'aide d'un procédé de dépôt chimique en phase vapeur ; à soumettre le produit obtenu à un traitement thermique dans une atmosphère d'hydrogène, de façon que le hafnium se diffuse dans la couche de base (103) à partir de la couche de composé métallique (104) et soit transformé en silicate, ce qui génère un film d'isolation de grille (106) ; à soumettre le produit obtenu à un traitement thermique dans une atmosphère oxydante. Lesdits traitements thermiques sont réalisés de manière que le hafnium n'atteigne pas l'interface entre le substrat de silicium (101) et le film d'isolation de grille (106).
PCT/JP2004/015128 2003-10-15 2004-10-14 Procede de fabrication d'un dispositif semi-conducteur Ceased WO2005038929A1 (fr)

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JP2005217409A (ja) * 2004-01-29 2005-08-11 Samsung Electronics Co Ltd 半導体素子の多層誘電体構造物、半導体及びその製造方法
JP2006319091A (ja) * 2005-05-12 2006-11-24 Renesas Technology Corp 半導体装置の製造方法
JP2007123662A (ja) * 2005-10-31 2007-05-17 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2007243049A (ja) * 2006-03-10 2007-09-20 Tokyo Electron Ltd 半導体装置
JPWO2006009025A1 (ja) * 2004-07-20 2008-05-01 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP2008311464A (ja) * 2007-06-15 2008-12-25 National Institute Of Advanced Industrial & Technology 半導体装置とその製造方法
JP2009141168A (ja) * 2007-12-07 2009-06-25 Panasonic Corp 半導体装置及びその製造方法
JP2010045210A (ja) * 2008-08-13 2010-02-25 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2011029478A (ja) * 2009-07-28 2011-02-10 Canon Anelva Corp 誘電体膜、誘電体膜を用いた半導体装置の製造方法及び半導体製造装置
US7902019B2 (en) 2001-02-02 2011-03-08 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
KR101024962B1 (ko) 2007-12-27 2011-03-25 캐논 아네르바 가부시키가이샤 절연막의 형성방법
JP2012522379A (ja) * 2009-03-26 2012-09-20 東京エレクトロン株式会社 低減された等価酸化膜厚を有する高誘電率ゲートスタックの形成方法
WO2024048764A1 (fr) * 2022-08-31 2024-03-07 株式会社Gaianixx Cristal, structure feuilletée, élément, dispositif électronique, appareil électronique et système

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JP2002314074A (ja) * 2001-02-06 2002-10-25 Matsushita Electric Ind Co Ltd 絶縁膜の形成方法及び半導体装置の製造方法
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US7902019B2 (en) 2001-02-02 2011-03-08 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
JP2005217409A (ja) * 2004-01-29 2005-08-11 Samsung Electronics Co Ltd 半導体素子の多層誘電体構造物、半導体及びその製造方法
JPWO2006009025A1 (ja) * 2004-07-20 2008-05-01 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP2006319091A (ja) * 2005-05-12 2006-11-24 Renesas Technology Corp 半導体装置の製造方法
JP2007123662A (ja) * 2005-10-31 2007-05-17 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2007243049A (ja) * 2006-03-10 2007-09-20 Tokyo Electron Ltd 半導体装置
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JP2009141168A (ja) * 2007-12-07 2009-06-25 Panasonic Corp 半導体装置及びその製造方法
KR101024962B1 (ko) 2007-12-27 2011-03-25 캐논 아네르바 가부시키가이샤 절연막의 형성방법
JP2010045210A (ja) * 2008-08-13 2010-02-25 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2012522379A (ja) * 2009-03-26 2012-09-20 東京エレクトロン株式会社 低減された等価酸化膜厚を有する高誘電率ゲートスタックの形成方法
JP2011029478A (ja) * 2009-07-28 2011-02-10 Canon Anelva Corp 誘電体膜、誘電体膜を用いた半導体装置の製造方法及び半導体製造装置
WO2024048764A1 (fr) * 2022-08-31 2024-03-07 株式会社Gaianixx Cristal, structure feuilletée, élément, dispositif électronique, appareil électronique et système
JPWO2024048764A1 (fr) * 2022-08-31 2024-03-07
JP7784766B2 (ja) 2022-08-31 2025-12-12 株式会社Gaianixx 積層構造体、電子デバイス、電子機器及びシステム

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