Audio power amplifier
The present invention relates to electric power amplifiers, and in particular relates to an amplifier for converting a digital audio signal into a power output signal and to a method for converting a digital audio signal into a power output signal. It is especially suited for portable electronic audio devices such as portable phones, portable CD players or portable radio receivers. Electronic audio devices require power amplifiers for electronic signals. Earlier audio devices used so-called Class-A or Class-AB power amplifiers. These are analog circuits that consume significant amounts of power and have a low efficiency of typically not more than 60 %. This is disadvantageous, especially for portable electronic audio devices such as portable phones, portable CD players or portable radio receivers, which should be small, light, powerful and power efficient. These disadvantages have been largely overcome by the so-called Class-D power amplifiers. A Class-D amplifier has typically two output transistors that are operated as switches. Its power dissipation is low and its efficiency high - typically 80 to 90 % -, thus requiring less power from the power supply and smaller heat sinks for the amplifier. These are important advantages in portable battery-powered devices. The classical implementation of a Class-D amplifier 101 is shown in Figure 1. An analog input audio signal to be amplified is fed into the amplifier 101 via an input line 102. The amplifier 101 uses a pulse- width-modulation (PWM) configuration, i.e., consists of an analog PWM stage 104 and a power output stage 105. The PWM stage 104 comprises a comparator 143 with two input lines 141, 142. A first input line 141 is for the analog audio input signal. A second input line 142 is connected to an output of a clock 144 generating a reference signal 145, typically a triangle or sawtooth wave, with a reference frequency fk which is much higher than the frequency of the audio input signal. The output of the comparator 143 is used to drive the power output stage 105 comprising two transistors 151 and 152, e.g., metal-oxide-
semiconductor field-effect transistors (MOSFETs), which operate as switches. Gate drivers 153 and 154 may be connected in series to the gates of the transistors 151, 152. An output line 106 is for the amplified pulse-width-modulated output signal. A passive low-pass filter (not shown) is typically used for filtering out the reference frequency fR, its harmonics and frequency bands around these frequencies. Thus, an amplified analog audio signal is reconstructed that can be used for driving a load, e.g., a loudspeaker (not shown). The load may be a part of the low-pass filter. The disadvantage of the Class-D amplifier 101 shown in Fig. 1 is that the input audio signal must be analog. In today's digital-enhanced-cordless- telecommunications (DECT) baseband processors, the audio signal is processed by a digital signal processor (DSP) and is available in pulse-code-modulated (PCM) form, i.e., digital. There is then the need to design a digital/analog (D/A) stage, normally a high-performance one, to feed the audio signal into the PWM input 141 in analog form. It is complicated to convert the signal into analog format and then digitalize it again. To exploit the fact that the audio signal is available already in PCM form, the analog PWM modulator 104 must be transferred to the digital domain. It is impossible to simply use a digital PWM since the reference frequency required to generate the modulation signal would become too high. For example in the field of DECT, the PCM input audio signal has a word length of N = 16 bit and a sampling frequency of fs == 8 kHz. This would require a reference signal with a reference frequency of fR = 2N-8 kHz = 524 MHz, which is certainly too high. For a higher sampling frequency, a still higher reference frequency fR would be required. It has been proposed to use a sigma-delta noise shaper to convert the PCM input audio signal into a 1-bit bitstream, directly driving the gate drivers. A circuit 101 ' of this type is shown in Figure 2. It consists of a noise-shaping stage 103 comprising a sigma-delta noise shaper 132, and a power output stage 105 as described with reference to Fig. 1. An interpolator 131 is connected in series to the input of the sigma-delta noise shaper 132. The main disadvantage of this circuit 101' is the fact that, in order to obtain the same signal-to-noise ratio (SNR) at the input and at the output of the noise-shaping stage 103, a high oversamplmg ratio K is needed, ending with a high switching frequency of the output MOSFETs 151, 152. This will be illustrated in the following numerical example.
For a uniformly quantized PCM, the SNR is given by the following formula: SNR [dB] = 1.76 + 6.02-N + lO-logιo(K) , (1) where N is the word length in bits and K is the oversampling ratio. For N = 16 bit and K = 1, Eq. (1) gives SNR = 98 dB. For a noise shaper 132, Eq. (1) has to be modified to take into account the noise-shaping effect. For a second-order loop, the SNR increases by approximately 15 dB per doubling of K. Thus, the SNR for a noise-shaper is given by SNR [dB] = 1.76 + 6.02-N + 15-log2(K) . (2) The SNR of the 2nd order noise shaper 132 is preferably chosen to be equal to that of the incoming PCM signal. In the example with an input word length of N = 16 bit, Eq. (1) yields an SNR of 98 dB. Inserting this SNR and a word length of N' = 1 bit into Eq. (2) and resolving for K, one gets K = 64. However, Eq. (2) is somehow optimistic. Simulations of the noise-shaper circuit 132 show that in reality, higher oversampling ratios K have to be chosen in order to achieve an SNR of 98 dB. Consequently, K = 108 is chosen. With this oversampling ratio and a sampling frequency of fs = 8 kHz, a bitstream frequency of K fs = 864 kHz results. This frequency is too high for the output MOSFETs 151, 152. Another disadvantage of this circuit 101 ' is related to the statistical property of the bitstream. The noise-shaped bitstream is pulse-density modulated, which corresponds to a higher number of transitions compared to a PWM scheme. This causes a decrease of efficiency and an increase of the distortion. Moreover, the jitter sensitivity is higher.
It is therefore an object of the invention to provide a power amplifier and a method for power amplification which avoid the aforementioned disadvantages of the prior art. In particular, the power amplifier shall be small, light, powerful and power efficient; its bitstream frequency shall be so low that it can be processed by the MOSFETs in the output stage. This and other objects are solved by the invention as defined in the independent claims. Advantageous embodiments of the invention are defined in the
dependent claims. The invention is based on the idea to depart from the classical Class-D amplifier, to adopt its advantageous qualities and to improve its characteristics by remaining in the digital domain. This is achieved by introducing the following steps: 1. The N-bit-long PCM input signal is upsampled by an inteφolator and noise shaped by a sigma-delta noise shaper.
2. The noise-shaped signal is used as an input for a digital PCM/PWM converter.
3. The output signal of the PCM/PWM converter is fed into a power output stage. The amplifier according to the invention for converting a digital audio signal into a power output signal comprises a noise-shaping stage for noise-shaping the digital audio signal, thus providing a pulse-code-modulated noise-shaped signal; a PCM/PWM converter stage for converting said pulse-code-modulated noise-shaped signal into a pulse-width-modulated signal; and a power output stage for converting said pulse-width-modulated signal into a power output signal. The method according to the invention for converting a digital audio signal into a power output signal comprises the steps of noise-shaping the digital audio signal, thus providing a pulse-code-modulated noise-shaped signal; converting said pulse-code-modulated noise-shaped signal into a pulse-width-modulated signal; and converting said pulse-width-modulated signal into a power output signal. The invention and, for comparison, the prior art are described in greater detail hereinafter relative to the attached schematic drawings.
Fig. 1 shows a block diagram of a classical Class-D power amplifier according to the prior art. Fig. 2 shows a block diagram of an improved Class-D power amplifier according to the prior art. Fig. 3 shows a flow diagram of the method according to the invention. Fig. 4 shows a block diagram of the power amplifier according to the invention.
The method according to the invention is schematically illustrated in the flow diagram of Figure 3. The block diagram of the power amplifier 1 according to the invention is shown in Figure 4. The PCM audio input signal is supposed to have N bits and a sampling frequency fs. This input signal is fed via an input line 2 into a first, noise-shaping stage 3 of the power amplifier 1. The noise-shaping stage 3 comprises an inteφolator 31 for upsampling the sampling frequency to K-fs, where K is the oversampling ratio. The noise-shaping stage 3 further comprises a sigma-delta noise shaper 32 which reduces the quantization noise in the audio band by pushing the quantization noise out of the audio band towards higher frequencies. The noise-shaped signal has then M bits, with 1 < M < N, and a sampling frequency K-fs. In other words, the noise-shaping stage 3 increases the sampling frequency, decreases the number of bits and reduces the noise in the audio band. The noise-shaped signal is fed via an input line 41 into a second, PCM/PWM converter stage 4. This stage 4 comprises a counter 44 which provides on a reference input line 42 a reference signal with a reference frequency fR, and a comparator 43 for comparing the PCM input signal with the counter signal. The reference frequency must be at least f > 2M-K-fs. The PWM signal on a PWM output line 46 is then used to drive a power output stage 5, just like in a conventional Class-D amplifier. The output stage 5 comprises two gate drivers 53, 54 connected in series to two transistors 51, 52, respectively, which are preferably MOSFETs. In the following, a numerical example will be considered for the power amplifier 1 according to the invention, comprising a 2nd order noise shaper 32. Again, the SNR is chosen to be 98 dB in order to match the SNR of the incoming PCM signal, and the sampling frequency shall be fs = 8 kHz. With a word length of M = 6 bit at the noise-shaper output, Eq. (2) yields K = 18. Again, this theoretical oversampling ratio is too optimistic and is realistically increased to K = 32. The sampling frequency of the noise-shaped signal is K-fs = 256 kHz, which is acceptable for driving the output MOSFETs 51 , 52. The reference frequency for the PCM/PWM stage 4 required in this numerical example is only fR = 2M-K-fs = 16 MHz, which is also a realistic value. The invention is suitable for all devices that require an audio power
output stage and high efficiency, e.g., portable electronic audio devices. To exploit the complementary metal-oxide-semiconductor (CMOS) digital manufacturing processes and to decrease the development time, the amplifier is as much as possible digital; the "analog" part is limited to the design of the output MOSFETs and their gate drivers. Thus, the amplifier can be made small, light, powerful and power efficient. This is achieved by processing the PCM input signal in the digital domain.