WO2005015653A1 - Field effect transistor - Google Patents

Abstract

The present invention relates to field effect transistor comprising source and drain electrodes separated by a semiconductor body region, and a gate electrode separated from said semiconductor body region by a gate insulator region, wherein the gate insulator region comprises a non-crystalline, preferably solutionprocessed, organic like material. Furthermore, the present invention also relates to a method of fabricating a field effect transistor comprising the steps of- a) forming a gate electrode; b) forming a gate insulator region; c) forming a semiconductor body region separated from said gate electrode by said gate insulator region; and d) forming source and drain electrodes separated from each other by said semiconductor body region, such that the gate insulator region comprises a solution processed non crystalline organic like material. A transistor in accordance with an embodiment of the present invention can be used in memory devices to store one bit per one component and the memory is permanent but re-writeable.

Description

FIELD EFFECT TRANSISTOR

Field of the Invention

The present invention relates to a field effect transistor and a method of fabricating the same, and more particularly but not exclusively, a field effect transistor (FET) for use in devices such as smart cards, liquid crystalline displays (LCDs) and organic light emitting displays (OLEDs).

Background to the Invention

A wide range of electronic devices use FETs. For example, organic active matrix drivers for displays (both LCD and OLED) currently rely on memories consisting of a conventional FET and a capacitor. A significant drawback to such memory devices is that they require two components and the memory is volatile due to capacitor leakage.

The working principle of an FET is that the current between source and drain electrodes (which are separated by a semiconductor region) depends on the field present in the transistor, which is itself controlled by applying a voltage to a gate insulator region via a gate electrode. The semiconductor body is separated from the gate electrode by the gate insulator region. When a sufficiently high voltage of a suitable polarity is applied to the gate electrode the associated electric field induces a charged accumulation layer in the semiconductor at the semiconductor-gate insulator interface of the device. Current will flow through the accumulation layer so as to put the device into an "on" state.

For an n-channel FET when a positive voltage is applied to the gate electrode a conducting accumulation layer, that is, channel is induced in the semiconductor body region adjacent to the gate insulator. The result of this is that if a voltage is applied to the drain electrode with respect to the source electrode then a current will flow. This current will flow from the drain to the source (following the convention on direction of current flow), a djacent to the b ody r egion, w ith e lectrons c omprising t he m ajority c harge carriers (i.e. the electrons will flow from the source to the drain). It will be appreciated that for a p- channel FET a negative voltage must be applied to the gate electrode in order to induce an accumulation layer in the semiconductor body, and in this case the majority charge carriers making up the current from the drain to the source will be holes. When the voltage applied to the gate electrode is reduced below a threshold voltage the charged accumulation layer is removed and significant current can no longer flow from the drain to the source electrode through the body region of the FET, although there will still be a very low leakage, that is, "off, current within the semiconductor body.

In order for a conventional FET (i.e. a FET having a dielectric insulating layer) to perform a memory function the voltage to the gate electrode must be sustained for the drain to source current to remain in its "on" state, which is achieved by applying a suitable gate voltage to the transistor incessantly, most typically by using a capacitor to store charge to help maintain the field in the FET. (C. D. Sheraw, et al., "Organic thin-film transistor-driven polymer-dispersed liquid crystal displays on flexible polymeric substrates", Appl Phys Lett. 80, p. 1088-1090 (2002)), (H.E.A. Huitema, et al, "Active-Matrix Displays Driven by Solution-Processed Polymeric Transistors", Adv. Mat. 14, p.1201-1204 (2002)). When a high voltage is applied to the gate electrode of the FET, current is allowed to flow between the drain and the source. A capacitor is charged and stores a- charge equating to a logic high condition. When the gate control voltage is reduced below the threshold value the capacitor retains its charge for a period of time until the capacitor has discharged. In order for the logic high condition on the capacitor to be maintained the device must be periodically refreshed, before the capacitor has discharged significantly. The voltage across the capacitor must be read and if this equates to a logic high the gate voltage of the FET must be pulsed high again, to allow current to flow from the drain to the source, and replace the charge on the capacitor.

Within an active matrix display the voltage applied to the gate electrode of the FET must again be sustained to maintain the drain to source current, that is, to maintain the device in. the "on" state. A capacitor is connected between the gate and source electrodes of the FET. The drain electrode is connected to one of the display electrodes. A separate voltage charges the capacitor such that the voltage at the gate electrode is sustained. To maintain a current to the display electrode it is necessary to periodically refresh the charge on the capacitor to sustain the gate voltage.

One way of overcoming some of the problems encountered when using capacitor-based transistor memory devices is to use a ferroelectric or ferroelectric-like material as the gate insulator. Ferroelectric materials possess a crystalline structure and a thermodynamic phase wherein they display a characteristic hysteresis loop for the electric displacement with respect to the applied electric field while the temperature of the material remains below the Curie temperature of that particular material. When the electric field is increased in one direction the polarity of the material is aligned, and this alignment remains at least in part when the electric field is reduced back to zero. The material retains a remanent polarisation. To reverse this polarisation it is necessary to apply an electric field across the material in the opposite direction.

The FET can then simply be poled by an initially applied voltage, with the insulator acting to keep the FET in the "on" state after the poling voltage is turned off (Tingkai Li et al, "Fabrication and characterization of a Pb₅Ge₃O_n one-transistor-memory device", Appl. Phys. Lett. 79, p. 1661-1663 (2001); M. W. J. Prins et al, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett. 68, p. 3650-3652 (1996).).

The development of new transistor memory devices is of particular interest in applications, such as mobile t elecommunications, where there i s a d esire to 1 ower the p ower c onsumption and n on- volatile memories are desirable. Ferroelectric FETs typically employ an inorganic semiconductor layer in conjunction with an inorganic ferroelectric insulating layer. TTo address problems related to lattice mismatch between the inorganic insulator and semiconductor layers it is often necessary to provide an 'intermediate crystal structure mediating layer', which increases the cost and complexity of FETs incorporating such layers.

More recently, the development of organic memory devices, such as organic smart cards and organic active matrix drivers for displays has lead to the investigation of FETs incorporating organic semiconductors (such devices are referred to as Organic FETs or OFETs). Significant problems have been encountered in fabricating single OFET memory devices using inorganic ferroelectric gate insulators, which do not comprise a capacitor. This is due to the incompatibility of the processing steps required to construct the organic semiconductor layer and the crystal growing process normally required to ensure the insulating layer exhibits ferroelectric behaviour. Unfortunately, many of the resulting devices exhibit unacceptable performance.

Fabrication of an OFET incorporating an inorganic ferroelectric insulator region and an organic semiconductor has been described (G. Velu et al, "Low driving voltages and memory effect in organic thin-film transistors with a ferroelectric gate insulator", A ppl. Phys. Lett. 79, p. 659-661 (2001)). The inorganic insulator material (PbZrTi0₃ (PZT)) was deposited by radio frequency sputtering and then annealed at 625 °C for 30 min, which is both a lengthy and costly process. Moreover, while it would be desirable to incorporate a flexible organic substrate in an OFET (such as that produced by G. Velu et al), the high temperature processing steps required to provide the inorganic ferroelectric insulator region are incompatible with organic substrates since the organic substrate is unlikely to withstand the high temperatures involved (e.g. 625 °C).

A further p ossible a pproach to o vercoming p roblems r elating t o t he fabrication o f O FETs c omprising organic semiconductors and inorganic ferroelectric insulators is to use an organic insulator material. One organic material known to exhibit ferroelectric behaviour is polyvinylidenefluoride (PVDF). This material may exhibit ferroelectricity when formed into films by melt processing followed by stretching. Unfortunately PVDF films processed in that way are typically several microns thick and are therefore not suitable for FET construction which requires much thinner insulator layers to operate at commercially acceptable voltages. Moreover, PVDF films formed in this way are likely to be too rough for incorporation into a FET. Furthermore, the ferroelectric behaviour exhibited by PVDF films is not displayed uniformly across the surface of the film because PVDF films comprise crystalline regions that are ferroelectric, and non-crystalline regions that are not ferroelectric. Such ferroelectric heterogeneity is likely to result in unacceptable performance of a FET incorporating a PVDF film making the use of such films highly unattractive. US-A-2003/0127676 discloses a non-volatile memory device with a ferroelectric gate insulator layer which has been deposited by spin-coating. PVDF and vinylidene fluoride-trifluor ethylene copolymers (P(VDF-TrFE)) are described as suitable materials ^' for the gate insulator layer. While US-A- 2003/0127676 provides no indication of the thickness of the gate insulator layers used, it is envisaged that the use of spin-coating should enable gate insulator layers to be deposited that are thinner than gate insulator layers formed from melt-processed films. However, the gate insulator layers described in US-A- 2003/0127676 are still likely to exhibit ferroelectric heterogeneity because the ferroelectric behaviour of the gate insulator layers will remain limited to the crystalline regions of the gate insulator layer.

Murata et al. (Y. Murata et al, "Ferroelectric behaviour in polyamides of m-Xylylenediamine and dicarboxylic acids", Jpn. J. Appl. Phys. 34, p. 6458-6462 (1995)) describes the electric behaviour of a series of nylon-type polyamide films 8 to 45 μm thick formed by melt processing. The films produced exhibited electric displacement/electric field hysteresis loops characteristic of ferroelectric materials, however, since the films exhibited this behaviour in the amorphous phase they are not strictly ferroelectric materials but should rather be considered as ferroelectric-like materials in line with the definition of this term set out above. Unfortunately, the thickness of Murata' s films alone makes them unsuitable for incorporation in to an OFET device.

An object of the present invention is to at least mitigate at least one or more of problems of the prior art.

Summary of Invention

According to a first aspect of embodiments of the present invention there is provided a field effect transistor comprising source and drain electrodes separated by a semiconductor body region, and a gate electrode s eparated from s aid s emiconductor b ody r egion b y a g ate i nsulator region, wherein the gate insulator region comprises a non-crystalline, preferably solution-processed, organic ferroelectric-like material.

This aspect of embodiments of the present invention thus provides a field effect transistor comprising a non-crystalline, preferably solution-processed, organic insulator region, which exhibits ferroelectric-like behaviour rather than an inorganic insulator region, which exhibits ferroelectric behaviour. The term 'ferroelectric-like' will be used herein to refer to non-crystalline (i.e. amorphous) materials that exhibit a similar electric displacement/electric field hysteresis (D-E), and thereby a similar remanent polarisation, to ferroelectric materials but do not possess a crystalline structure and do not necessarily possess the same thermodynamic properties, that is, a thermodynamic phase associated with ferroelectricity. Ferroelectric materials according to embodiments of the present invention do not exhibit a Curie temperature. Instead, the D-E disappears above the glass transition temperature. Preferably, the polarisation according to embodiments of the present invention is not permanent, that is, it can be changed by application of an appropriate electric field. It is to be understood that the term 'ferroelectric-like' is not intended to encompass electret materials. A transistor in accordance with an embodiment of the present invention can be used in memory devices to store one bit per one component and the memory is permanent but re- writeable. Poling the gate once into the "on" or "off bias state switches the transistor into the respective state. It will remain in that state as long as no new gate bias is applied. When a new gate bias is applied memory can be erased or reset at will. Thus embodiments of the present invention can provide significant advantages over flash memory in terms of the power required to write and delete memory, the speed of operation, and the complexity of construction of the device.

It is envisaged that single transistor, permanent memory devices in accordance with the present invention based on organic materials which are compatible with flexible substrates are likely to find application in the field of organic electronics, for example in organic active matrix displays for use in the mobile telecommunications and various non-mobile electronics markets. A transistor in accordance with an embodiment of the present invention will also be a good candidate for LCD and OLED driver electronics because its fabrication should be compatible with the LCD/OLED fabrication process. Furthermore such devices will no longer incorporate a capacitor. Therefore capacitor leakage will be eliminated and the fabrication of displays (e.g. active matrix displays) which require several thousand pixels will be simplified significantly. Removing the need to refresh the device through not incorporating capacitors which need to be repeatedly refreshed, will reduce the amount of energy drawn from the power supply. This will also improve the performance of smart cards which will not need to be permanently connected to a power supply to refresh memory and will only require power when the memory is altered.

Preferably the ferroelectric-like material comprises at least one type of polymer. Thus, the ferroelectric- like material may be comprised substantially of one type of polymer or may comprise a blend of two or more different types of polymer. The ferroelectric-like material may comprise hydrogen bond donor and hydrogen bond acceptor groups.

The ferroelectric-like material is preferably a polyamide and may be formed from the condensation of a diamine and a dicarboxylic acid. It is preferred that the diamine comprises an aromatic group, more preferably the diamine is xylenediamine and most preferably the diamine is m-xylenediamine. The dicarboxylic acid preferably comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups. The dicarboxylic acid may comprise up to 13 carbon atoms, 5 to 11 carbon atoms or 6 carbon atoms. It will be appreciated by those skilled in the art that MXD6 comprises a ferroelectric-like polarisation hysteresis in its amorphous state due to hydrogen bond alignment see, for example, Y. Murata et al, "Ferroelectric Properties in Polyamides of M-Xylylenediamine and Dicarboxylic-Acids", Jpn. J. Appl. Phys. 32, pp L849-L851, June 1993, which is incorporated herein by reference for all purposes. In a preferred embodiment of this aspect of the invention the ferroelectric-like material comprises repeating unit having the formula:

where n = 4- 11.

More preferably n = 4, in which case the polymer is poly(m-xylylenediamine-alt-adipic acid).

The successful fabrication of a field effect transistor having an insulator region comprised of a non- crystalline solution-processed organic ferroelectric-like material as hereinbefore described is particularly unexpected in view of the fact that the ferroelectric-like properties described by Murata et al. (Y. Murata et al, "Ferroelectric behaviour in polyamides of m-Xylylenediamine and dicarboxylic acids", Jpn. J. Appl. Phys. 34, p. 6458-6462 (1995)) for a family of polyamides were only observed in much thicker melt-processed films and Murata' s work provides no indication that the polyamides described therein would exhibit ferroelectric-like behaviour when processed using techniques such as solution phase deposition, e.g. spin-casting, inkjet printing, or dip coating.

The insulator region should be of sufficient thickness to ensure that it contains no pinholes. For many applications it will be desirable to make the insulator region as thin as practically possible. However, in certain circumstances (e.g. if a larger memory window was required) a slightly thicker insulator region would be desirable. The thickness of the insulator region influences the memory window of the device

(defined as the difference between the gate voltages that turn the device "off and "on"). In preferred embodiments, the thickness of the insulator is influenced by the solution concentration, a fabrication spin speed and solution temperature. It is thought that the solution concentration has a strong effect on the crystallinity of the insulator. Therefore, various thickness can be achieved by varying the above.

Preferably the insulator region has a thickness in the range 50 to 400 nm. Such thicknesses provide a memory window of approximately 5 V to 40 V depending on the application. The insulator region may have a thickness of up to approximately 350 nm. In further preferred embodiments of this aspect of the invention the insulator region has a thickness in the range 100 to 300 nm, more preferably in the range

150 to 250 nm, and yet more preferably a thickness of approximately 210 nm. The insulator region should have a surface roughness, which is as low as possible. Preferably the insulator region has a surface roughness equal to or less than 5 nm.

It is preferred that the semiconductor body region comprises an organic semiconductor material. Alternatively, since inorganic semiconductors are often used in conventional FETs, any known inorganic semiconductor may be used in the device according to the present invention. The semiconductor body region m ay c omprise a p -type s emiconductor m aterial. The s emiconductor b ody r egion m ay c omprise pentacene.

A transistor in accordance with an embodiment of the present invention may additionally comprise a substrate region, which may comprise glass or plastic. The gate electrode preferably comprises indium tin oxide or a synthetic metal (e.g. poly(ethylene dioxythiophene)-poly(styrene sulfonic acid) (PEDOT/PSS)), although any suitable material may be used e.g. polyaniline (PAni) emeraldine salt or a metal as such aluminium or gold. It is preferred that at least one of the source and drain electrodes comprises a material selected from the group consisting of PEDOT/PSS, polyaniline (PAni) emeraldine salt, gold, calcium, silver, magnesium, tin, aluminium, alloys comprising one or more of the aforementioned materials, or any other suitable material.

According t o a second aspect o f e mbodiments o f the p resent invention there i s p rovided a m ethod o f fabricating a field effect transistor comprising the steps of: a) forming a gate electrode; b) forming a gate insulator region; c) forming a semiconductor body region separated from said gate electrode by said gate insulator region; and d) forming source and drain electrodes separated from each other by said semiconductor body region,

such that the gate insulator region comprises a solution processed non-crystalline organic ferroelectric- like material.

It will be evident to the skilled person that steps a)-d) may be carried out in any convenient order to produce the desired transistor structure. For example, the order of steps may be a), b), c), d), or a), b), d), c), or alternatively d), c), b), a).

Being able to form the insulator layer from the solution phase means that the process should be much cheaper and less time-intensive than conventional methods of fabricating transistor devices incorporating crystalline or polycrystalline inorganic materials. Additionally, the inventive method is compatible with the deposition of organic semiconductors on top of the ferroelectric-like non-crystalline gate insulator.

Further steps may be performed so as to modify the structure formed in steps a) - d), e.g. surface modification of the gate insulator, modification of the gate insulator bulk, modification of the electrode/semiconductor interface, modification of the semiconductors etc. The gate insulator region may comprise a plurality of insulator materials.

Suitable ferroelectric-like materials for use in the second aspect of the invention are described above in relation to the first aspect of the invention.

Preferably step b) comprises solution phase deposition, and more preferably step b) comprises spin- casting, although it will be evident to the skilled person that any number of alternative techniques may be used to form the gate insulator region, such as inkjet printing, or dip coating. The spin-casting may be carried out at a speed in the range 100 to 10000 rpm, at a speed in the range 3000 to 5000 rpm, or at a speed of approximately 4000 rpm. It is preferred that the spin-casting is carried out over a period of time in the range 20 seconds to 15 minutes, over a period of time in the range 5 to 11 minutes, or over a period of time of approximately 8 minutes.

It is preferred that the non-crystalline organic ferroelectric-like material is formed from a solution of a precursor of said ferroelectric-like material in a suitable solvent (e.g. hexafluoroisopropanol, formic acid, trifluoroacetic acid and sulfuric acid, phenol/ethanol (as a 4:1 by volume mixture)).

It will be apparent to the person skilled in the art that suitable precursors to the ferroelectric-like material comprise the various embodiments of the ferroelectric-like materials set out above in respect of the first aspect of the present invention but which cannot be termed ferroelectric-like materials since they will not exhibit ferroelectric-like properties by virtue of being in a solution phase.

Suitable precursors thus include a polymer or a blend of the two or more different polymers, which may comprise hydrogen bond donor and acceptor groups. A precursor is preferably a polyamide and may be formed by condensation of a diamine and dicarboxylic acid. It is preferred that the diamine comprises an aromatic group, more preferably the diamine is xylenediamine and most preferably the diamine is m- xylenediamine. The dicarboxylic acid preferably comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups. The dicarboxylic acid may comprise up to 13 carbon atoms, 5 to 11 carbon atoms or 6 carbon atoms.

In a preferred embodiment of this aspect of the invention the precursor comprises a repeating unit having the formula:

where n = 4 - 11.

More preferably n = 4, in which case the polymer is poly(m-xylylenediamine-alt-adipic acid).

The concentration of the precursor in said solution is preferably in the range 20 to 70 mg/ml. More preferably the concentration of the precursor in said solution is in the range 30 to 60 mg/ml, and most preferably the concentration of the precursor in said solution is approximately 35 mg/ml.

The solvent is preferably an organic acid, or an organic solvent. The solvent may comprise an aromatic group and the solvent is preferably o-cresol or m-cresol. It is particularly preferred that the solvent is m- cresol. While the precursor may be dissolved in the solvent at room temperature (i.e. a temperature of approximately 20°C), given a sufficient period of time, it is preferable that the precursor is dissolved in the solvent at a temperature in the range 20 to 70 °C, more preferably at a temperature in the range 40 to 60 °C, and yet more preferably at a temperature of approximately 50 °C.

Preferably the solution of the precursor is filtered prior to formation of the gate insulator region. The solution of the precursor may be filtered at a temperature in the range 50 to 100°C prior to formation of the gate insulator region. Moreover, the solution of the precursor may be filtered at a temperature in the range 70 to 80°C prior to formation of the gate insulator region. The solution of the precursor may be filtered through any desirable number of suitable filters. Preferably the solution of the precursor is filtered through a first syringe-mounted filter, which preferably has a pore diameter of approximately 5 μm. It is preferred that the solution of the precursor which has been filtered through the first syringe-mounted filter is then filtered through a second syringe-mounted filter having a narrower pore diameter than the first filter. The second syringe-mounted filter may have a pore diameter of approximately 0.45 μm.

The semiconductor body region may be formed in step c) by thermal evaporation or spin casting.

It is preferred that the gate electrode is formed at least in part on a substrate region. It is further preferred that the gate insulator region is formed at least in part on the gate electrode. The semiconductor body region may be formed at least in part on the gate insulator region.

Brief Description of the Drawings Embodiments of the present invention will now be described, by way of example only, with reference to the following non-limiting examples and accompanying figures in which: figure 1 is a schematic representation of a transistor device in accordance with a first embodiment; figure 2 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how to turn the device "on" by applying a gate voltage; figure 3 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how the device remains in the "on" state when the gate voltage is zero; figure 4 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how to turn the device "off; figure 5 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how the device remains in the "off state when the gate voltage is zero; figure 6 is a circuit diagram representing the arrangement of apparatus used to test the device of figure 1 prepared in accordance with examples 1 and 2; figure 7 is a graphical representation of the transfer characteristics of the device of figure 1 prepared in accordance with example 1; figure 8 is a graphical representation of the transfer characteristics of the device of figure 1 prepared in accordance with example 2; figure 9 illustrates transfer characteristics according to embodiments of the present invention; figure 10 depicts AFM imges of MXD6 spherulites; figures 10(a) and 10(b).10 x 10 μm² AFM images of

MXD6 spherulites in the unwanted crystalline phase spun from a 40 g/1 solution; (a) 2D image shows spherulites and the grain boundaries in between, (b) 3D profile of the same image, visualizing the roughness of 18 nm root-mean-square, 150 nm base to peak; figure 11 shows AFM images of amorphous MXD6 layers according to embodiments; Figures 11(a) and 11(b).10 x 10 μm² AFM images of amorphous MXD6 layers, (a) Cast from a 50g/l solution, roughness:

0.8 nm RMS. (b) cast from a 45 g/1 solution, roughness: 2 nm RMS, due to an onset of crystallinity; and figure 12 illustrates memory retention of devices according to embodiments of the present invention.

Memory retention of the "on" and "off state for "FerrOFET" device 1, depicted as currents vs. time. The

"off state current is extrapolated beyond the first four hours. Detailed Description of Preferred Embodiments

The basic construction of a field effect transistor in accordance with a first embodiment is illustrated schematically in figure 1. A transistor 1 comprises a glass substrate 2 with an indium tin oxide gate electrode 3 formed thereon. A thin layer of a non-crystalline gate insulator material 4, MXD-6, is supported on the substrate/gate electrode layer 2, 3. A semiconductor layer 5 comprised of a p-type organic semiconductor, pentacene, is supported on the insulator layer 4, and gold source and drain electrodes 6, 7 are formed on the semiconductor layer 5. Details of two non-limiting examples of methods for fabricating the transistor 1 are set out below in examples 1 and 2.

Figure 2 shows the operation of switching the transistor 1 on when the transistor has been prepared in accordance with example 1. The device as drawn is a p-channel FET, but it will be appreciated that this embodiment i s f or i llustration o nly a nd a transistor in a ccordance w ith an e mbodiment o f the present invention may also comprise an n-channel FET. If the voltage between the source 6 and the drain 7 is kept constant, a current may flow between the drain 7 and the source 6 if an accumulation layer is induced in the body region 5. -40V is applied between the gate region 3 and the body region 5 polarising the insulator layer 4. The effect is to induce an accumulation layer in the body region 5 adjacent the insulator layer 4 between the drain 7 and the source 6. Arrows 8 show the insulator layer 4 being polarised in a first direction creating an electric displacement in a first direction i.e. from the gate region 3 to the body region 5. The arrows 8 point from positive to negative polarity. Thus the current flowing between the drain and the source increases. For a p-channel transistor in a ccordance with the present invention poling the gate voltage to a negative voltage will polarise the ferroelectric-like material layer in a first direction, which induces holes in the semiconductor body region by driving out electrons allowing current to flow. It will be appreciated that for an n-channel transistor in accordance with the present invention the polarity of the voltage that must be applied to the gate to create an accumulation layer will be reversed to that described above. Furthermore, for current to flow in an n-channel transistor in the "on" state the drain voltage must be reversed. Additionally for an n-channel transistor in accordance with an embodiment of the present invention the polarisation of the insulator that induces an accumulation layer in the semiconductor body region will be reversed.

Figure 3 shows that when the voltage applied to the gate region 3 is returned to ground the insulator layer 4 retains a remanent polarisation and the associated electric displacement in the body region 5 remains. The accumulation layer remains and current continues to flow between the drain 7 and the source 6. Arrows 9 show that the insulator layer 4 remains polarised in the first direction creating an electric displacement in the first direction, in the absence of an applied gate voltage corresponding to the remanent polarisation. When using pentacene as the semiconductor the majority of charge carriers will be holes.

Figure 4 shows that when 40V is applied between the gate region 3 and the body region 5 of the transistor 1 prepared in accordance with Example 1 the polarity of the insulator layer 4 reverses. This has the effect of removing the accumulation layer in the body region 5 and reducing the current flowing from the drain 7 to the source 6. Arrows 10 show the insulator layer 4 being polarised in a second direction, opposite to the first direction creating an electric displacement in the second direction. If the gate voltage is then poled to a positive voltage the electric displacement of the ferroelectric-like material layer is first zeroed when the applied positive voltage is large enough to reach the coercitive field of the ferroelectric-like material and then reversed when the positive voltage is increased beyond the voltage required to reach the coercitive field. The effect is that the accumulation layer is removed and therefore the current that can flow from the drain to the source is considerably reduced and the device 1 is in the "off state.

Figure 5 shows that when the voltage applied to the gate region 3 is returned to zero the insulator layer 4 retains its remanent polarisation while the accumulation layer is removed, inhibiting current flow between the drain 7 and the source 6 and therefore the device remains in the "off state. Arrows 11 show that the insulator layer 4 remains polarised in the second direction creating an electric displacement in the second direction, in the absence of an applied gate voltage.

From the above description it will be evident to the skilled person that the inventive device may store a logical high or low condition depending on the direction in which the gate has most recently been poled.

To read this logic value a voltage is applied to the drain region with respect to the source region. A current sensor senses whether the current flowing through the transistor is high or low and registers a logic high or logic low condition respectively. Alternatively, if the transistor is used in an active matrix display, a display pixel will light-up or not light-up. In essence, during use the device 1 would be cycled between the situations shown in Figures 3 and 5. This approach has significant advantages over the traditional use of a conventional FET in conjunction with a storage capacitor for memory devices. It does not involve a capacitor to store the charge, which may discharge over time. As such a transistor in accordance with an embodiment of the present invention does not need to be periodically refreshed in order to store the logic state. The circuit will thus require no power other than during a read or write operation as in accordance with conventional ferroelectric gate insulator FETs.

Transistors 1 prepared in accordance with Examples 1 and 2 were tested using two Keithley 2400 (denoted 12 in figure 6) source and measure units, one for applying a gate voltage, and one for applying a drain voltage and simultaneously measuring the resulting drain current. The ground of the two Keithley units 12 was linked and connected to the source contact. Note that, in figure 6, the electronic symbol of a p-type, accumulation mode MESFET has been used to represent the inventive device 1 under test as we are currently unaware of a standardised symbol for a ferroelectric FET. The memory effect of the transistor 1 was characterized by holding the drain voltage constant and varying the gate voltage while reading the current between source and drain. For transistor 1 prepared according to example 1 a so-called memory window of about 40V was observed, while the current between gate and source was less than 0.1 nA (minimum resolution of the Keithley 2400) at all times. For transistor 1 prepared according to Example 2 a memory window of around 20V was observed. The results of these tests are shown in Figures 7 and 8 for device 1 prepared in accordance with Examples 1 and 2 respectively. The upper section of figure 8 shows the results of the above tests conducted at a scan speed of 0.25 V/s and the lower section of figure 8 shows the results depicted in the upper section of figure 8 (shown as 'x') overlaid with results obtained using a scan speed of 0.50 V/s (shown as '+'). The two memory hysteresis curves illustrated in the lower section of figure 8 are essentially the same which illustrates that the memory window of the device 1 in accordance with an embodiment of the present invention is due to a genuine remanent polarisation that does not depend on the write or read speeds.

Such high voltages were used when testing the device 1 prepared in accordance with example 1 due to the thickness of the insulator layer. The thickness of the layer was chosen to ensure that it did not contain any pinholes. The results presented in relation to the device 1 prepared in accordance with example 2 illustrate that the method forming the second aspect of the present invention is eminently suitable to be adapted to produce thinner insulator layers, which use smaller gate voltages and provide smaller memory windows.

Ferroelectric-like behaviour, and the hysteresis associated with it, are visualized by a gate-sweep transfer characteristic, where the voltage between source and drain is held constant, and the gate voltage is swept from a positive voltage to a negative voltage and back. Figures 7 and 8 show the associated transfer characteristic of the transistor 1 prepared in accordance with examples 1 and 2 respectively. Referring to figure 7, starting at point 13 this shows a device in the "off state with no voltage applied to the gate and minimal leakage current flowing from the drain to the source. When the voltage applied to the gate is ramped to -40V the drain to source current increases to point 14. As the gate voltage is returned to zero

(point 15) the drain to source current reduces slightly as the electric displacement is lower resulting from the polarised insulator layer compared to that present when the gate voltage is at -40 V. A s the gate voltage is ramped to +40V the drain / source current decreases to point 16, which is substantially the same current level as at point 13. As the positive gate voltage is removed the drain / source current remains low.

The key feature of the behaviour of the device 1 prepared according to Example 1 as depicted in figure 7 is that the current at point 15 (after negative pulsing of the gate voltage) is 5.5 times higher than at point 13 (after positive pulsing of the gate voltage) even though the gate voltage at points 13 and 15 is zero. Thus, device 1 prepared according to Example 1 exhibits a 'memory ratio' of 5.5. The term 'memory ratio' shall be used herein to refer to the ratio of the source-drain current at zero gate voltage after negative pulsing of the gate voltage compared to the source-drain current at zero gate voltage after positive pulsing of the gate voltage. A memory ratio of 5.5 is a sufficient variation in current for a current sensor to register the difference between high and low current and thus record logic high and logic low respectively thus enabling the device 1 of Example 1 to perform a memory function. The device 1 prepared according to Example 2 as depicted in the upper section of figure 8 exhibits a significantly increased memory ratio of 200, which represents a major improvement in performance and is comparable to conventional inorganic ferroelectric transistors. In view of the high remanent polarisation of 60 mC/cm² reported for MXD-6 (Y. Murata et al, Jpn. J. Appl. Phys. 32, L849 (1995)) the theoretical limit for the memory ratio of transistors using an MXD-6 gate insulator layer is over lxl 0⁵. Thus, it is envisaged that the methods described in Examples 1 and 2 can be adapted, whilst still falling within the scope of the method forming the second aspect of the present invention, to provide devices in accordance with an embodiment of the first aspect of the present invention exhibiting further significant improvement in performance.

Figures 1 - 5 show the transistor 1 constructed as a planar FET with the gate electrode lowermost on the substrate. The insulator, semiconductor body and drain / source electrodes are shown as being placed on top of one another working upwards. It will be clear to the appropriately skilled person that a transistor in accordance with an embodiment of the present invention may take any number of physical forms, in common with other forms of both ferroelectric transistors and traditional FETs. The form of the device can be controlled by choosing a particular order for steps a) to d) as previously defined for fabricating the device. A transistor in accordance with an embodiment of the present invention may include a planar layer o f s emiconductor m aterial d eposited on t op o f an i nsulator m aterial a s shown i n figures 1 1 o 5, however, planar structures with the gate uppermost may also be formed. Alternatively trench structures wherein the gate is formed in a trench etched into the body of the semiconductor through the source electrode and / or the drain electrode, and separated from these by an insulator layer lining the gate trench may be constructed.

Field effect transistor devices in accordance with embodiments of the present invention can be prepared according to the following non-limiting examples.

EXAMPLE 1

Step 1 - Substrate And Gate Electrode

A glass substrate was purchased with indium-tin-oxide (ITO, a conductive, transparent metal oxide) sputtered upon it.

The ITO was patterned using the following process. The parts of the ITO electrode to be preserved were coated with a protective acid-resistant material in solution (which could subsequently be removed by acetone). The protective layer was then dried and the substrate immersed in 30 % hydrochloric acid for 6 minutes to remove the non-protected ITO. The protective layer was then removed by immersion in acetone.

The substrate was cleaned using the following procedure. Ultrasonic bath cleaning in acetone for 5 minutes followed by ultrasonic bath cleaning for 20 minutes in a 70 °C solution of deionised water with 3 % Helmanex cleaning agent. The substrate was then washed with de-ionised water and subjected to further ultrasonic bath cleaning in deionised water at 70 °C for 20 minutes. Finally, the substrate was washed with de-ionised water and then underwent ultrasonic bath cleaning in a 50 °C methanol bath for 15 minutes. Step 2 - Gate Insulating Layer

A polyamide polymer MXD-6 and m-Cresol were combined in a ratio of 50 mg of MXD-6 per 1 ml of m- Cresol and the m-Cresol heated to 50 °C and stirred to accelerate the dissolving process. Complete dissolution of MXD-6 pellets yielded a very viscous solution of MXD-6. Dissolution takes between 8 and 12 hours depending on the exact temperature of the m-Cresol. If a different form of MXD-6 were used, such as powdered MXD-6 rather than pellets, the dissolution time would be significantly less than 8 hours.

The MXD-6 solution was then hot-filtered at 70 - 80 °C through a syringe with a fastened syringe filter of 5 μm pore diameter. The MXD-6 solution was then spun cast onto the glass-ITO substrate, which had been preheated to the same temperature as that of the solution (i.e. approximately 70 °C), at 4000 rpm for 8 minutes. Finally, the substrate with the gate insulator layer deposited thereon was placed in a vacuum oven at 1 Torr and 50 °C for 24 hours to let any remaining m-Cresol and humidity evaporate. This process provided a layer of MXD-6 of approximately 350 nm thickness with less than 5 nm surface roughness.

Step 3 - Semiconductor Layer

Pentacene was placed into a quartz basket, which in turn was placed into a compatibly shaped tungsten filament housed in an evaporation chamber. The substrate with the gate insulator deposited thereon was placed into the chamber approximately 12 cm from the quartz basket with the gate insulator side facing the opening of the basket. The chamber was then evacuated to a pressure of 2xl0^"6 Torr and pentacene thermally evaporated onto the gate insulator at a rate of 0.5 nm/s.

Step 4 - Source And Drain Electrodes

The quartz basket and tungsten filament from step 3 were replaced with a molybdenum boat and 1 cm of 0.5 mm gold wire placed into the boat. The substrate having insulator and semiconductor layers deposited thereon was placed 12 cm from the boat and a shadow mask positioned between the boat and the substrate so as to define electrode sizes of 2 mm x 2 mm (for both source and drain electrodes) and with channel lengths on one mask of 20, 40, 60, or 80 μm to provide four pairs of electrodes. Gold was then evaporated at a pressure of 2xl0^"6 Torr and a rate of 0.1 nm/s to provide gold electrodes having a thickness of approximately 100 nm.

EXAMPLE 2 Step 1 - Substrate And Gate Electrode

A glass substrate having an ITO gate electrode formed thereon was cleaned in accordance with the method described in Step 1 of Example 1.

Step 2 - Gate Insulating Layer

A gate insulator layer was formed in accordance with Step 2 of Example 1 subject to the following two differences. First, polyamide polymer MXD-6 and m-Cresol were combined in a ratio of 35 mg of MXD- 6 per 1 ml of m-Cresol. Second, the MXD-6 solution formed by dissolution of MXD-6 in m-Cresol was initially hot-filtered at 70 - 80 °C through a syringe with a fastened syringe filter of 5 μm pore diameter and subsequently hot-filtered through a syringe with a fastened syringe filter of 0.45 μm pore diameter. This process provided a layer of MXD-6 of approximately 210 nm thickness .

Step 3 - Semiconductor Layer

A semiconductor layer was formed as described in Step 3 of Example 1 subject to the following differences. The evaporation chamber was evacuated to a pressure of 8x10^~7 Torr and pentacene was thermally evaporated onto the gate insulator at a rate of 0.3 nm/s.

Step 4 - Source And Drain Electrodes

Source and drain electrodes were formed as described in Step 4 of Example 1 save for the fact that gold was evaporated at a rate of 0.2 nm/s to provide the gold electrodes.

FETs a ccording to e mbodiments o f t he p resent i nvention c an a lso b e r ealised u sing t he e mbodiments described in the paper below.

"Raoul S chroeder, L eszek A . M ajewski, M onika V oigt, and M artin Grell, " Memory p erformance and retention of an all-organic ferroelectric-like memory transistor"

Abstract — We have built a non-volatile memory field-effect transistor (FET) based on organic compounds. The memory effect is provided by a polymer that exhibits ferroelectric-like characteristics in its amorphous phase - allowing the transistor to be built using techniques developed for organic transistors. The memory exhibits channel resistance modulations and retention times close in performance to inorganic ferroelectric FETs (FEFETs), yet at a small fraction of the cost, suitable for low-cost circuitry.

Index Terms — ferroelectric memory, non-volatile memory, organic compounds, plastics INTRODUCTION

ORGANIC (0PT0-)ELECTR0NICS have received substantial research and development attention from academia [1-3] and industry [4-6] during the last two decades. In recent years, organic FETs (OFETs) were of particular interest [7-9], due to the possibility of producing them very inexpensively and making them flexible, paving the way for flexible and disposable electronics. Owing to the applications of these transistors, current organic memory solution are unsuitable as they are either based on capacitors, thus volatile and power intensive, or necessitate very high voltages for the writing process, with retention times of less than three hours [10-11].

In inorganic electronics, FEFETs have been researched intensively for several decades to achieve high integration single transistor memories with very long memory retention times [12-16]. Efforts have been made to integrate inorganic ferroelectrics with organic semiconductors to open the world of organic electronics to FEFETs, yet have thus far produced devices with extremely poor channel resistance modulation [17], albeit with respectable retention times [18]. More importantly, the concept of prystalline ferroelectrics is not truly compatible with organic electronics, as the deposition is difficult and costly, and the necessary annealing steps are too high in temperature for organic semiconductors and flexible substrates.

We have recently shown a memory transistor that bridges the gap between expensive inorganic ferroelectrics and cheap, flexible OFETs, the "FerrOFET" [19]. For the "FerrOFET", we rely on a well- commercialized polymer, poly-(m-xylylenediamine-alt-adipic acid), better known as MXD6, which has been shown to exhibit a ferroelectric-like polarization hysteresis in its amorphous state due to hydrogen bridge b ond a lignment [ 20] . F erroelectric-like means t hat t he d isplacement v ersus e lectric f ield ( D-E) hysteresis exhibits the same shape as typical ferroelectric materials; yet the material does not exhibit a thermodynamic phase or crystallinity associated with ferroelectricity. The ferroelectric-like property also does not show a Curie temperature; instead the D-E hysteresis disappears above the glass transition temperature. Previously, the "FerrOFET" exhibited a memory ratio of 200 and a retention time of a few hours [19]. In this letter we show that through careful process parameter control, performance can be highly improved see [figure 9], which shows transfer characteristics of the "FerrOFET" device 1. At zero gate voltage, the memory ratio is 2.7 x 10⁴. The dashed curve is the first sweep in the device lifetime, whereas the dashed and dotted curves were measured at later times. Inset: Transfer characteristic for device 2 with a current memory ratio of 5 x 10².

Experimental

Indium-tin-oxide (ITO) covered glass slides were etched in hydrochloric acid (20%) to define the ITO gate electrodes. They were subsequently cleaned in de-ionized water and in an oxygen plasma chamber. To be most compatible with OFET production technologies, MXD6 was deposited from a solution, in contrast to rapid quenching from a melt. MXD6, obtained from the Mitsubishi Gas Company and used-as-received, was dissolved in m-Cresol (99.3%, Aldrich) and filtered. As m-Cresol has a high boiling point of over 200 C, the solution was spin-cast at slightly elevated temperatures of around 40-60 C. While solid MXD6 films stay amorphous below 150 C, films cast from solution can crystallize at room temperature, in the form of hexagonal spherulites (cf. [figure 10]), i.e. for concentrations at or below 40 g/1. The control of the solution concentration and deposition temperature is therefore imperative to prevent crystallization. The samples were then stored in vacuo for several hours to remove any remaining solvent. The thickness of the MXD6 layer is influenced by the solution concentration,- which also has -a strong effect on the crystallinity of the film, the solution temperature, and the spin speed.

The substrates with the dried MXD6 films are then placed into a vacuum chamber, and pentacene (97%, Aldrich) is evaporated upon the samples at room temperature with a deposition rate of 1 A/s.^' The area onto which pentacene was evaporated was limited to 2x2 mm² with a shadow mask. In a final evaporation step, gold source and drain contacts were evaporated on top of the pentacene at 0.5 A/s. The electrode areas were 1x2 mm² each, separated by a 60 μm channel, to give a width versus length ratio of WIL = 2000 / 60.

The transistors were analyzed using two Keithley 2400 source-measure units to apply the drain voltage and gate voltage, and measure the drain current and the gate leakage current. These two Keithley have a constant offset current of -2 x 10^"10 A, which is therefore the smallest current measured reliably.

Results and Discussion

The drain current vs. gate voltage graphs, or transfer characteristics, of two "FerrOFETs" with different MXD6 gate insulator layers are shown in [figure 9]. Device 1 - shown as the main graph - is made of a layer of MXD6 spun from a 50 g/1 solution (~50C) filtered with an 0.2 μm syringe filter. The gate insulator layer thus deposited is 350 nm thick, and is extremely uniform. The root-mean-square (RMS) roughness is less than 0.8 nm, and the roughness base to peak is 2 nm (cf. [figure 11(a)]). This is the same roughness as a bare ITO layer, which means that this MXD6 layer is completely amorphous. The scan voltage is -45 V to + 30 V, whereas the memory window, defined as the difference between the threshold voltage on the up sweep and down sweep, is 20 V. The scan voltage was chosen as such that the "FerrOFET" reaches the point of polarization saturation. The ratio between the scan voltage and the memory window is 0.27, a value comparable to inorganic FEFETs [15]. The overall operating gate voltages are higher than for FEFETs due to the fact that the c oercitive field in MXD6 is an order o f magnitude higher than in most ceramic ferroelectrics (E- = 100 MVm^"1) [20]. Leakage currents, however, are very small as amorphous films usually have smaller leakage compared to crystalline films [21], and even thinner MXD6 films are possible. The leakage currents in all "FerrOFETs" were below 10^"8 Acm^"2, and for more than 80% of the gate scan well below our detection limit of 10^"9 Acm^"2.

The "memory ratio" between the "on" current and the "off current at zero gate voltage, also called the channel resistance modulation, is 2.7 x 10⁴. The memory ratio was measured at zero gate voltage, which is preferable over having to apply a sustain voltage, not uncommon in FEFETs [14-15].

For device 2 - in the inset - MXD6 was spun from a 45 g/1 solution through an 0.45 μm filter, to a thickness of only 190 nm. The device thickness is lower due to the lower concentration and most likely a lower solution temperature (~40C) during the spin process. The scan voltage to saturation is -22 V to + 15 V, and the memory window is^" 10 V. This indicates that, as expected, the memory window and the scan voltage to saturation depend linearly on the thickness of the MXD6 gate insulator layer. It is also amorphous but shows some onset of crystallinity, giving it a slightly higher roughness (2 nm RMS, 8 nm base to p eak). T o o ur knowledge [ and w ithout w ishing t o b e b ound b y a ny p articular t heory],' t his is because of the lower concentration of the solution: for comparison, the very crystalline MXD6 film in [figure 10] was spun from a solution with a concentration of 40 g/1.

The memory ratio of device 2 is, with a value of 500, two orders of magnitude smaller than for device 1. We propose that it is the onset of crystallinity seen in [figure 11(b)] that reduced the memory ratio in device 2. Firstly, Murata et al. have shown that crystalline MXD6 shows a much smaller ferroelectric-like effect, likely due to a quenching of the alignment of the hydrogen bridge bonds in the crystal [22]. Secondly, the pentacene morphology at the interface layer is less ordered in device 2 due to the rougher MXD6 surface. It is well known that the pentacene morphology strongly influences the mobility of the material, especially the morphology of the first few pentacene layers near the interface.

It is also worth noting that at 0 V on the gate, device 2 stays entirely off. The increase in layer thickness from 50 nm (device l) to 150 nm brings forth a longer path from the injection electrode area to the accumulation layer. Therefore, a higher field is needed to start accumulating charges at the semiconductor/insulator interface, and this shifts the onset to more negative voltages. The control of the pentacene layer thickness therefore allows the exact placement of the memory window.

In [figure 12], the retention of the "on" state and "off state are shown as time progresses, while the state is read continuously. The memories of both the "on" and "off states are lost with two different time constants: The first order of magnitude of the "on" and "off current decays over a few ten seconds to an hour, while the remainder decays very slowly over the course of hours, depending on the quality of the MXD6 film. Due to the small, but non-zero leakage currents, and the depolarization field [16], the "FerrOFET" will likely require memory refreshing every few days, which is acceptable for most memory applications in organic electronics. Conclusion

The "FerrOFET", an MXD6/pentacene all₇organic ferroelectric-like memory transistor, shows a very comparable performance with respect to the inorganic FEFETs researched in the last two years, at a very small fraction of the cost and production difficulty. This enables the "FerrOFET" to be the memory of choice for many organic electronics circuits. A solution processable gate insulator that exhibits ferroelectric-like polarization in an amorphous phase will enable tight integration of the memory with OFETs in mobile, flexible, and cheap circuits.

^" We have shown that with rigorous control over the MXD6 deposition parameters, high memory ratios, reduced operating voltages, and memory retention times of hours to days are possible. REFERENCES

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It will be appreciated by those skilled in the art that embodiments of the present invention can be realised in the form of n or p type devices. Furthermore, embodiments can be realised in which the devices are enhancement mode or depletion mode devices.

Although the above embodiments have been described with reference to devices that comprise a solution processed insulator, embodiments are not limited to such devices. Embodiments can be realised in which the non-crystalline organic ferroelectric-like material is produced using some other process.

The reader's attention is directed to all papers and documents that are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including ariy accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A field effect transistor comprising source and drain electrodes separated by a semiconductor body region, and a gate electrode separated from said semiconductor body region by a gate insulator region, wherein the gate insulator region comprises a non-crystalline, preferably solution-processed, organic ferroelectric-like material.

2. A field effect transistor according to claim 1, wherein the ferroelectric-like material comprises at least one type of polymer.

3. A field effect transistor according to claim 2, wherein the polymer comprises hydrogen bond donor and hydrogen bond acceptor groups.

4. A field effect transistor according to claim 2 or 3, wherein the polymer is a polyamide.

5. A field effect transistor according to claim 4, wherein the polyamide is formed from the condensation of a diamine and a dicarboxylic acid.

6. A field effect transistor according to claim 5, wherein the diamine comprises an aromatic group.

7. A field effect transistor according to claim 5 or 6, wherein the diamine is xylenediamine.

8. A field effect transistor according to claim 5, 6 or 7, wherein the diamine is m-xylenediamine.

9. A field e ffect transistor a ccording to any one ofc laims 5 t o 8 , w herein the d icarboxylic a cid comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups.

10. A field effect transistor according to one of claims 5 to 9, wherein the dicarboxylic acid comprises up to 13 carbon atoms.

11. A field effect transistor according to one of claims 5 to 10, wherein the dicarboxylic acid comprises a number of carbon atoms in the range 5 to 11.

12. A field effect transistor according to one of claims 5 to 11, wherein the dicarboxylic acid comprises six carbon atoms.

13. A field effect transistor according to any preceding claim, wherein the ferroelectric-like comprises a repeating unit having the formula: 24

Where n = 4 - 11.

14. A field effect transistor according to claim 13, wherein n = 4.

15. A field effect transistor according to any preceding claim, wherein the insulator region has a thickness in the range 50 to 400 nm.

16. A field effect transistor according to any one of claims 1 to 14, wherein the insulator region has a thickness of up to approximately 350 nm.

17. A field effect transistor according to any one of claims 1 to 14, wherein the insulator region has a thickness in the range 100 to 300 nm.

18. A field effect transistor according to any one of claims 1 to 14, wherein the insulator region has a thickness in the range 150 to 250 nm.

19. A field effect transistor according to any one of claims 1 to 14, wherein the insulator region has a thickness of approximately 210 nm.

20. A field effect transistor according to any preceding claim, wherein the insulator region has a surface roughness equal to or less than 5 nm.

21. A field effect transistor according to any preceding claim, wherein the semiconductor body region comprises an organic semiconductor material.

22. A field effect transistor according to any preceding claim, wherein the semiconductor body region comprises a p-type semiconductor material.

23. A field effect transistor according to any preceding claim, wherein the semiconductor body region comprises pentacene.

24. A field effect transistor according to any preceding claim, wherein the transistor additionally comprises a substrate region.

25. A field effect transistor according to claim 24, wherein the substrate region comprises glass or plastic.

26. A field effect transistor according to any preceding claim, wherein the gate electrode comprises indium tin oxide or a synthetic metal.

27. A field effect transistor according to any preceding claim, wherein at least one of the source and drain electrodes comprises a material selected from the group consisting of PEDOT/PSS, polyaniline emeraldine salt, gold calcium, silver, magnesium, tin, aluminium and alloys comprising one or more of the aforementioned materials.

28. A method of fabricating a field effect fransistor comprising the steps of: a) forming a gate electrode; b) forming a gate insulator region; c) forming a semiconductor b ody region separated from said gate electrode by said gate insulator region; and d) forming source a nd d rain electrodes s eparated from e ach o ther b y s aid s emiconductor body region, such that the gate insulator region comprises a solution processed non-crystalline organic ferroelectric-like material.

29. A method according to claim 28, wherein step b) comprises solution phase deposition.

30. A method according to claim 28 or 29, wherein step b) comprises spin-casting.

31. A method according to claim 30, wherein the spin-casting is carried out at a speed in the range 100 to 10000 rpm.

32. A method according to claim 30, wherein the spin-casting is carried out at a speed in the range 3000 to 5000 rpm.

33. A method according to claim 30, wherein the spin-casting is carried out at a speed of approximately 4000 rpm.

34. A method according to any one of claims 30 to 33, wherein the spin-casting is carried out over a period of time in the range 20 seconds to 15 minutes.

35. A method according to any one of claims 30 to 33, wherein the spin-casting is carried out over a period of time in the range 5 to 11 minutes.

36. A method according to any one of claims 30 to 33, wherein the spin-casting is carried out over a period of time of approximately 8 minutes.

37. A method according to any one of claims 28 to 36, wherein the non-crystalline organic ferroelectric-like material is formed from a solution of a precursor of said ferroelectric-like material in a suitable solvent.

38. A method according to claim 37, wherein the concentration of the precursor in said solution is in the range 20 to 70 mg/ml.

39. A method according to claim 37, wherein the concentration of the precursor in said solution is in the range 30 to 60 mg/ml.

40. A method according to claim 37, wherein the concentration of the precursor in said solution is approximately 35 mg/ml.

41. A method according to any one of claims 37 to 40, wherein the solvent is an organic acid.

42. A method according to any one of claims 37 to 40, wherein the solvent is an organic solvent.

43. A method according to claim 42, wherein the solvent comprises an aromatic group.

44. A method according to claim 43, wherein the solvent is o-cresol or m-cresol.

45. A method according to claim 43, wherein the solvent is m-cresol.

46. A method according to any one of claims 37 to 45, wherein the precursor is dissolved in the solvent at a temperature in the range 20 to 70 °C.

47. A method according to any one of claims 37 to 45, wherein the precursor is dissolved in the solvent at a temperature in the range 40 to 60 °C.

48. A method according to any one of claims 37 to 45, wherein the precursor is dissolved in the solvent at a temperature of approximately 50 °C.

49. A method according to any one of claims 37 to 48, wherein the solution of the precursor is filtered prior to formation of the gate insulator region.

50. A method according to any one of claims 37 to 49, wherein the solution of the precursor is filtered at a temperature in the range 50 to 100°C prior to formation of the gate insulator region.

51. A method according to any one of claims 37 to 49, wherein the solution of the precursor is filtered at a temperature in the range 70 to 80 °C prior to formation of the gate insulator region.

52. A method according to claim 49, 50 or 51, wherein the solution of the precursor is filtered through a first syringe-mounted filter.

53. A method according to claim 52, wherein the first filter has a pore diameter of approximately 5 μm.

54. A method according to claim 52 or 53, wherein, the solution of the precursor which has been filtered through the first syringe-mounted filter is then filtered through a second syringe-mounted filter having a narrower pore diameter than the first filter.

55. A method according to claim 54, wherein the second filter has a pore diameter of approximately 0.45 μm.

56. A method according to any one of claims 28 to 55, wherein the semiconductor region is formed in step c) by thermal evaporation or spin casting.

57. A method according to any one of claims 28 to 56, wherein the gate electrode is formed at least in part on a substrate region.

58. A method according to any one of claims 28 to 57, wherein the gate insulator region is formed at least in part on the gate electrode.

59. A method according to any one of claims 28 to 58, wherein the semiconductor body region is formed at least in part on the gate insulator region.

60. A field effect transistor substantially as described herein with reference to and/or as illustrated in the accompanying drawings.

61. A method of fabricating a field effect transistor substantially as herein with reference to and/or as illustrated in the accompanying drawings.