WO2005010985A1 - Semiconductor device, method for manufacturing semiconductor device, semiconductor module and personal computer card - Google Patents

Abstract

A semiconductor device used in an electronic device comprises a semiconductor chip wherein a transistor having two electrodes on a major surface and an electrode on the back surface is formed; two electrically independent electrode plates connected to the respective electrodes on the major surface; an electrode plate electrically connected to the electrode on the back surface of the semiconductor chip; and an encapsulant made of an insulating resin, covering the lateral surfaces of the semiconductor chip, and placed in the space between the electrode plates. The package and the electrode plates shape the semiconductor device into a hexahedron. An active portion of the transistor is located on the major surface of the semiconductor chip and the two electrodes are arranged, with the active portion interposed therebetween. The electrode plates arranged on the major surface of the semiconductor chip have lateral surfaces facing to each other and provided with a recess for preventing the electrode plates from coming off the encapsulant.

Description

 Description Semiconductor device, method of manufacturing semiconductor device, semiconductor module and personal computer

 The present invention relates to a semiconductor device and a method for manufacturing the same, a semiconductor module, and a personal computer card, and more particularly to a technology effective when applied to a thinning technology. Background art

 With the spread of personal computers (PCs) in offices and homes, communication between the personal computers such as the one-in-one network has been actively carried out. The wireless LAN (local area network) has attracted attention The personal computer card (personal computer) used for the wireless LAN includes an antenna, a transmission / reception switch, and a reception switch. It incorporates a low-noise amplifier, a receiver mixer, a transmitter mixer, a voltage controlled oscillator (VCO), and a high-output power amplifier for transmission.

 On the other hand, as mobile phones and personal digital assistants (PDs) are becoming smaller and thinner, products (such as semiconductor devices) mounted on them are also required to be smaller and thinner.

As a conventional semiconductor device, a surface mount transistor is known. For example, one lead protrudes from the lower end of one end of the resin package, two leads protrude from the lower end of the other end, and a semiconductor chip is fixed on the inner end of the one lead. A structure in which an electrode of a chip and a lead on the other end are connected by a wire is known. Each lead is inside the resin And the lower surface of the lead and the lower surface of the resin projecting outward from the package are located on the same plane (for example, Japanese Patent Application Laid-Open No. H7-14739). .

 Also, as a semiconductor device incorporating a diode, two diode pellets are placed between a pair of conductors facing each other, and an insulating resin is filled between the conductor plates to integrate the two semiconductor elements. 2. Description of the Related Art A semiconductor device is known (for example, Japanese Patent Application Laid-Open No. Hei 9-27959).

 This semiconductor device is manufactured by the following method. First, the diodes are aligned on a semiconductor wafer. Electrodes having different polarities are provided on the upper and lower surfaces of the wafer, respectively. Next, an extensible tape is attached to one surface of the wafer. Next, the wafer is cut for each diode, and the tape is stretched to separate adjacent diode pellets for a predetermined distance. Next, the first conductor plates are overlapped and electrically connected to the exposed electrodes of each diode pellet. Next, the tape is peeled off, and a second conductor plate is superimposed on the electrode surface of the diode pellet that has appeared to be electrically connected. Next, an insulating resin is filled between the first and second conductive plates. Next, at least one of the first and second conductor plates is cut to electrically separate the electrodes of the adjacent diode pellets. Next, a plurality of semiconductor devices are manufactured by cutting and separating the conductive plate and the insulating resin so as to include two adjacent diode pellets.

The present applicant has developed a semiconductor device 90 shown in FIGS. 35 and 36 as a miniaturized transistor. This semiconductor device 90 is designed for the optimal design of the transistor of Patent Document 1 described above, in which the rise of the lead in the package is made oblique and the package is made smaller. In the semiconductor device 90, two leads 92, 93 are protruded from one end of a sealing body (package) 91 made of an elongated insulating resin in appearance. In this structure, a single lead 94 wider than the leads 92 and 93 protrudes. A semiconductor element (semiconductor chip) 95 is fixed on the inner end of the wide lead 94 covered by the sealing body 91 via a conductive bonding material.

 The semiconductor chip 95 is formed of a transistor chip. For example, although not shown, an emitter electrode and a base electrode are provided on the upper surface, and the lower surface is a collector electrode. Therefore, lead 94 becomes a collector lead. The electrodes on the upper surface of the semiconductor chip 95 and the inner ends of the leads 92 and 93 covered by the sealing body 91 are electrically connected by conductive wires 96 and 97. Therefore, of the leads 92 and 93, one lead becomes an emergency lead and the other lead becomes a pace lead. The wires 96 and 97 are also covered by the sealing body 91 so that they cannot be seen through from the outside.

 The lower surfaces of the outer ends of the leads 92 to 94 and the lower surface of the sealing body 91 are located on the same plane to constitute a surface-mounted semiconductor device. The leads 92 to 94 extending into the sealing body 91 rise obliquely from the middle and extend again to be parallel to the outer end portion. The semiconductor chip 95 is fixed to the parallel portion, and the wires 96 and 97 are connected. The sealing body 91 is designed to be as small as possible, and the lengths of the leads 92 to 94 protruding from the sealing body 91 are designed to be as short as possible to achieve miniaturization.

Here, as an example of the dimensions, the sealing body 91 has a width of 0.6 mm, a length of 0.8 mm, and a height of 0.4 mm. The projecting length of the leads 92 to 94 from the sealing body 91 is 0.1 mm, and the maximum length of the semiconductor device 90 is 1.0 mm. The length of the lower surface of the leads 92 to 94 is 0.15 mm, and this length region is the mounting surface. The semiconductor chip 95 is a square having a side length of 0.25 mm and a thickness of 0.1 mm. The loop height of the wire is 0.1 mm or less. Lead thickness is 0.11 mm The The thickness of the resin on the lower surface side of the lead 94 is 0.07 mm.ο

 In the manufacture of such a semiconductor device 90, the external dimensions are also as described above by stabilizing the resin molding when forming the sealing body 91 and maintaining the mechanical strength of the leads 92 to 94. It is difficult to make it smaller than the numerical value, and it is difficult to make it even smaller and thinner. '

 As mobile phones become smaller and thinner and PC cards become thinner, semiconductor devices to be embedded are required to be even thinner. For example, the VC0 (VC0 module) to be incorporated into a personal computer card is required to be as thin as 0.3 mm.

 An object of the present invention is to provide a small and thin semiconductor device, a semiconductor module, and an electronic device.

 The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

 The outline of a typical invention disclosed in the present application is briefly described as follows.

(1) The semiconductor device includes a semiconductor chip having a transistor having two electrodes on a main surface and one electrode on a back surface, and a semiconductor chip electrically connected to and electrically connected to each electrode on the main surface. Two independent electrode plates, an electrode plate electrically connected to the electrode on the back surface, and a sealing body that covers a side surface of the semiconductor chip and is filled with an insulating resin and is filled between the electrode plates. And a hexahedral structure formed by the sealing body and the electrode plate. The active portion of the transistor is located on the main surface of the semiconductor chip, and two electrodes are arranged so as to sandwich the active portion. The semi-conductive In the plurality of electrode plates arranged on the main surface side of the body chip, a side surface of the electrode plate between the adjacent electrode plates is provided with a depression having a shape that makes it difficult for the electrode plate to come off from the sealing body.

 Such a semiconductor device is manufactured by the following method. That is, the semiconductor device includes a first lead frame formed of a metal plate having a plurality of slits formed by etching and a plurality of lead patterns including lead portions on both sides of the first slits in parallel. A second lead frame made of a metal plate having the same size as the first lead frame; electrodes disposed on a main surface at intervals larger than the width of the first slit; and Preparing a semiconductor chip having electrodes on the opposite back side of

 In each of the lead patterns of the first lead frame, electrically connecting the respective electrodes on the main surface of the semiconductor chip to the respective lead portions on both sides of the first slit;

 Electrically connecting a second lead frame to the electrodes on the back surface of each of the semiconductor chips so that the second lead frame overlaps the first lead frame;

 A step of attaching an adhesive tape to a surface of the first lead frame on which the semiconductor chip is not fixed to close the first slit;

 Filling a space between the first lead frame and the second lead frame with an insulating resin, and curing the resin to form a resin layer;

After peeling the adhesive tape, the first lead frame, the resin layer, and the second lead frame are cut and separated lengthwise and crosswise to make one electrode plate at one end with the lead pattern portion as one unit. And manufacturing a hexahedral semiconductor device having two electrode plates at the other end. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing the appearance of a semiconductor device (transistor) which is an embodiment (Embodiment 1) of the present invention.

 FIG. 2 is a schematic cross-sectional view taken along line AA of FIG.

 FIG. 3 is a schematic sectional view taken along the line B--B in FIG.

 FIG. 4 is a schematic plan view of a semiconductor chip incorporated in the semiconductor device of the first embodiment.

 FIG. 5 is a schematic cross-sectional view taken along the line CC of FIG.

 FIG. 6 is a diagram for manufacturing the semiconductor chip, and is a schematic diagram showing a semiconductor wafer and a semiconductor chip manufactured from the semiconductor wafer.

 FIG. 7 is a schematic plan view of a first lead frame used when manufacturing the semiconductor device of the first embodiment.

 FIG. 8 is a schematic enlarged cross-sectional view of a part of the first lead frame including a slit portion.

 FIG. 9 is a schematic plan view of the second lead frame.

 FIG. 10 is a schematic plan view in which the main surface side of the semiconductor chip is connected to the first lead frame so as to overlap.

 FIG. 11 is a schematic enlarged plan view showing a part of a first lead frame to which a semiconductor chip is connected.

 FIG. 12 is a schematic enlarged sectional view showing a part of a first lead frame to which a semiconductor chip is connected.

 FIG. 13 is a partial enlarged cross-sectional view showing a state in which the second lead frame is connected to the back surface of the semiconductor chip connected to the first lead frame.

FIG. 14 is a schematic enlarged sectional view showing a state where a resin layer is formed by filling an insulating resin between the first lead frame and the second lead frame. FIG. 15 is a schematic enlarged cross-sectional view showing two manufacturing examples in which the first and second lead frames are cut together with the resin layer to form a plurality of semiconductor devices. FIG. 16 is a schematic enlarged sectional view showing a semiconductor device manufactured by using a first lead frame in which a stepped slit is formed by a press. FIG. 17 is a process sectional view illustrating a method of forming a stepped slit.

 FIG. 18 is a schematic enlarged sectional view showing a semiconductor device (diode) manufactured by the method for manufacturing a semiconductor device according to the first embodiment.

 FIG. 19 is a perspective view showing the appearance of the VC0 module incorporating the transistor and the diode manufactured in the first embodiment.

 FIG. 20 is a schematic plan view of the VC0 module with the cap removed.

 FIG. 21 is a schematic sectional view of the VCO module with the cap removed.

 FIG. 22 is a partial schematic perspective view showing a transistor mounted on the module substrate of the VC0 module.

 FIG. 23 is a partial schematic cross-sectional view showing a transistor mounted on the module substrate of the VC0 module.

 FIG. 24 is a partial schematic perspective view showing a diode mounted on the module board of the VC0 module.

 FIG. 25 is a partial schematic cross-sectional view showing a diode mounted on the module substrate of the VC0 module.

 FIG. 26 is an equivalent circuit diagram of the VC0 module.

 Figure 27 is a schematic plan view of a PC card incorporating a VCO module.

 Figure 28 is an equivalent circuit diagram of a personal computer.

FIG. 29 shows a semiconductor device (T) according to another embodiment (Embodiment 2) of the present invention. FIG. 4 is a partially enlarged schematic cross-sectional view showing a state in which a semiconductor chip is mounted between first and second lead frames in the manufacture of Rungis. FIG. 30 is a schematic plan view of a second lead frame used in the second embodiment.

 FIG. 31 is a schematic enlarged view showing a state in which an insulating resin is filled between the first lead frame and the second lead frame to form a resin layer in the manufacture of the semiconductor device of the second embodiment. It is sectional drawing.

 FIG. 32 is a schematic enlarged sectional view showing a semiconductor device according to another embodiment (Embodiment 3) of the present invention.

 FIG. 33 is a schematic enlarged sectional view showing a semiconductor device according to another embodiment (Embodiment 4) of the present invention.

 FIG. 34 is a schematic enlarged sectional view showing a semiconductor device according to another embodiment (Embodiment 5) of the present invention.

 FIG. 35 is a schematic perspective view showing the external appearance of a semiconductor device (transistor) developed by the present applicant, with the inside being seen through.

 FIG. 36 is a schematic enlarged sectional view of the semiconductor device shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

 (Embodiment 1)

 1 to 15 are diagrams related to a method for manufacturing a semiconductor device according to an embodiment (Embodiment 1) of the present invention. 1 to 3 are cross-sectional views showing the external appearance of a semiconductor device and its internal structure.

The semiconductor device 1 of the first embodiment forms a transistor, As shown in Fig. 1, it has a hexahedral structure, that is, a rectangular parallelepiped. One end of the rectangular parallelepiped is formed by one electrode plate 2, and the other end is sealed by two electrode plates 3, 4 and insulating resin filled between the two electrode plates 3, 4. It is formed of body 5. The sealing body 5 is embedded between the electrode plate 2 at one end and the electrode plates 3 and 4 at the other end. Electrode plate 2 is a collector (C) electrode terminal, electrode plate 3 is an emitter (E) electrode terminal, and electrode plate 4 is a base (B) electrode terminal.

 The remaining four sides except the both end faces of the rectangular parallelepiped are formed by cutting, and each is a flat surface. That is, the upper and lower surfaces shown in FIG. 1 are formed by electrode plates 2, 3, and 4 and a sealing body 5 extending between these electrode plates 2, 3, and 4, and the left front surface shown in FIG. , 3 and a sealing body 5 extending between the electrode plates 2, 3, and the back surface thereof is formed by a sealing body 5 extending between the electrode plates 2, 4 and the electrode plates 2, 4. I have. The right end face of the rectangular parallelepiped is formed by a square electrode plate 2, and the left end face is formed by electrode plates 3, 4 and a sealing body 5 sandwiched between the electrode plates 3, 4.

2 and 3 are cross-sectional views taken along lines AA and BB in FIG. The semiconductor chip 6 is connected to the inner surface of the electrode plate 2. As shown in FIGS. 4 and 5, the semiconductor chip 6 has two protruding bump-shaped electrodes 8 and 9 on the main surface side of the semiconductor substrate 7, and has electrodes 10 on the entire back surface of the semiconductor substrate 7. have. The semiconductor chip 6 is a transistor chip 6 constituting a transistor. The electrode 8 is an emitter electrode 8, the electrode 9 is a base electrode 9, and the electrode 10 is a collector electrode 10. The semiconductor substrate 7 constituting the semiconductor chip 6 is, for example, an n-type semiconductor. In addition, a P-type semiconductor region is locally formed in a surface layer portion on the main surface side of the semiconductor substrate 7, and an n-type semiconductor region is locally formed in a central surface layer portion of the p-type semiconductor region. . The p-type semiconductor region becomes the pace region 11 and the n-type semiconductor region Is the Emi ヅ evening area 12. Therefore, the semiconductor substrate 7 to be an n-type semiconductor forms a collector region. Insulating films 13 and 14 are selectively provided on the main surface side of the semiconductor substrate 7 in two layers, and the wiring layers 15 and 14 are sewn between the insulating films 13 and 14. 16 are provided. The wiring layer 15 electrically connects the emitter region 12 and the electrode (electrode electrode) 8, and the wiring layer 16 electrically connects the base region 11 to the electrode (base electrode) 9. are doing.

 The semiconductor chip 6 of the first embodiment has a predetermined distance because two electrodes on the main surface, that is, the emitter electrode 8 and the base electrode 9 are connected to the two electrode plates 3 and 4 respectively. It needs to be manufactured away. Therefore, the emitter electrode 8 and the base electrode 9 are arranged on both sides of the active part (active area) 17 in which the base region 11 and the emitter region 12 are provided (FIG. 4). Schematically shows the wiring layers 15 and 16 and the active portion 1 #). For example, the semiconductor chip 6 is a square having a thickness of 0.15 mm and a side of 0.25 mm. The pitch between the emitter electrode 8 made of Au bumps and the base electrode 9 is 0.16 mm.

 The electrode 10 on the back surface of the semiconductor chip 6 serving as a collector electrode is fixed to the inner surface of the electrode plate 2 by an adhesive 20 such as an AuSi layer or an Ag paste. The electrode plate 2 becomes a collector electrode terminal as an external electrode terminal. The electrode plate 2 and the electrode plates 3 and 4 are formed of a Cu alloy or 42 alloy, and an Au plating film or the like is formed on the bonding surface of the electrodes in order to improve the bondability with the electrodes. Since the electrode plates 2 to 4 are formed by cutting a metal plate (lead frame) having a thickness of 0.1 mm to 0.15 mm, the thickness of the electrode plate 2 and the electrode plates 3 and 4 is It becomes 0.1 mm to 0.15 mm.

As shown in FIGS. 2 and 3, the emitter electrode 8 on the main surface of the semiconductor chip 6 is connected to the electrode plate 3, and the electrode plate 3 serves as an external electrode terminal. Will form a child. Further, the base electrode 9 is connected to the electrode plate 4, and the electrode plate 4 serves as a base electrode terminal as an external electrode terminal.

 Also, this is one of the features of the present invention, but the surfaces of the electrode plate 3 and the electrode plate 4 facing each other are surfaces formed by slits formed by etching in a state of a lead frame. The surface facing the slit formation is hereinafter referred to as an adjacent surface 21. In the first embodiment, since the slit is formed by the etching using the liquid etchant, the distance between the pair of adjacent surfaces 21 facing each other depending on the manner of the etching gradually goes inward from the surface. The shape can be made wider. That is, since the adjacent surface 21 is a surface whose center is depressed, the degree of coupling with the sealing body 5 filled in the pair of adjacent surfaces 21 is improved. This improvement in the degree of bonding (adhesion) is due to the fact that the adjacent surface 21 is a curved surface, the contact area with the sealing body 5 is wider than the flat surface, and the adjacent surface 21 of the electrode plates 3 and 4 is This is due to the fact that it comes into contact with the sealing body 5.

 For example, when the thickness of each of the electrode plates 2 to 4 is 0.15 mm and the semiconductor chip 6 is 0.15 mm thick and 0.25 mm on a side, the semiconductor device 1 has a structure shown in FIG. In this state, that is, in the surface mounting posture, the length can be 0.55 mm, the width is 0.3 mm, and the height is 0.3 mm. If the thickness of the semiconductor chip 6 is set to the current limit of 0.1 mm and the electrode plate is further thinned, the length of the semiconductor device 1 can be further reduced.

Next, a method for manufacturing the semiconductor device 1 of the first embodiment will be described. In manufacturing the semiconductor device 1, a semiconductor chip 6 and two lead frames are prepared. As shown in FIG. 6 (a), the semiconductor chip 6 is formed by vertically and horizontally arranging element portions 26 which become semiconductor chips in a state of a semiconductor wafer 25 made of silicon. Each element section 26 is formed in the structure described with reference to FIGS. A bump electrode is formed in the state of the semiconductor wafer 25, and an electrode (a plating film or the like) on the back surface is formed as necessary. Next, The semiconductor wafer 25 is diced into individual pieces by dicing or the like, and a plurality of semiconductor chips 6 each having a thickness of 0.15 mm and a side length of 0.25 mm are formed [see FIG. 6 (b)].

 As shown in FIG. 7, the two lead frames include a first lead frame 29 in which a plurality of first slits 30 are provided in parallel along the width direction, and as shown in FIG. The second lead frame 35 has the same outer dimensions as the first lead frame 29. These lead frames are made of a Cu alloy or a 42 alloy having a thickness of 0.1 mm to 0.15 mm, all of which have guide holes 31 and 3 arranged at a constant pitch on both sides. Has 6. These guide holes 31 and 36 are formed so as to be aligned when the first lead frame 29 is overlapped with the second lead frame 35. Guide holes 31 and 36 are used to transport and position the lead frame. In addition, these lead frames are connected to the electrode plates 2 to 4 of the semiconductor chip 6 on one surface thereof, and are provided with Au plating or the like (not shown) at the connection portions.

As shown in FIG. 9, the second lead frame 35 has no flat hole except for the guide hole 36 and is a flat metal plate. As shown in FIG. 7, the first lead frames 29 are arranged such that the first slits 30 are located in the middle of the pitch between the adjacent guide holes 31. The slit pitch (groove interval) of the first slit 30 is, for example, 0.45 mm. The first slit 30 of the first lead frame 29 is formed by etching using a liquid etchant. As a result, as shown in FIG. 8, a pair of facing surfaces (adjacent surfaces 21) constituting the first slit 30 are depressed at the center in the thickness direction of the first lead frame 29. It becomes a curved surface. In other words, it is possible to make the shape such that the distance between the pair of adjacent surfaces 21 facing each other gradually increases inward from the surface depending on the etching method. Thus, such a curved surface can be formed.

 Further, in the first lead frame 29, the product forming portion 37 on which the semiconductor device 1 is formed is a square region having one side along the first slit 30 as partially shown in FIG. Since the portion including the first lead frame 29 is cut by a dicing blade or a wire cutter to separate the product forming portion 37, as shown in FIG. They are arranged vertically and horizontally. The length of one side of the product forming portion 37, that is, the length in the direction orthogonal to the first slit 30 is the center of the first slit 30 and the lead portions 39 on both sides thereof. It is the length up to the middle part, which is 0.3 mm when the length removed by cutting is subtracted.

 Next, the semiconductor chip 6 is connected to such a first lead frame 29. As shown in FIG. 10, the emitter electrode 8 and the base electrode 9 on the main surface of the semiconductor chip 6 are connected to the lead portions 39 on both sides of the first slit 30, respectively, and the semiconductor chip 6 is connected. Fix to the first lead frame 29. The emitter electrode 8 and the base electrode 9 of the semiconductor chip 6 are separated from each other via the first slit 30. The semiconductor chip 6 is fixed to each product forming part 37. FIG. 11 is a partially enlarged plan view showing a state in which the semiconductor chip 6 is connected to the lead portion 39 of the first lead frame 29 via the electrodes 8 and 9, and FIG. 12 is further enlarged. It is sectional drawing. The electrodes 8, 9 are connected near the edge of the lead portion 39. Electrodes of different semiconductor chips 6 are connected to both sides of one elongated lead portion 39. As shown in FIG. 11, the pitches a and b in the direction along the first slit 30 and in the direction orthogonal to the first slit 30 of the semiconductor chip 6 are, for example, 0.45 mm. The width c of the first slit 30 is 0.1 mm.

Next, as shown in FIG. 13, a second lead frame is provided on the back surface of each semiconductor chip 6 connected to the first lead frame 29 in an inverted state. The arm 35 is positioned and electrically connected via the adhesive 20. In the manufacturing method, the electrodes 10 on the back surface of the semiconductor chip 6 are omitted. As the adhesive 20, for example, connection is made using an Ag paste.

 Next, as shown in FIG. 14, an adhesive tape 42 is attached to the exposed surface of the first lead frame 29 to close the first slit 30. Thereafter, a space between the first lead frame 29 and the second lead frame 35 is filled with an insulating resin to fill it without gaps, and then the resin is blanked to form a resin layer 43. The resin layer 43 is formed so as to fill the space between the adjacent lead portions 39, between the adjacent semiconductor chips 6, and between the first lead frame 29 and the second lead frame 35 without any gap. However, it is also important for improving the reliability of the semiconductor device 1.

 Next, after the adhesive tape 42 is removed, it is cut by a cutting example as shown in FIG. Fig. 15 (a) shows a method of cutting with a wide dicing blade, a thick wire force, and a wide cutting allowance by Yuichi. Fig. 15 (b) shows a two-step cutting with a thin dicing blade or a thin wire cutter. It is. If the pitch for fixing the chip cannot be made narrow in chip bonding or the like, the semiconductor device 1 is manufactured by such cutting. If there is no problem in chip fixing and the chip fixing pitch can be narrowed, one-stage cutting is sufficient. In this way, the cutting in the direction along the first slit 30 and the cutting in the direction perpendicular to the first slit 30 are performed, and the electrode plate 2 is provided at one end. A large number of semiconductor devices 1 having the electrode plates 3 and 4 at the other end and in which the gap is filled with the sealing body 5 are manufactured.

As shown in FIG. 15 (a), a resin layer 43 serving as a sealing body 5 is interposed between a pair of adjacent surfaces 21 facing each other so as to be surrounded by a ring. The formed electrode plates 3 and 4 are less likely to come off, and the reliability as external electrode terminals is increased. FIGS. 16 and 17 are modifications of the first embodiment. In the first embodiment, a concave portion having a curved surface is formed in the pair of adjacent surfaces 21 so that the electrode plates 3 and 4 do not come off. In the present modification, as shown in FIG. The semiconductor device 1 was manufactured by using the slot 30 as a stepped slit having a stepped cross section. FIGS. 17 (a) to 17 (d) are schematic diagrams showing a method of forming stepped slits by pressing. As shown in Fig. 17 (a), the upper surface of the first lead frame 29 is pressed from below the first lead frame 29 with the press die holder 50 having a slit held down. The press die punch 51 is lifted up to form a slit 30a having a constant width as shown in FIG. 17 (b).

Next, as shown in FIG. 17 (c), with the upper surface side of the first lead frame 29 held down by the flat press die holder 52, the lower part of the first lead frame 29 is The press die punch 53, which is wider than the press die punch 51, is attached to form a recess 54, which is wider than the slit 30a, as shown in FIG. 17 (d). To form a stepped slit. In the manufacture of the semiconductor device 1, after connecting the electrode plates 3 and 4 of the semiconductor chip 6 to the surface opposite to the surface where the recesses 54 exist, the semiconductor device 1 is manufactured according to the semiconductor device manufacturing method of the first embodiment. Then, the semiconductor device 1 shown in FIG. 16 can be manufactured. Since the depression 54 is located on the other end side of the semiconductor device 1, the sealing body 5 enters the depression, and the electrode plates 3 and 4 hardly fall off. FIG. 18 is an example in which a diode (semiconductor device) is manufactured by the method for manufacturing a semiconductor device according to the first embodiment, and is a schematic enlarged cross-sectional view of the diode. In this modification, a diode is manufactured using two flat metal plates without slits. That is, two metal plates having the same dimensions and having only guide holes on both sides as shown in FIG. 9 are prepared. On one metal plate, one electrode of a semiconductor chip 59 having one electrode 57 and 58 on the upper and lower surfaces, respectively. Connect the poles. The semiconductor chip 59 is aligned and fixed on one metal plate as in the first embodiment. Thereafter, the other metal plate is connected to the other electrode of each semiconductor chip 59, and then, as in Embodiment 1, an insulating resin is filled between the pair of metal plates and cured to form a resin layer, Next, the two metal plates and the resin layer are cut vertically and horizontally to separate them, and as shown in FIG. 18, a semiconductor device (diode) 60 having electrode plates 61 and 62 at both ends is manufactured. In the figure, the adhesive at the connection between the electrode and the metal plate is omitted. This semiconductor device (diode) 60 can also be manufactured to the same dimensions as in the first embodiment.

 The transistor 1 and the diode 60 manufactured according to the first embodiment are incorporated in a semiconductor module and an electronic device. In the case of a semiconductor module, the transistor 1 and the diode 60 are mounted on the module substrate. In the case of an electronic device, at least one of the transistor 1, the diode 60, and the semiconductor module is mounted on a wiring board such as a mother board constituting the electronic device.

 Next, an example in which the present invention is applied to a V C0 module as a semiconductor module and a personal computer card incorporating the V C0 module will be described.

 The personal computer card 65 used in the wireless LAN has a thin flat force-type structure as shown in FIG. 27, and a connector 66 is provided at one end. When a PC card 65 is inserted into the PC card slot, the connector 66 will be electrically connected to the PC. The antenna is housed in the housing 67 of the personal computer 65.

Such a personal computer card 65 has a receiving system and a transmitting system as shown in the block diagram of FIG. The receiving system includes an antenna 68, a transmission / reception switching switch (SW) 69 to which the antenna 68 is connected, and a reception low-noise amplifier (LNA) connected to the transmission / reception switching switch 69. 7 0, It is composed of a reception system mixer (Rx—Mix) 71 connected to the reception low-noise amplifier 70, and a spanned LSI 72 connected to the reception system mixer 71. The transmission system includes a baseband LS72, a transmission mixer (Tx-Mix) 73 connected to the baseband LS72, and a transmission mixer 73 connected to the transmission mixer 73. It comprises a high output power amplifier 74, a transmission / reception switching switch 69 connected to the high output power amplifier (PA) 74, and an antenna 68. In addition, a voltage controlled oscillator (VCO: VC0 module) 75 is connected to the baseband LSI 72, the receiving mixer 71, and the transmitting mixer 73. Although not described in detail, two antennas 68 are connected because of the diversity configuration to improve the sensitivity.

 FIGS. 19 to 26 are diagrams relating to the VC0 module (semiconductor module) 75. FIG. The VC module 75 is, as shown in FIG. 19, externally composed of a module substrate 79 and a cap 80 attached to the upper surface of the module substrate 79. The module substrate 79 is made of a wiring substrate, and is provided with wiring 81, though only partially shown on the upper surface and inside (see FIG. 20). As shown in FIG. 21, a part of this wiring extends from the side surface to the lower surface of the module substrate 79, and the external electrode terminal 82 is formed from the side part to the lower part.

As shown in FIG. 20, on the upper surface of the module substrate 79, transistors T1 and T2, variable capacitance diodes D1, chip capacitors represented by C1 to C5, and chips represented by R1 to R4 A resistor is mounted. The transistors T 1 and T 2 are manufactured by the method for manufacturing a semiconductor device according to the first embodiment, and have the configuration of the semiconductor device (transistor) 1. The variable capacitance diode D 1 is also manufactured by the method for manufacturing a semiconductor device of the first embodiment, and has the configuration of the semiconductor device (diode) 60. ing. The chip resistor and the chip capacitor are chip components having a height of 0.55 mm, generally called 106, and have a structure having external electrode terminals at both ends.

 On the upper surface of the module substrate 79, a land is provided to which the external electrode terminals of the above-mentioned electronic components (transistors T1, T2, variable capacitance diode D1, chip resistor and chip capacitor) are connected. Has been. External electrode terminals of each electronic component are electrically connected to these lands via an adhesive such as solder. In FIGS. 20 and 21, in order to emphasize that the transistors T1, T2 and the variable capacitance diode D1 are products manufactured by the manufacturing method of the first embodiment, circles indicated by two-dot chain lines are used. Surrounded by

 FIGS. 22 and 23 show the mounting structure of the semiconductor device (transistor) 1, and FIGS. 24 and 25 show the mounting structure of the semiconductor device (diode) 60. The external electrode terminal of the transistor 1 is connected to the lands 83a and 83b of the module substrate 79 with an adhesive 84a, and the external electrode terminal of the diode 60 is connected to the land 83e, Connected to 8 3 f by adhesive 8 4 c o

 FIG. 26 is an equivalent circuit diagram of the personal computer card 65. It has a control signal input terminal P c in, an output terminal P out, a power supply voltage terminal (V cc), and a reference voltage terminal (GND) as external electrode terminals. This circuit is formed by two transistors T1 and T2, a variable capacitance diode D1, chip capacitors indicated by C1 to C5, and chip resistors indicated by R1 to R4. The rectangular part in the circuit diagram is a microstrip line.

 According to the first embodiment, the following effects are obtained.

(1) The semiconductor device 1 has a transistor chip 6 in a sealing body 5, and electrode plates 3, 4 electrically connected to an emitter electrode 8 and a base electrode 9 at one end, respectively. And the other end is electrically connected to the collector electrode 10 Because the electrode plate 2 has a rectangular parallelepiped structure that exposes the electrode plate 2, the four peripheral surfaces of each of the electrode plates 2 to 4 are formed by cutting at the same time when the outer shape of the sealing body 5 is formed. The semiconductor device 1 is thin and small.

 That is, the electrodes 8 and 9 of the semiconductor chip 6 constituting a transistor having two electrodes 8 and 9 on the main surface and one electrode 10 on the back surface are connected to the first lead frame 29 of the first lead frame 29. A plurality of semiconductor chips 6 are aligned and connected to a first lead frame 29 by connecting to the lead portions 39 separated by the lits 30, respectively, and then the electrodes 1 on the back surface of each semiconductor chip 6 are connected. 0, the second lead frame 35 is connected, and then the first lead frame 29 is pasted with an adhesive tape 42 to close the first slit 30 and then the first lead frame 29 A space between the first lead frame 35 and the second lead frame 35 is filled with an insulating resin and cured to form a resin layer 43. Then, the first lead frame 29 and the second lead frame 3 are formed. 5 is cut vertically and horizontally together with the resin layer 4 3 to manufacture the semiconductor device 1. Can it to produce type semiconductor device. Therefore, according to the first embodiment, the dimension of the transistor 1 diode 60 can be set to 0.55 mm in length, 0.3 mm in width, and 0.3 mm in height. It is smaller and thinner than 0.8 mm, 0.4 mm in width and 0.4 mm in height. Further, by further reducing the terminal thickness and the chip thickness, the thickness of the semiconductor device can be further reduced.

(2) In manufacturing the semiconductor device 1, in forming the first slit 30 provided in the first lead frame 29, the first slit 30 opposed to the first slit 30 by etching is formed. The surface 21 has a depression, or a stepped slit formed by two-stage press molding has a depression on the adjacent surface 21.In the assembly, it is formed by cutting. Since the electrode plates 3 and 4 are hardly dropped from the sealing body 5, the reliability of the semiconductor device 1 is improved. The nature becomes high.

 (3) Small and thin semiconductor devices (transistors) 1 and semiconductor devices (diodes) 60 incorporating the small and thin semiconductor device (transistor) 1 according to the first embodiment can also be made small and thin. For example, the thickness of the VCO module 75 can be reduced from the current 1.2 mm to 1.0 Omm. Therefore, the personal computer card 65 incorporating the VC0 module can be reduced in size and thickness.

 (Embodiment 2)

 FIGS. 29 to 31 are diagrams relating to a semiconductor device according to another embodiment (Embodiment 2) of the present invention. FIG. 29 is a partially enlarged schematic cross-sectional view showing a state where a semiconductor chip is mounted between the first and second lead frames in the manufacture of a semiconductor device (transistor). FIG. FIG. 31 is a schematic plan view of a second lead frame to be used. FIG. 31 shows a state in which an insulating resin is filled between the first lead frame and the second lead frame to form a resin layer. It is a typical expanded sectional view shown.

 In the second embodiment, in the method of manufacturing a semiconductor device of the first embodiment, the second lead frame 35 shown in FIG. 30 is replaced with the second lead frame 35 having no slit shown in FIG. A second lead frame 35b having a frame 33 is used. The first slit 30 of the first lead frame 29 is provided between the guide holes 31 of the guide holes 31 provided on both sides of the first lead frame 29, that is, adjacent guides. Although provided corresponding to the center position between the holes 31, the second slit 33 corresponds to the guide holes 36 provided on both sides of the second lead frame 35 b. It is provided in.

As a result, as shown in FIG. 29, the first lead frame 29 is positioned and connected to the main surface side of the semiconductor chip 6, and the second lead frame 35b is positioned to the back surface side of the semiconductor chip 6. Connected, the second switch The lip 33 is located along the edge of the product forming part 37.

 As described above, heat is applied by providing the first slit 30 and the second slit 33 in the first lead frame 29 and the second lead frame 35 b. In this case, even if there is a difference in the coefficient of thermal expansion between the silicon forming the semiconductor chip 6 and the metal forming the lead frame, the slit serves as a buffer space for preventing deformation, and the first and second lead frames 29, 3 5b does not warp as a whole, does not hinder the manufacture of semiconductor devices, and improves the yield.

 In the case of the second embodiment, when the resin layer is formed of the insulating resin, as shown in FIG. 31, not only is the adhesive tape 42 attached to the first lead frame 29, but also Then, the adhesive tape 42 is also applied to the second lead frame 35 b to close the second slit 33. As a result, as shown in FIG. 31, the resin layer 43 can be manufactured by filling the insulating resin between the first and second lead frames 29 and 35b and curing. After the formation of the resin layer 43, both the resin layers 43 are peeled off, and the first and second lead frames 29, 35b are cut lengthwise and crosswise together with the resin layer 43 so that the semiconductor device 1 is formed. To manufacture.

 According to the second embodiment, in the manufacture of the semiconductor device, the first lead frame 29 is less likely to be warped in the longitudinal direction, so that a longer first lead frame 29 can be used. The productivity can be improved, and the manufacturing cost of the semiconductor device 1 can be reduced.

 (Embodiment 3)

FIG. 32 is a schematic enlarged sectional view showing a semiconductor device according to another embodiment (Embodiment 3) of the present invention. The third embodiment has a structure in which a plurality of semiconductor chips are arranged in parallel. For example, two transistor chips 6 are arranged in parallel, and the electrodes 8 and 9 on the main surface of the transistor chip 6 are respectively electrically connected. Electrode plates 3 and 4 are electrically connected, and electrode plate 2 is electrically connected to electrode 10 on the back surface of transistor chip 6. In the case of the semiconductor device 1C as well, the side of the electrode plate between the adjacent electrode plates (between the electrode plates 3 and 4 and between the electrode plates 2 and 2) is provided with the sealing plate 5 and the Depressions with a shape that makes it difficult for 2 to 4 to come off are provided. In FIG. 32, a depression is formed by etching, but the depression may be formed by a stepped slit as in the first embodiment.

 In the third embodiment, the number of the transistor chips 6 is two, but may be more. In the third embodiment, the semiconductor device 1C incorporates two transistor chips 6. However, a structure in which a transistor chip and a diode chip are incorporated may be adopted. In the third embodiment, in the manufacture of the semiconductor device, the semiconductor devices having various structures as described above can be manufactured by selectively using the patterns of the first and second lead frames.

 That is, to give an example of the manufacture of a semiconductor device, in the step of preparing a first lead frame, a plurality of first leads are arranged in parallel so that a plurality of semiconductor chips can be connected side by side in the lead pattern. A first lead frame having a slit formed therein is prepared, and in the step of arranging and connecting a plurality of semiconductor chips to the first lead frame, a plurality of semiconductor chips are connected in each lead pattern. In the cutting and separating step, a lead pattern portion is cut and separated into one unit, and a hexahedral semiconductor device having a plurality of electrode plates at both ends and each of them is manufactured. By such a method of manufacturing a semiconductor device, a transistor array, a diode array, and the like can also be manufactured.

 (Embodiment 4)

FIG. 33 is a schematic enlarged sectional view showing a semiconductor device according to another embodiment (Embodiment 4) of the present invention. The semiconductor device 1D of the fourth embodiment has one end It has one external electrode terminal 85 and a plurality (four in this embodiment) of external electrode terminals 86 at the other end, and has a structure in which a semiconductor chip 6 d is covered with a sealing body 5. I have. The semiconductor chip 6d is an IC (integrated circuit device), and a plurality of bump-shaped electrodes 87 are provided in a line on the main surface of the semiconductor chip 6d. These electrodes 87 are electrically connected to external electrode terminals 86. In addition, one electrode 88 is provided on the back surface of the semiconductor chip 6 d, and this electrode 88 is electrically connected to the external electrode terminal 85 via an adhesive 20. ing.

 In manufacturing the semiconductor device 1D of the fourth embodiment, in the method of manufacturing the semiconductor device of the first embodiment, in the step of preparing the first lead frame, a plurality of semiconductor devices are arranged side by side in a lead pattern. A first lead frame having a plurality of first slits formed in parallel so that a semiconductor chip can be connected is prepared, and then a semiconductor chip 6 d having electrodes 87 arranged at regular intervals on the main surface is prepared. Are connected such that each electrode 87 is connected to each lead portion separated by the first slit. After that, the second lead frame is electrically connected to the electrode 88 side via the adhesive 20 in the same manner as in the first embodiment, and then the resin layer is formed and cut and separated, as shown in FIG. 33. Such a hexahedral semiconductor device is manufactured. Embodiment 4 is thin ■ A small IC (integrated circuit device) can be manufactured.

 (Embodiment 5)

 FIG. 34 is a schematic enlarged sectional view showing a semiconductor device according to another embodiment (Embodiment 5) of the present invention. In the semiconductor device 1E of the fifth embodiment, the electrode plate electrically connected to the electrode on the main surface of the semiconductor chip is exposed from the sealing body 5, and the semiconductor chip is completely buried in the sealing body 5. This is a semiconductor device having a structure.

The semiconductor device 1E of the fifth embodiment is a method of manufacturing the semiconductor device of the fourth embodiment. In the method, after connecting a plurality of electrodes on the main surface of the semiconductor chip to the first lead frame, an adhesive tape is attached to the surface of the first lead frame to close the first slit. It can be manufactured by forming a resin layer of an insulating resin so as to cover the first lead frame and the semiconductor chip, and then cutting the first lead frame together with the resin layer vertically and horizontally.

 That is, specifically, a plurality of first slits extending in parallel and a plurality of lead windows including lead portions on both sides of the first slit are provided in parallel. A first lead frame made of a metal plate and a semiconductor chip having an electrode on a main surface that can be connected to each lead portion of the lead pattern are prepared. Next, in each lead pattern of the first lead frame, each electrode on the main surface of the semiconductor chip is electrically connected to each lead portion. Next, an adhesive tape is attached to the surface of the first lead frame on which the semiconductor chip is not fixed to close the first slit, and then the entire semiconductor chip is covered and the space between the leads is filled. The insulating resin is filled as described above, and the resin is cured to form a resin layer. Thereafter, after the adhesive tape is peeled off, the first lead frame and the resin layer are cut and separated lengthwise and crosswise to manufacture a hexahedral semiconductor device having a plurality of electrode plates at one end using a lead pattern portion as one unit. .

 In the fifth embodiment, since the electrode on the back surface of the semiconductor chip 6d is not directly connected to the external electrode terminal, the electrode on the back surface of the semiconductor chip 6d may be omitted.

 Also in the fifth embodiment, a thin IC (integrated circuit device) can be manufactured.

Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and the gist of the invention is as follows. It goes without saying that various changes can be made without departing from the scope of the present invention. In the embodiment, an example in which the present invention is applied to an example of manufacturing a VC0 module to be incorporated in a personal computer card and an example of manufacturing a transistor, a diode, and an IC are described. For example, if the present invention is applied to an electronic component or a semiconductor module to be incorporated in a mobile phone, the size and thickness of the mobile phone can be reduced.

 The following is a brief description of the effects obtained by the representative inventions out of the inventions disclosed in the present application.

 (1) A thin semiconductor device can be provided.

 (2) A small semiconductor device can be provided.

 (3) By incorporating small and thin semiconductor devices, small and thin semiconductor modules and electronic devices can be manufactured.

 (4) Small and thin V C0 module can be provided.

 (5) Smaller and thinner VCO modules can be achieved by incorporating small and thin VC0 modules. Industrial applicability

 As described above, the semiconductor device according to the present invention is used by being incorporated in a semiconductor module electronic device. However, since it is small and thin, it contributes to the miniaturization and thinning of semiconductor modules and electronic devices. I do.

Claims

The scope of the claims 1. a semiconductor chip having an electrode on a main surface and a back surface opposite to the main surface; and an electrode plate electrically connected to the electrode on the main surface; An electrode plate electrically connected to the electrode on the back surface, A sealing body made of an insulating resin that covers a side surface of the semiconductor chip and is filled between the electrode plates. A semiconductor device having a hexahedral structure formed by the sealing body and the electrode plate.  2. The semiconductor device according to claim 1, wherein one electrode is provided on each of the main surface and the back surface of the semiconductor chip.  3. A plurality of electrodes are provided on the main surface of the semiconductor chip, and electrically independent electrode plates are connected to each of the plurality of electrodes. 14. The semiconductor device according to claim 1.  4. A transistor is formed on the semiconductor chip, and an active portion of the transistor is located on a main surface of the semiconductor chip, and two electrodes are arranged with the active portion interposed therebetween. The semiconductor device according to claim 3.  5. In the plurality of electrode plates arranged on the main surface side of the semiconductor chip, a recess having a shape that makes it difficult for the electrode plate to be pulled out of the sealing body is provided on a side surface of the electrode plate between the adjacent electrode plates. 4. The semiconductor device according to claim 3, wherein: 6. The semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are arranged in parallel, and each electrode of each of the semiconductor chips is connected to an electrically independent electrode plate. . 7. The semiconductor device according to claim 6, wherein a side surface of the electrode plate between the adjacent electrode plates is provided with a depression having such a shape that the electrode plate is difficult to be removed from the sealing body.  8. A semiconductor chip having a plurality of electrodes on a main surface; A plurality of electrically independent electrode plates each electrically connected to each electrode of the main surface; A sealing body made of an insulating resin that covers the entire semiconductor chip and is filled between the electrode plates, A hexahedral structure is formed by the sealing body and the electrode plate, A semiconductor device, wherein one surface of each of the electrode plates is exposed side by side on one surface side of the hexahedron.  9. Module board and A plurality of electronic components mounted on the main surface of the module substrate, A semiconductor module having a cap attached to a main surface side of the module substrate and covering the plurality of electronic components, 2. A semiconductor module, wherein at least one of the electronic components is the semiconductor device according to claim 1.  10. The semiconductor module according to claim 9, wherein the semiconductor module is a voltage controlled oscillator module.  11. An electronic device incorporating a plurality of electronic components and a semiconductor module, wherein at least one of the electronic components and the semiconductor module has the semiconductor device according to claim 1. Electronic device. 12 2. An electronic device that constitutes a personal computer including an antenna, a switch for switching between transmission and reception, a low-noise amplifier for reception, a mixer for reception, a mixer for transmission, a voltage-controlled oscillator, and a high-output power amplifier for transmission. Yes, the voltage regulation An electronic device, characterized in that the control oscillator is the semiconductor module according to claim 10.  13. A first lead frame made of a metal plate having a plurality of parallel lead patterns including a first slit and lead portions on both sides of the first slit; A second lead frame made of a metal plate having the same size as that of the first lead frame; Preparing a semiconductor chip having electrodes; and Electrically connecting the respective electrodes on the main surface of the semiconductor chip to the respective lead portions on both sides of the first slit in each of the lead patterns of the first lead frame; , Electrically connecting a second lead frame to the electrode on the back surface of each of the semiconductor chips so that the second lead frame is overlaid on the first lead frame; Adhering an adhesive tape to a surface of the first lead frame on which the semiconductor chip is not fixed to close the first slit; and Filling a space between the first lead frame and the second lead frame with an insulating resin, and curing the resin to form a resin layer; After peeling off the adhesive tape, the first lead frame, the resin layer, and the second lead frame are cut and separated lengthwise and crosswise, and the lead-pan portion is defined as one unit, and one end is provided at one end. A method of manufacturing a hexahedral semiconductor device having an electrode plate and having two electrode plates at the other end. 14. The first slit is formed by etching, and the surface of the lead portion forming the first slit has a thickness equal to the thickness of the lead portion. 14. The method for manufacturing a semiconductor device according to claim 13, wherein a center side thereof is depressed in a direction.  15. The first slit is formed into a stepped slit by punching twice with a press, and the first slit is formed on the opposite side of the wide slit width side of the stepped slit. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the electrodes on the main surface of the semiconductor chip are connected.  16. In the step of preparing the first lead frame, a first lead frame provided with a plurality of first slits in parallel so that a plurality of electrodes can be connected in the lead pattern. Prepare In the step of preparing the semiconductor chip, a semiconductor chip having a plurality of electrodes on a main surface that can be connected to each lead portion in the lead pattern and preparing an electrode on a back surface is prepared. 13. The step of connecting the semiconductor chip to the first lead frame, wherein each electrode of the semiconductor chip is connected to each lead portion of the lead pattern. The method for manufacturing the semiconductor device described in the above.  17. In the step of preparing the second lead frame, a second slit extending in the same direction as the first slit is formed at a position outside the fixing region of the semiconductor chip. And In the step of closing the slit, an adhesive tape is attached to a surface of the first lead frame and the second lead frame on which the semiconductor chip is not fixed, When peeling the adhesive tape after forming the resin layer, the adhesive tape bonded to the first lead frame and the second lead frame is peeled, and then the cutting and separating are performed. 13. The method for manufacturing a semiconductor device according to item 13. 18. In the step of preparing the first lead frame, a first plurality of first slits formed in parallel so that a plurality of the semiconductor chips can be connected side by side in the lead pattern In a step of preparing a lead frame and arranging and connecting a plurality of semiconductor chips to the first lead frame, a plurality of the semiconductor chips are connected in each of the lead patterns. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is cut and separated as a unit to manufacture a hexahedral semiconductor device having a plurality of electrode plates at both ends thereof.  19.2 preparing two metal plates, and a main surface and a semiconductor chip having electrodes on the back surface opposite to the main surface; A step of electrically connecting one of the electrodes of the semiconductor chip to one surface of the one metal plate, and arranging and connecting a plurality of semiconductor chips to the one metal plate; Electrically connecting the other electrode of the semiconductor chip so that the other metal plate overlaps the one metal plate; Filling a space between the two metal plates with an insulating resin and curing the resin to form a resin layer; Manufacturing a hexahedral semiconductor device having the two metal plates and the resin layer cut vertically and horizontally to separate them, each having an electrode plate at each end, and having the semiconductor chip therein. Semiconductor device manufacturing method. 20. A first metal plate having a plurality of first slits extending in parallel and a plurality of lead patterns including lead portions on both sides of the first slits in parallel. Preparing a semiconductor chip having an electrode connectable to each lead portion of the lead pattern on a main surface of the semiconductor chip; and, in each lead pattern of the first lead frame, a main surface of the semiconductor chip. Are electrically connected to the respective lead portions. Process Bonding an adhesive tape to a surface of the first lead frame on which the semiconductor chip is not fixed to close the first slit; and A step of filling an insulating resin so as to cover each of the semiconductor chips as a whole and fill each of the lead portions, and curing the resin to form a resin layer; Removing the adhesive tape, Manufacturing a hexahedral semiconductor device having a plurality of electrode plates at one end by cutting and separating the first lead frame and the resin layer vertically and horizontally and using the lead pattern portion as one unit. A method for manufacturing a semiconductor device.