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WO2005083577A3 - Integrated circuit with two different bus control units - Google Patents

Integrated circuit with two different bus control units Download PDF

Info

Publication number
WO2005083577A3
WO2005083577A3 PCT/IB2005/050524 IB2005050524W WO2005083577A3 WO 2005083577 A3 WO2005083577 A3 WO 2005083577A3 IB 2005050524 W IB2005050524 W IB 2005050524W WO 2005083577 A3 WO2005083577 A3 WO 2005083577A3
Authority
WO
WIPO (PCT)
Prior art keywords
spi
integrated circuit
control units
bus control
different bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2005/050524
Other languages
French (fr)
Other versions
WO2005083577A2 (en
Inventor
Juerg Fries
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of WO2005083577A2 publication Critical patent/WO2005083577A2/en
Publication of WO2005083577A3 publication Critical patent/WO2005083577A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The integrated circuit according to the invention comprises an IIC controller unit (TIC block) having an IIC clock output (SCL) and a SPI controller unit (SPI block) having a SPI clock output (SCK SPI), wherein the IIC clock output (SCL) and the SPI clock output (SCK SPI) are connectable to a clock pin (88).
PCT/IB2005/050524 2004-02-18 2005-02-10 Integrated circuit with two different bus control units Ceased WO2005083577A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100634.7 2004-02-18
EP04100634 2004-02-18

Publications (2)

Publication Number Publication Date
WO2005083577A2 WO2005083577A2 (en) 2005-09-09
WO2005083577A3 true WO2005083577A3 (en) 2006-03-09

Family

ID=34896078

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/050524 Ceased WO2005083577A2 (en) 2004-02-18 2005-02-10 Integrated circuit with two different bus control units

Country Status (1)

Country Link
WO (1) WO2005083577A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5530269B2 (en) * 2010-06-28 2014-06-25 ラピスセミコンダクタ株式会社 Communication interface device and communication method
TWI581105B (en) * 2010-10-29 2017-05-01 威盛電子股份有限公司 Integrated circuit and control method thereof
US8959274B2 (en) * 2012-09-06 2015-02-17 Silicon Laboratories Inc. Providing a serial download path to devices
CN110753424B (en) * 2019-10-31 2021-11-09 上海灵信视觉技术股份有限公司 Driving circuit defined by pins based on LED driving chip
CN117076360B (en) * 2023-08-15 2024-04-23 杭州凡诺电子有限公司 Circuit compatible with integrated circuit bus interface and serial peripheral interface

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696994A (en) * 1995-05-26 1997-12-09 National Semiconductor Corporation Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes
US6253268B1 (en) * 1999-01-15 2001-06-26 Telefonaktiebolaget L M Ericsson (Publ) Method and system for multiplexing a second interface on an I2C interface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696994A (en) * 1995-05-26 1997-12-09 National Semiconductor Corporation Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes
US6253268B1 (en) * 1999-01-15 2001-06-26 Telefonaktiebolaget L M Ericsson (Publ) Method and system for multiplexing a second interface on an I2C interface

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"XILINX Application Note XAPP348 (v1.2) Coolrunner CPLD - CoolRunner Serial Peripheral Interface Master", 13 December 2002 (2002-12-13), XP002342030, Retrieved from the Internet <URL:HTTP://DIRECT.XILINX.COM/BVDOCS/APPNOTES/XAPP348.PDF> [retrieved on 20050826] *
ANONYMOUS: "The I2C-bus specification Version 2.1", January 2000, PHILIPS SEMICONDUCTORS. PRODUCT SPECIFICATION, PAGE(S) 1-46, XP002218697 *

Also Published As

Publication number Publication date
WO2005083577A2 (en) 2005-09-09

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