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WO2005081769B1 - Mémoire flash sans contact avec effacement de canal et programme de canal de type non-ou sur soi - Google Patents

Mémoire flash sans contact avec effacement de canal et programme de canal de type non-ou sur soi

Info

Publication number
WO2005081769B1
WO2005081769B1 PCT/US2005/002655 US2005002655W WO2005081769B1 WO 2005081769 B1 WO2005081769 B1 WO 2005081769B1 US 2005002655 W US2005002655 W US 2005002655W WO 2005081769 B1 WO2005081769 B1 WO 2005081769B1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
memory cells
eeprom memory
column
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/002655
Other languages
English (en)
Other versions
WO2005081769A3 (fr
WO2005081769A2 (fr
Filing date
Publication date
Priority claimed from US10/781,112 external-priority patent/US7042044B2/en
Application filed filed Critical
Publication of WO2005081769A2 publication Critical patent/WO2005081769A2/fr
Publication of WO2005081769A3 publication Critical patent/WO2005081769A3/fr
Publication of WO2005081769B1 publication Critical patent/WO2005081769B1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Abstract

Un dispositif semi-conducteur ayant une mémoire morte programmable effaçable électriquement (EEPROM) comprend une matrice sans contact de cellules mémoires EEPROM disposées en rangées et en colonnes et construites au-dessus d’une pastille silicium sur isolant. Cheque cellule mémoire EEPROM comporte une région de drain, une région source, une région porte et une région corps. Le dispositif semi-conducteur comprend en outre une pluralité de lignes de portes chacune connectant les régions portes d’une rangée de cellules mémoires EEPROM, une pluralité de lignes de corps chacune connectant les régions corps d’une colonne de cellules mémoires EEPROM, une pluralité de lignes sources chacune connectant les régions sources d’une colonne de cellules mémoires EEPROM, et une pluralité de lignes de drain chacune connectant les régions de drain d’une colonne de cellules mémoires EEPROM. Les lignes de sources et les lignes de drain sont des lignes enterrées, et les régions sources et les régions de drain d’une colonne de cellules mémoires EEPROM sont isolées des régions sources et des régions de drain des colonnes adjacentes de cellules mémoires EEPROM.
PCT/US2005/002655 2004-02-18 2005-02-01 Mémoire flash sans contact avec effacement de canal et programme de canal de type non-ou sur soi Ceased WO2005081769A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/781,112 US7042044B2 (en) 2004-02-18 2004-02-18 Nor-type channel-program channel-erase contactless flash memory on SOI
US10/781,112 2004-02-18

Publications (3)

Publication Number Publication Date
WO2005081769A2 WO2005081769A2 (fr) 2005-09-09
WO2005081769A3 WO2005081769A3 (fr) 2005-12-29
WO2005081769B1 true WO2005081769B1 (fr) 2006-02-23

Family

ID=34838687

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/002655 Ceased WO2005081769A2 (fr) 2004-02-18 2005-02-01 Mémoire flash sans contact avec effacement de canal et programme de canal de type non-ou sur soi

Country Status (3)

Country Link
US (3) US7042044B2 (fr)
CN (1) CN1914739A (fr)
WO (1) WO2005081769A2 (fr)

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