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WO2005061378A3 - Equipment and process for creating a custom sloped etch in a substrate - Google Patents

Equipment and process for creating a custom sloped etch in a substrate Download PDF

Info

Publication number
WO2005061378A3
WO2005061378A3 PCT/US2004/041864 US2004041864W WO2005061378A3 WO 2005061378 A3 WO2005061378 A3 WO 2005061378A3 US 2004041864 W US2004041864 W US 2004041864W WO 2005061378 A3 WO2005061378 A3 WO 2005061378A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
creating
equipment
sloped etch
custom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/041864
Other languages
French (fr)
Other versions
WO2005061378A2 (en
Inventor
Dan W Youngner
John S Starzynski
James F Detry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Priority to PCT/US2004/041864 priority Critical patent/WO2005061378A2/en
Publication of WO2005061378A2 publication Critical patent/WO2005061378A2/en
Publication of WO2005061378A3 publication Critical patent/WO2005061378A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00547—Etching processes not provided for in groups B81C1/00531 - B81C1/00539
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B81C1/00396—Mask characterised by its composition, e.g. multilayer masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B81C1/00412—Mask characterised by its behaviour during the etching process, e.g. soluble masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H10P50/642—
    • H10P50/694—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Weting (AREA)

Abstract

Equipment and processes for creating a custom sloped etch in a substrate are disclosed. An illustrative process may include the steps of providing a substrate having a surface to be etched, providing a control layer on the surface of the substrate, forming a mask above the control layer, and then selectively etching each of the control layer and substrate at variable rates to form a sloped etch in the substrate.
PCT/US2004/041864 2003-12-18 2004-12-14 Equipment and process for creating a custom sloped etch in a substrate Ceased WO2005061378A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2004/041864 WO2005061378A2 (en) 2003-12-18 2004-12-14 Equipment and process for creating a custom sloped etch in a substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/739,314 2003-12-18
US10/739,521 US20050133479A1 (en) 2003-12-19 2003-12-19 Equipment and process for creating a custom sloped etch in a substrate
PCT/US2004/041864 WO2005061378A2 (en) 2003-12-18 2004-12-14 Equipment and process for creating a custom sloped etch in a substrate

Publications (2)

Publication Number Publication Date
WO2005061378A2 WO2005061378A2 (en) 2005-07-07
WO2005061378A3 true WO2005061378A3 (en) 2005-11-10

Family

ID=34677628

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/041864 Ceased WO2005061378A2 (en) 2003-12-18 2004-12-14 Equipment and process for creating a custom sloped etch in a substrate

Country Status (2)

Country Link
US (1) US20050133479A1 (en)
WO (1) WO2005061378A2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7492502B2 (en) 2004-09-27 2009-02-17 Idc, Llc Method of fabricating a free-standing microstructure
US7527996B2 (en) 2006-04-19 2009-05-05 Qualcomm Mems Technologies, Inc. Non-planar surface structures and process for microelectromechanical systems
US7534640B2 (en) 2005-07-22 2009-05-19 Qualcomm Mems Technologies, Inc. Support structure for MEMS device and methods therefor
US7547568B2 (en) 2006-02-22 2009-06-16 Qualcomm Mems Technologies, Inc. Electrical conditioning of MEMS device and insulating layer thereof
US7547565B2 (en) 2005-02-04 2009-06-16 Qualcomm Mems Technologies, Inc. Method of manufacturing optical interference color display
US7561321B2 (en) 2006-06-01 2009-07-14 Qualcomm Mems Technologies, Inc. Process and structure for fabrication of MEMS device having isolated edge posts
US7566664B2 (en) 2006-08-02 2009-07-28 Qualcomm Mems Technologies, Inc. Selective etching of MEMS using gaseous halides and reactive co-etchants
US7569488B2 (en) 2007-06-22 2009-08-04 Qualcomm Mems Technologies, Inc. Methods of making a MEMS device by monitoring a process parameter
US7623287B2 (en) 2006-04-19 2009-11-24 Qualcomm Mems Technologies, Inc. Non-planar surface structures and process for microelectromechanical systems
US7630114B2 (en) 2005-10-28 2009-12-08 Idc, Llc Diffusion barrier layer for MEMS devices

Families Citing this family (12)

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DE102005029803A1 (en) 2005-06-27 2007-01-04 Robert Bosch Gmbh Method for producing a micromechanical component and micromechanical component
US7450295B2 (en) 2006-03-02 2008-11-11 Qualcomm Mems Technologies, Inc. Methods for producing MEMS with protective coatings using multi-component sacrificial layers
US20070205473A1 (en) * 2006-03-03 2007-09-06 Honeywell International Inc. Passive analog thermal isolation structure
US7401515B2 (en) * 2006-03-28 2008-07-22 Honeywell International Inc. Adaptive circuits and methods for reducing vibration or shock induced errors in inertial sensors
US8367303B2 (en) * 2006-07-14 2013-02-05 Micron Technology, Inc. Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control
US7719752B2 (en) 2007-05-11 2010-05-18 Qualcomm Mems Technologies, Inc. MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same
US20090111271A1 (en) * 2007-10-26 2009-04-30 Honeywell International Inc. Isotropic silicon etch using anisotropic etchants
US7719754B2 (en) 2008-09-30 2010-05-18 Qualcomm Mems Technologies, Inc. Multi-thickness layers for MEMS and mask-saving sequence for same
US8969105B2 (en) 2010-07-26 2015-03-03 Fujifilm Corporation Forming a device having a curved piezoelectric membrane
JP6066422B2 (en) 2011-02-15 2017-01-25 フジフィルム ディマティックス， インコーポレイテッド Piezoelectric transducer using microdome array
US8659816B2 (en) 2011-04-25 2014-02-25 Qualcomm Mems Technologies, Inc. Mechanical layer and methods of making the same
US9105587B2 (en) 2012-11-08 2015-08-11 Micron Technology, Inc. Methods of forming semiconductor structures with sulfur dioxide etch chemistries

Citations (3)

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Publication number Priority date Publication date Assignee Title
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
US4938841A (en) * 1989-10-31 1990-07-03 Bell Communications Research, Inc. Two-level lithographic mask for producing tapered depth
US5007984A (en) * 1987-09-28 1991-04-16 Mitsubishi Denki Kabushiki Kaisha Method for etching chromium film formed on substrate

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US3839111A (en) * 1973-08-20 1974-10-01 Rca Corp Method of etching silicon oxide to produce a tapered edge thereon
JPS59214240A (en) * 1983-05-09 1984-12-04 Fujitsu Ltd Manufacture of semiconductor device
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
GB8921722D0 (en) * 1989-09-26 1989-11-08 British Telecomm Micromechanical switch
US5486485A (en) * 1994-02-18 1996-01-23 Philip Electronics North America Corporation Method of manufacturing a reflective display
US5627112A (en) * 1995-11-13 1997-05-06 Rockwell International Corporation Method of making suspended microstructures
US5750441A (en) * 1996-05-20 1998-05-12 Micron Technology, Inc. Mask having a tapered profile used during the formation of a semiconductor device
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US6071652A (en) * 1997-03-21 2000-06-06 Digital Optics Corporation Fabricating optical elements using a photoresist formed from contact printing of a gray level mask
US6420073B1 (en) * 1997-03-21 2002-07-16 Digital Optics Corp. Fabricating optical elements using a photoresist formed from proximity printing of a gray level mask
US6613498B1 (en) * 1998-09-17 2003-09-02 Mems Optical Llc Modulated exposure mask and method of using a modulated exposure mask
US6929030B2 (en) * 1999-06-28 2005-08-16 California Institute Of Technology Microfabricated elastomeric valve and pump systems
SG112804A1 (en) * 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
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US6749997B2 (en) * 2002-05-14 2004-06-15 Sandia National Laboratories Method for providing an arbitrary three-dimensional microstructure in silicon using an anisotropic deep etch

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
US5007984A (en) * 1987-09-28 1991-04-16 Mitsubishi Denki Kabushiki Kaisha Method for etching chromium film formed on substrate
US4938841A (en) * 1989-10-31 1990-07-03 Bell Communications Research, Inc. Two-level lithographic mask for producing tapered depth

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SPIERINGS G A C M: "REVIEW WET CHEMICAL ETCHING OF SILICATE GLASSES IN HYDROFLUORIC ACID BASED SOLUTIONS", JOURNAL OF MATERIALS SCIENCE LETTERS, CHAPMAN AND HALL LTD. LONDON, GB, vol. 12, no. 23, 1 December 1993 (1993-12-01), pages 6261 - 6273, XP000414624, ISSN: 0261-8028 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7492502B2 (en) 2004-09-27 2009-02-17 Idc, Llc Method of fabricating a free-standing microstructure
US7547565B2 (en) 2005-02-04 2009-06-16 Qualcomm Mems Technologies, Inc. Method of manufacturing optical interference color display
US7534640B2 (en) 2005-07-22 2009-05-19 Qualcomm Mems Technologies, Inc. Support structure for MEMS device and methods therefor
US7630114B2 (en) 2005-10-28 2009-12-08 Idc, Llc Diffusion barrier layer for MEMS devices
US7547568B2 (en) 2006-02-22 2009-06-16 Qualcomm Mems Technologies, Inc. Electrical conditioning of MEMS device and insulating layer thereof
US7527996B2 (en) 2006-04-19 2009-05-05 Qualcomm Mems Technologies, Inc. Non-planar surface structures and process for microelectromechanical systems
US7623287B2 (en) 2006-04-19 2009-11-24 Qualcomm Mems Technologies, Inc. Non-planar surface structures and process for microelectromechanical systems
US7561321B2 (en) 2006-06-01 2009-07-14 Qualcomm Mems Technologies, Inc. Process and structure for fabrication of MEMS device having isolated edge posts
US7566664B2 (en) 2006-08-02 2009-07-28 Qualcomm Mems Technologies, Inc. Selective etching of MEMS using gaseous halides and reactive co-etchants
US7569488B2 (en) 2007-06-22 2009-08-04 Qualcomm Mems Technologies, Inc. Methods of making a MEMS device by monitoring a process parameter

Also Published As

Publication number Publication date
WO2005061378A2 (en) 2005-07-07
US20050133479A1 (en) 2005-06-23

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