WO2005060043A2

WO2005060043A2 - Phase shifters, such as for a multiple antenna wireless communication system

Info

Publication number: WO2005060043A2
Application number: PCT/US2004/041234
Authority: WO
Inventors: David J. Allstot; Hossein Zarei; Taeik Kim
Original assignee: University of Washington
Current assignee: University of Washington
Priority date: 2003-12-11
Filing date: 2004-12-10
Publication date: 2005-06-30
Anticipated expiration: 2006-06-11
Also published as: WO2005060043A3

Abstract

According to embodiments of the present invention, a silicon-based reflective-type phase shifter fabricated using complementary metal-oxidesemiconductor (CMOS) technology includes 3dB directional coupler and variable impedance reflective loads having MOS transistor negative resistance circuits to reduce power loss. In one embodiment, the phase shifter includes a sigma-delta phase-locked loop having a voltage controlled oscillator (VCO) that is a replica of the reflective loads to ensure tracking to mitigate the effects of process, voltage, temperature variations, as well as aging and frequency changes. Accumulation varactors are used in the reflective loads and the VCO, and the same control voltage is used to control the capacitance of the varactors. According to embodiments of the present invention, a tunable transmission line phase shifter with a merged structure comprising a coplanar waveguide above an accumulation NMOS varactor which has improved characteristics by removing undesired interconnect parasitics is introduced. In one embodiment, the tunable transmission line phase shifter as a unit cell can be cascaded to increase phase control range.

Description

PHASE SHIFTERS, SUCH AS FOR A MULTIPLE ANTENNA WIRELESS COMMUNICATION SYSTEM

BACKGROUND

1. Field

[0001] Embodiments of the present invention relate to wireless communication systems and, in particular, to variable phase shifters in wireless communication systems.

2. Discussion of Related Art

[0002] Wireless communication systems, such as cellular phones, radios, and radar systems, for example, implement multiple-antenna systems, such as adaptive smart antenna receivers and transmitters. To ensure proper operation of such multiple-antenna systems, many of the parameters, such as signal amplitude and signal phase, for example, may be monitored and controlled using control loops. Amplifiers may be used to adjust the gain of incoming signals. Phase shifters may be used to adjust the phase of incoming signals.

[0003] There are various types of phase shifters that are currently being used. Current phase shifters have limitations, however.

BRIEF DESCRIPTION OF THE DRAWINGS [0004] In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally equivalent elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number, in which:

[0005] Figure 1 is a high-level block diagram of a multiple-antenna receiver according to an embodiment of the present invention;

[0006] Figure 2 is a high-level block diagram of a phase shifter according to an embodiment of the present invention;

[0007] Figure 3 is a schematic diagram illustrating a lumped element equivalent of the phase shifter depicted in Figure 2 according to an embodiment of the present invention;

[0008] Figure 4 is a high-level block diagram of a multiple-antenna receiver according to an alternative embodiment of the present invention;

[0009] Figure 5 is a high-level block diagram showing the sigma-delta (∑-Δ) phase-locked loop (PLL) depicted in Figure 4 according to an embodiment of the present invention;

[0010] Figure 6 is a schematic diagram of the voltage controlled oscillator (VCO) depicted in Figure 5 according to an embodiment of the present invention;

[0011] Figures 7 and 8 are a graphical representations illustrating scattering parameter (S-parameter) measurements for a phase detector according to an embodiment of the present invention;

[0012] Figure 9 is a graphical representation illustrating loss characteristics of a phase detector according to an embodiment of the present invention;

[0013] Figure 10 is a schematic diagram illustrating a lumped element equivalent of a low pass phase shifter according to an embodiment of the present invention; [0014] Figure 11 is a graphical representation 1100 illustrating phase shift characteristics of the phase shifter 1000 according to an embodiment of the present invention;

[0015] Figure 12 is a cross-section view of a phase shifter according to an alternative embodiment of the present invention;

[0016] Figure 13 is a top view of the phase shifter using the CMOS technology depicted in Figure 12 according to an embodiment of the present invention;

[0017] Figure 14 is a schematic diagram of the phase shifter depicted in Figure 12 according to an embodiment of the present invention;

[0018] Figure 15 illustrates the accumulation NMOS capacitor depicted in Figure 12 according to an embodiment; and

[0019] Figures 16 and 17 are graphical representations illustrating scattering parameter (S-parameter) measurements for a phase shifter according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS [0020] Figure 1 is a schematic diagram of a multiple-antenna receiver 100 according to an embodiment of the present invention. In the illustrated embodiment, the receiver 100 includes three antennas 102, 104, and 106, coupled to three bandpass filters 108, 110, and 112, respectively, via transmission lines 103, 105, and 107, respectively. The example bandpass filters 108, 110, and 112 are coupled to three variable-gain low-noise amplifiers 114, 116, and 118, respectively, which are coupled to three silicon-based phase shifters 120, 122, and 124, respectively, which are coupled to a mixer 126. The example mixer 126 is coupled to an analog-to-digital (AID) converter 128, which is coupled to a baseband section 130. The example base-band section is coupled to a control block 132, which is coupled to two digital-to-analog (D/A) converters 134 and 136. The example D/A converter 134 is coupled to the phase shifters 120, 122, and 124 via a control line 138, and the example D/A converter 136 is coupled to the variable- gain amplifiers 114, 116, and 118 via a control line 140.

[0021] In one embodiment, the example receiver 100 may operate as follows. A signal carried on an electromagnetic wave, such as a radio frequency (RF) signal, may be transmitted to the receiver 100 and may arrive at the antennas 102, 104, and 106 as three separate signals 142, 144, and 146, respectively. The bandpass filters 108, 110, and 112 may filter out all frequencies in their respective signals that do not fall within their pass bands. The mixer 126 may linearly combine the signals 142, 144, and 146 (filtered and amplified versions of these signals) and then convert them to a low-intermediate (IF) frequency. The AID converter 128 may convert the analog output 148 of the mixer 126 to a digital base band signal, such as to an audio frequency, for example. The base-band section 130 may provide modem control, signal processing, and phase and amplitude sample and update timing, for example. The example control block 132 may compare the loss and phase characteristics of the amplifiers 114, 116, and 118 and the phase shifters 120, 122, and 124, respectively, with a control voltage or other value, stored in a lookup table (not shown), for example, and may generate the control signals, such as a control voltage, for example, on the control lines 140 and 138, respectively, that control the gain applied to the signals 142, 144, and 146 by the amplifiers 114, 116, and 118, respectively, and the phase shift applied to the 142, 144, and 146 by the phase shifters 120, 122, and 124, respectively, to ensure that the signals 142, 144, and 146 from each path arrive at the mixer 126 at the substantially same time. [0022] In one embodiment, the antennas 102, 104, and 106, and bandpass filters 108, 110, and 112 may be off-chip and the low noise amplifiers 114, 116, and 118, mixer 126, A/D converter 128, base-band section 130, and control block 132 may be on-chip. Alternatively, one or all of the antennas 102, 104, and 106, bandpass filters 108, 110, and 112, low noise amplifiers 114, 116, and 118, mixer 126, A/D converter 128, base-band section 130, and control block 132 may be on-chip. For example, in embodiments of the present invention, the phase shifters 120, 122, and 124 may be implemented on a complementary metal-oxide- semiconductor (CMOS) chip.

[0023] In the illustrated embodiment, a voltage controlled oscillator 150 is coupled to the mixer 126. The voltage controlled oscillator 150 is described in more detail with reference to Figure 10.

[0024] Figure 2 is a high-level block diagram of a phase shifter 200 according to an embodiment of the present invention. The illustrated phase shifter 200 includes a three dB co-directional coupler 202 and two variable impedance (Z) reflective loads with negative resistance 204 and 206 (hereinafter "reflective loads"). The co-directional coupler 202 includes an input port 208 to receive the signal 142 (or a filtered and amplified version of the signal 142), and two load ports 210 and 212 coupled to pass the signal 142 to the reflective loads 204 and 206, respectively.

[0025] In one embodiment, the impedance (Z) of the reflective loads 204 and 206 may determine whether the phase shift applied to the signal 142 is a phase advance or a phase delay. A control voltage on the control line 138 may be used to control the impedance (Z) of the reflective loads 204 and 206, via reflective load ports 214 and 216. [0026] The example directional coupler 202 includes an output port 218 to output the phase-shifted signal 142 to the mixer 126.

[0027] Figure 3 is a schematic diagram illustrating the lumped element equivalent of the phase shifter 200 according to an embodiment of the present invention. In the illustrated embodiment, the phase shifter 200 includes eight capacitors 302, 304, 306, 308, 310, 312, 350, and 352, each having two terminals, four varactors 314, 316, 318, 320, each having three terminals, four inductors 322, 324, 326, and 328, and ten MOS transistors 330, 332, 334, 336, 337, 338, 340, 342, 344, and 345. Each MOS transistor 330, 332, 334, 336, 337, 338, 340, 342, 344, and 345 includes a gate, a source, and a drain. Blocking capacitors and resistors (not shown) are added to DC bias the varactors 314, 316, 318, 320.

[0028] One terminal of each two-terminal capacitor 302, 304, 306, and 308 is coupled to ground. One terminal of each of the varactors 314, 316, 318, and 320 is coupled to ground.

[0029] The second terminal of the capacitor 302, one terminal of the inductor 322, and one terminal of the capacitor 10 form a node at the input port 208. The second terminal of the capacitor 306, one terminal of the inductor 324, and the second terminal of the capacitor 310 form a node at the output port 214.

[0030] The second terminal of the capacitor 304, the second terminal of the inductor 322, and one terminal of the capacitor 312 are coupled to one terminal of the varactor 314, one terminal of the inductor 326, the drain of the MOS transistor 330, the gate of the MOS transistor 332, the drain of the MOS transistor 334, and the gate of the MOS transistor 336. The source of the MOS transistor 337 is coupled to ground. The drain of the MOS transistor 337 is coupled to the sources of the MOS transistors 334 and 336. The gate of the MOS transistor 337 is coupled to receive a bias current to bias the MOS transistors 330, 332, 334, and 336.

[0031] A second terminal of the varactor 318, one terminal of the inductor 328, the drain of the MOS transistor 338, the gate of the MOS transistor 340, the drain of the MOS transistor 342, and the gate of the MOS transistor 344 are coupled to the second terminal of the capacitor 308, the second terminal of the inductor 324, and the second terminal of the capacitor 312. The source of the MOS transistor 345 is coupled to the ground. The drain of the MOS transistor 345 is coupled to the sources of the MOS transistors 342 and 344. The gate of the MOS transistor 345 is coupled to receive the current to bias the sixth, seventh, eighth, and ninth MOS transistors 338, 340, 342, and 344.

[0032] In the illustrated embodiment, the third terminals of the varactors 314 and 318 are coupled to the control line 138 to receive the control voltage, which changes the capacitance of the varactors 314 and 318 and thus the impedance (Z) of the varactors 314 and 318. Although not illustrated for purposes of clarity, the third terminals of the varactors 316 and 320 also are coupled to the control line 138 to receive the control voltage. The desired phase shift may be achieved by controlling the phase (φ) of the reflection coefficient (T) of the reflective loads 204 and 206. The reflection coefficient (F) is given by:

P _ _τ ~ _ϋ _ jX — Z₀ Z_τ + Z₀ jX + Z₀ and by varying the impedance (Z ) of the reflective loads 204 and 206, the resulting phase variation (Δφ) is given by: Aφ = 2 (2)

where Z_T is reflective impedance with maximum and minimum values of Z_ma_x, and Z_mi_n, respectively, and Zo is the source impedance. X is the reactance of reflective load.

[0033] To increase the tuning range of the phase shifter 200, in one embodiment a multiple finger varactor layout may be used. To increase the quality factor (Q) of the phase shifter 200, in one embodiment, the finger lengths of the varactors 314, 316, 318, and 320 may be made short. A trade off may have to be made because a larger phase shift range may require longer fingers. In one embodiment in which the center frequency (ωø) is 2.4GHz, the component values for the lumped-element equivalent of the co-directional coupler 202 may be calculated using:

(4) ύ_n ^■ ' c₂ =- (5) ω_n

where Ci is the value of the capacitors 302, 304, 306, and 308, C₂ is the value of the capacitors 312 and 312, and Li is the value of the inductors 322 and 324.

[0034] In embodiments of the present invention, any of the varactors 314, 316,

318, and 320 may be an accumulation NMOS varactor implemented in CMOS and or a SiGe process. In these embodiments, the phase shifter 200 may have a monotonic capacitance, and therefore a monotonic phase characteristic. The minimum capacitance of the varactors 314, 316, 318, and 320 may be designed to be much higher than their parasitic capacitance.

[0035] The resistive component of the inductors 326 and 328 may cause undesired signal power losses. In the illustrated embodiment, the phase shifter 200 includes a negative resistance circuit comprising the cross-coupled NMOS and PMOS transistor pairs 330, 332, 334, 336, 338, 340, 342, and 344, along with the bias current on the gates of the MOS transistors 337 and 345. In one embodiment, the bias current on the gates of the MOS transistors 337 and 345 may be large enough to compensate most of the DC series resistance of the inductors 326 and 328, respectively, and may be small enough to have low power consumption. In spite of using some active devices, such as the MOS transistors 330, 332, 334, 336, 337, 338, 340, 342, 344, and 345, the total noise figure (NF), which is the amount of thermal and/or flicker noise that the MOS transistors 330, 332, 334, 336, 337, 338, 340, 342, 344, and 345 and all resistive parts of all passive elements contribute, is not larger than the NF of a conventional circuit that uses only passive-elements. This may be due at least in part to the higher gain of the low-loss phase shifter 200 compare to a phase shifter without these MOS transistors.

[0036] The components in the example phase shifter 200 may be affected by variations in process, voltage, and temperature (PVT) as well as aging and frequency changes. As a result, the characteristics of the components, which ideally should be matched components, may change in different ways in response to PVT variations, aging, and/or frequency changes.

[0037] Figure 4 is a high-level block diagram of a receiver 400 according to an alternative embodiment of the present invention in which the effects of PVT variations, aging, and/or frequency changes may be mitigated. In the illustrated embodiment, the receiver 400 includes a sigma-delta (Σ-Δ) phase-locked loop (PLL) 402 coupled between the control block 132 and the phase shifters 120, 122, and 124. In one embodiment, the Σ-Δ PLL 402 provides the control voltage for varactors in the phase shifter 200 on the control line 138.

[0038] Figure 5 is a high-level block diagram showing the Σ-Δ PLL 402 in more detail according to an embodiment of the present invention. In the illustrated embodiment, the Σ-Δ PLL 402 includes a phase-frequency detector (PFD) 502 coupled to a loop filter 504. The example loop filter 504 is coupled to a voltage controlled oscillator (VCO) 506 and the phase shifter 200. The VCO 506 is coupled to one input of a multiple modulus divider 508. The example divider 508 which is coupled to one input of the PFD 502. A second input of the example PFD 502 is coupled to receive a reference clock signal, from a crystal, for example. A multiple bit sigma-delta (Σ-Δ) modulator 510 is coupled to a second input of the divider 508. The Σ-Δ modulator 510 is coupled to receive a digital control signal from the control block 132.

[0039] In one embodiment, the Σ-Δ PLL 402 operates as follows. The PFD 502 may receive a known reference clock signal on the reference clock input and may force the VCO 506 to oscillate at a known, constant frequency. The divider 508 may divide the VCO 506 frequency by a known integer value and provide the resulting feedback clock signal to the second input of the PFD502. As the loop continues, the PFD 502 will force the feedback clock signal frequency to be substantially equal to the reference clock signal frequency. Thus, the frequency difference between the reference clock signal and the feedback clock signal is substantially zero. In a like manner, the Σ-Δ PLL 402 also forces any phase difference between the reference clock signal and the feedback clock signal to be substantially zero. The control voltage output from the loop filter 504 is used to force phase and/or difference to be substantially zero. [0040] In one embodiment, the VCO 506 may be a replica of the reflective loads 204 and/or 206 to provide calibration of the reflective loads 204 and 206 to ensure that the reflective loads 204 and 206 respond substantially similarly to PVT variations, aging, and/or frequency changes. Because the VCO in the Σ-Δ PLL 402 is designed as a replica of the reflective loads and formed on the same chip as the reflective loads 204 and 206 and because the same control voltage (the output of the loop filter 504) is used for the reflective loads 204 and 206 as well as the VCO 506, then the phase and/or frequency relationship among the reflective loads 204 and 206 and the VCO 506 is known and is the forced, known phase and frequency relationship of the VCO 506. Thus, the phase and/or frequency relationship among the VCO 506, the reflective load 204, and the reflective load 206 are forced to track each other regardless of PVT variations, aging, and/or frequency changes.

[0041] The divider 508 divides the frequency of the VCO 506 by a specific value, such as an integer value. For example, in one embodiment, the frequency of the VCO 506 may be one GHz and the divider 508 may divide that frequency by ten to create a feedback frequency of one hundred megahertz (100MHz). In this embodiment, the reference clock signal frequency may be lOOMHz. In an alternative embodiment, the frequency of the VCO 506 may change to two GHz and the divider 508 may divide that frequency by twenty to create the feedback frequency of lOOMHz. In any event, because the example divider 508 may divide by integer values, at best it may be able to provide a resolution of lOOMHz for a frequency of the VCO 506 of one GHz.

[0042] In one embodiment of the present invention, the Σ-Δ modulator 510 provides a mechanism to obtain a fractional division of the frequency of the VCO 506. For example, in one embodiment the frequency of the VCO 506 may be divided by 10.03. In this embodiment, in one hundred cycles of the VCO 506 the divider 508 may divide three cycles by eleven and the remaining ninety-seven cycles by ten. The average division thus is 10.03 and the resolution may be improved to three kilohertz (3 KHz). The Σ-Δ modulator 510 provides the signals to the divider 508 to the average division to the desired value. For example, the Σ- Δ modulator 510 may provide digital signals to the divider 508 to force the divider 508 to divide three cycles by eleven and the remaining ninety-seven cycles by ten. A digital control signal may instruct the Σ-Δ modulator 510 to change the algorithm used to determine the average division based on a change in operating frequency, for example.

[0043] In one embodiment, the Σ-Δ modulator 510 may randomize the division algorithm to ensure that frequency artifacts, such as spurs, for example, are reduced. For instance, the Σ-Δ modulator 510, if dividing three cycles by eleven and the ninety-seven cycles by ten, may randomly select which three cycles to divide by eleven rather than always dividing the first three cycles by eleven and the remaining ninety-seven cycles by ten.

[0044] In one embodiment, the receiver 400 may have a phase shift range of 360°. The example phase shifter 200 may provide a 180° phase shift range and the Σ-Δ PLL 402 may provide the additional 180° by appropriately alternating the polarities of the VCO (1000)

applied to the mixer 126. Also, chip area may be saved because using the Σ-Δ modulator 510, digital-to-analog conversion is implicit in the architecture, thus the D/A converter 134 may not be needed.

[0045] Figure 6 is a schematic diagram of the VCO 506 along with the phase shifter 200 according to an embodiment of the present invention. In the illustrated embodiment, the VCO 506 is a replica of the reflective load 208 and/or the reflective load 210. For example, the illustrated VCO 506 includes two varactors 602 and 604 each having three terminals, one inductor 606, and five MOS transistors 608, 610, 612, 614, and 616. Each MOS transistor 608, 610, 612, 614, and 616 includes a gate, a source, and a drain.

[0046] In the illustrated embodiment, one terminal of each of the varactors 602 and 604 is coupled to ground, one terminal of the inductor 606, the drain of the MOS transistor 608, the gate of the MOS transistor 610, the drain of the MOS transistor 612, and the gate of the MOS transistor 614 are coupled together, the source of the MOS transistor 616 is coupled to a source voltage, the drain of the MOS transistor 616 is coupled to the sources of the MOS transistors 612 and 614, and the gate of the MOS transistor 616 is coupled to receive the bias current to bias the MOS transistors 608, 610, 612, and 614.

[0047] The third terminals of the varactors 602 and 604 are coupled to the control line 138 to receive the control voltage from the loop filter 504. The control voltage is used to change the capacitance of the varactors 602 and 604. The oscillation frequency (fo) of the example VCO 506 may be approximated by:

where, L_τ is the inductance of the inductor 326 and or 328 and or 606, Cj is the capacitance of the varactors 314 and/or 318 and/or 602, and ^ is the capacitance of the varactors 316 and/or 320 and/or 604. The reference frequency for the PFD 502 and the divider ratio of the divider 508 may be determined according to the oscillation frequency (fo) to create the required control voltage for the phase shifter 200.

[0048] In one embodiment, impedance matching of the inductors 326 and 328 may be optimized to reduce losses. To obtain a phase variation around 750° with reduced loss, which corresponds to a linear phase characteristic, in one embodiment, one option may be to calculate the inductance of the inductors 326 and 328 required at resonance with the minimum capacitance of the varactors 314, 316, 318, and 320. In this embodiment, the phase values of S₂ι at the minimum and maximum control voltages may be -180° and -360°, respectively. In one embodiment, the phase (φ) can be calculated using:

^ = -180 - 2 - tan (-1) 'x , ifX<0 (7) ^zo j

<2> = -180 + 2 - tan (-1) ^fx ifX>0

As mentioned before, X is the reactance of reflective loads 204 and 206.

[0049] In one embodiment, (X) can be calculated using:

where Lγ is the inductance of the inductor 326 and/or 328, CT is the capacitance of the varactors 314 and/or 318, C^ is the capacitance of the varactors 316 and/or 320, ωø is the center frequency.

[0050] In one embodiment, the inductance of the inductors 322 and 324 (L_τ) can be calculated using:

where C_mm is the minimum capacitance of the varactors 314, 316, 318, and 320.

[0051] In one embodiment, the capacitance of the varactors 314 and/or 318 (Cγ) can be calculated using:

C_™. R = (11) min

where R is the tuning range of the capacitance of the varactors 316 and/or 320, C_min and C_max are the minimum and maximum capacitance of the varactors 316 and or 320, and L_τ is the inductance of the inductors 326 and 328.

[0052] Scattering parameter (S-parameter) measurements were taken of one embodiment of the phase shifter 200 to characterize the performance of the example phase shifter 200 under linear conditions at microwave frequency range. S-parameters are the reflection and transmission coefficients, such as the voltage ratios, for example, between an incident wave, such as the signals 142, 144, and/ 144, for example, and reflection waves reflected back from the reflective loads 208 and/or 210. Each S-parameter is typically characterized by magnitude, decibel (dB) and phase (φ).

[0053] Sπ is the input reflection coefficient of 50Ω terminated output, S₂ι is forward transmission coefficient of 50Ω terminated output, Sι₂ is the reverse transmission coefficient of 50Ω terminated input, and S₂₂ is the output reflection coefficient of 50Ω terminated input. The S-parameters can convert to other parameters such as hybrid (H) or admittance (Y) parameters. Additionally, stability factor (K) and many gain parameters can be computed using S- parameters.

Figure 7 is a graphical representation 700 illustrating S-parameter measurements of Si i, S₂₂, S₂ι and the phase (φ) of S2₁ for the phase detector 200 using a control voltage on the control line 138 of approximately 0.8 volts, a frequency range of approximately 0.5GHz to 5GHz, and with the phase shifter 200 implemented in a 180nm CMOS chip according to an embodiment of the present invention.

[0054] Figure 8 is a graphical representation 800 illustrating the measured phase (φ) of S₂ι, plus Sπ and S₂₂ for the phase detector 200 using a control voltage on the control line 138 approximately equal to 0.0 volts, 0.8 volts, and 1.5 volts. The phase shift range from 2.27GHz to 2.45GHz is approximately 105° for each reflective load 208 and 210, and is determined by the tuning range of the varactors 314, 316, 318, and 320. Both sets of Sn and S₂₂ values are less than approximately -lOdB for the entire control voltage range.

[0055] Figure 9 is a graphical representation 900 illustrating a comparison of measured loss characteristics of a conventional reflective-type phase shifter (not shown, but can assume as the phase shifter 200 without MOS transistors 330, 332, 334, 336, 337, 338, 340, 342, 344, and 345)) with the phase detector 200 biased at 0.5mA with V_DD ⁼1.8V. In the illustrated embodiment, the phase shifter 200 has losses that are decreased as follows. The losses are decreased to -1 ldB at 2.27GHz using a control voltage approximately equal to 0.0 volts, which is an improvement of 5.9dB. The losses are decreased to -4.6dB at 2.45GHz using a control voltage on the control line 138 approximately equal to 0.8V, which is an improvement of 3.1dB. The losses are decreased to -l ldB at 2.45GHz using a control voltage approximately equal to 1.5 volts, which is an improvement of only 0.3dB where the varactor capacitance characteristic saturates. [0056] There may be other circuitry in the receivers 100 and/or, such as down converters, for example, that convert the frequency of the signals 142, 144, and 146 to lower frequencies, such as voice frequencies, but such circuitry is omitted for purposes of clarity. The output of the mixer 126 may be coupled to other portions of the receiver 100 that are not shown. For example, if the receiver 100 is part of a cell phone, then the output of the mixer 126 may be coupled to other portions of the cell phone. Alternatively, if the receiver 100 is part of a radar system having thousands of antennas, for example, then the output of the mixer 126 may be coupled to other portions of the radar system.

[0057] There are various other types of phase shifters, such as switched line phase shifters, loaded line phase shifters, and lumped-element high pass and low pass phase shifters, for example. In such phase shifters, phase delay may be provided by passing signals through a low pass filter comprised of series inductors and shunt capacitors. Phase advance may be provided by passing signals through a high pass filter comprised of series capacitors and shunt inductors.

[0058] Figure 10 is a schematic diagram illustrating a conceptual low pass phase shifter 1000 according to an embodiment of the present invention in which phase shift is controlled by adjusting the capacitance of varactors. The illustrated phase shifter 1000 includes two inductors 1002 and 1004 coupled to a varactor 1006. A signal to be phase shifted is received on an input port 1008, is phase shifted by adjusting the capacitance of the varactor 1006 by applying a voltage on a control line 1012, and is output of the output port 1010. To calculate an operation frequency and a transmission phase, a normalized ABCD matrix for the example low pass phase shifter 1000 is given by R. V. Garver, "Broad-Band Diode Phase Shifters," IEEE Trans, on Microwave Theory and Techniques, vol. 20, pp. 314-323, May. 1972 as :

(11)

The normalized ABCD matrix may be used to convert to the scattering matrix:

(12)

The transmission phase (φ) is given by:

The operation frequency /ø of the phase shifter 1000 is 1 fo = - (14) 2 ZC

In equations (13) and (14), L and C can be given by the following equations, respectively: L = L_par +L_v„ (15) and C = C_par + C_VSI (16)

where the subscript par and var indicate parasitic and variable components, respectively.

[0059] Figure 11 is a graphical representation 1100 illustrating phase shift characteristics of the phase shifter 1000 while varying series inductance and shunt capacitance at 13GHz. The graphical representation 1100 displays transition phase variation (Δφ) when inductances are changed from 0.1 nH to 1.5nH according to capacitance variation from OfF to lOOOfF at an operation frequency o of 13 GHz. As can be seen, the less inductance, the wider phase changes at given capacitance control ranges. Also, the maximum and minimum values of phase are dependent on either variable capacitance or inductance values when one of values is fixed.

[0060] Alternatively, the maximum and minimum values of phase (φ) can be achieved by varying the inductance, using active inductors or inductor arrays with digitally controlled switches as described in A. Thanachayanont, "A 1.5-V highr CMOS active inductor for IF/RF wireless applications," in IEEE Asia-Pacific Conference on Circuits and Systems, Dec. 2000, pp. 654-657, for example, the capacitance, using voltage controlled variable capacitors or varactors (should be deleted), for example, or both. However, variable inductors consume high DC power, increase complexity, and generate more noise. Thus, varactors are more realistic solutions for the phase shifters.

[0061] When variable capacitors are used for phase controls, the absolute value of the phase difference between maximum and minimum phase shift, (Δtp) is given by:

(17)

[0062] There are two ways to further increase phase shift operations using varactors. Ideally, the simplest method for improved phase shift operations is the use of a varactor with wide capacitance changing range, but it is not always possible due to unexpected parasitic capacitance. Another possibility to increase the phase control range is to reduce unwanted parasitic capacitance, such as interconnect capacitances.

[0063] Equation (14) shows that the operating frequency ø of a phase shifter is inversely proportional to inductance and capacitance. As the frequency goes higher and higher, required inductances and capacitances have to be decreased. To increase transmission phase control range at the desired frequency, variable capacitance should keep large enough. It would be better to decrease inductances to achieve desired operation frequency of the phase shifter. In addition, the smaller inductors have less geometrically occupied area and it would further decrease parasitic capacitances. Thus, possible ranges of phase shift would be increased.

[0064] Figure 12 is a cross-section view of a phase shifter 1200 according to an alternative embodiment of the present invention. As Figure 12 illustrates, the phase shifter 1200 includes a coplanar waveguide 1216 implemented in the top metal layer of the process and used as an inductor with an accumulation NMOS capacitor 1224 merged underneath the coplanar waveguide 1216 and used as a variable capacitor. The coplanar waveguide having two ground strips 1218 and 1220 and a signal conductor 1222 is disposed on the layer 1212. The ground strips 1218 and 1220 are parallel to the signal conductor 1222, but insulated from the signal conductor 1222. An accumulation NMOS capacitor 1224 is disposed underneath the coplanar waveguide 1216. The gate and source/drain terminals of the varactor are connected to the signal line and ground/bias lines of the coplanar waveguide, respectively. As the signal is transmitted over the signal line of the coplanar waveguide, its phase is varied by the capacitance of the varactor.

[0065] In one embodiment, the coplanar waveguide 1216 may be operated as an inductor and the accumulation NMOS capacitor 1224 may be operated as a varactor to vary the phase of signal passing through them. The inductor and the varactor are connected through a metal layer which has minimum interconnect parasitic capacitances. Minimizing interconnect parasitic capacitances is important because parasitic capacitances decrease capacitance control range of varactors and limit operating frequencies.

[0066] In addition to inherent advantages from the phase shifter 1200, only one control voltage for the accumulation NMOS capacitor 1224 operation is applied through the signal conductor 1222. One DC control voltage can reduce circuit complexity and power consumption, which are critical issues of modem personal wireless communication systems.

[0067] Another advantage of the phase shifter 1200 is that it may be able to absorb parasitic inductance from interconnects to other circuits. It may be able to increase the possibilities that receivers implementing the phase shifter 1200, such as the receivers 100 and/or 400, for example, operate at desired frequency and tuning ranges of the tank because parasitic inductances and capacitances of interconnects are tremendously reduced, as described in T. Kim and D. J. Allstot, "Tunable Transmission Line Phase Shifter (TTPS)," IEEE ISC AS, vol. I, pp. 972- 975, May 2004 . In embodiments, the phase shifter 1200 may be used a unit cell of a larger phase shifter to increase phase control range by cascading several phase shifters 1200.

[0068] In one embodiment, the phase shifter 1200 was designed and fabricated in a BiCMOS process with 0.25μm gate length for the CMOS devices. The layout of the accumulation NMOS varactor 1222 may be a combination of n-channel and p-channel MOSFETs.

[0069] Fig. 13 is a top view of the phase shifter 1200 according to an embodiment of the present invention showing the two ground strips 1218 and 1220, the signal conductor 1222, and the accumulation NMOS capacitor 1224. The accumulation NMOS capacitor 1224 includes a gate, a source, and a drain. The signal to be phase shifted, such as the signal 142, transmits through the signal conductor 1222 and phase is shifted by varying capacitance of accumulation NMOS capacitor 1224 using a control voltage. In embodiments of the present invention, the ground strip 1218 and/or 1220 may be coupled to ground. Alternatively, the ground strip 1218 and/or 1220 may be coupled to a bias voltage.

[0070] Figure 14 is a schematic diagram of the phase shifter 1200 according to an embodiment of the present invention. In the illustrated embodiment, the accumulation NMOS capacitor 1224 includes a gate, a source, and a drain, and the signal conductor 1222 of the coplanar waveguide 1216 is coupled to the gate of the accumulation NMOS capacitor 1224. The source and the drain of the accumulation NMOS capacitor 1224, which in a conventional accumulation NMOS capacitor are tied together, are untied in this embodiment and the source of the accumulation NMOS capacitor 1224 is coupled to the ground wire 1220 and the drain of the accumulation NMOS capacitor 1224 is coupled to the ground wirel218. A bias input terminal 1402 is coupled to the ground wire 1218 and the drain of the accumulation NMOS capacitor 1224. A bias input terminal 1404 is coupled to the ground wire 1218 and the source of the accumulation NMOS capacitor 1224.

[0071] The capacitance of the accumulation NMOS capacitor 1224 may be varied by applying a bias voltage to the drain and/or source of the accumulation NMOS capacitor 1224 while keeping the voltage on the gate of the accumulation NMOS capacitor 1224 constant. For example, instead of keeping the source and/or drain at ground, a bias voltage of one volt, etc., for example, is applied to the source and/or the drain of the accumulation NMOS capacitor 1224 via the bias input terminal 1402 and/or the bias input terminal 1404, respectively, which causes the capacitance of the accumulation NMOS capacitor 1224 to change and thus a different phase shift for the incoming signal. The output of the phase shifter 1200 may be taken from the gate of the accumulation NMOS capacitor 1224.

[0072] One advantage of having the ground wires 1218 and 1220 in the return current path is that there is a lower resistant path and thus lower losses. If the ground wires 1218 and 1220 were not there, the return path would be through the substrate 1214, and the parasitic capacitance between the signal line 1222 and the substrate 1214 would introduce more loss.

[0073] For example, conventional inductors used in phase shifters may be one or one and half turns spiral inductors. Using the coplanar waveguide 1216 as an inductor according to embodiments of the present invention results in an inductor that may be free from negative mutual inductance that is typically generated from opposite layers of conventional spiral inductors. Thanks to the absence of negative mutual inductance, the total metal length to obtain the same inductance compared with conventional one or one and half turns spiral inductors is shorter than the circumference of the loop. As the result of the total metal length being less, the resultant coplanar waveguide 1216 inductor demonstrates a lower total series metal resistance, which provides a significantly higher Q and consequently lower loss when compared to conventional low-impedance single-turn spiral inductors. To further increase Q, the series metal resistance is reduced by making the wires, conductors, or strips with wider metal, although capacitive coupling to the substrate is increased.

[0074] In embodiments of the present invention, the layout of the accumulation NMOS capacitor 1224 is a combination of n-channel and p-channel MOS field effect transistors (MOSFET). Figure 15 illustrates the accumulation NMOS capacitor 1224 according to an embodiment in which the accumulation NMOS capacitor 1224 includes a p-substrate 1502, an n-well 1504 disposed in the p- substrate 1502, an n+ source terminal 1506 disposed in the n-well 1504, an n+ drain terminal 1508 disposed in the n-well 1504, and a gate terminal 1510 disposed on the silicon surface 1518. In the illustrated embodiment, the gate terminal 1510 includes an oxide layer 1512 and a polysilicon layer 1514.

[0075] In one embodiment, the accumulation NMOS varactor 1224 operates as follows. The varactor function may be achieved by changing the mode of operation from depletion to accumulation, by which the capacitance of the NMOS varactor 1224 is changed from minimum (depletion) to maximum (accumulation). The total capacitance from the gate to the drain/source if a negative voltage applied between the gate and the drain source is the series connection of the oxide capacitance and the depletion capacitance. This is because electrons just beneath the gate are pushed away and a depleted area (not shown) is created. If the voltage applied between the gate and the drain/source is reversed, so that a positive voltage is applied between the gate and the drain/source, the silicon surface 1518 is accumulated with electrons from the two n+-diffusion areas, as indicate by the channel 1516. The total capacitance from the gate to the drain/source is approaching its maximum value, which is equal to the oxide 1512 capacitance.

[0076] In this embodiment, the main contribution to losses is the signal path through the accumulation layer 1516 just beneath the silicon surface 1518, where electrons are majority carriers. Consequently, the accumulation NMOS capacitor 1224 operated as a varactor according to embodiments of the present invention is expected to have a relatively high Q due to higher mobility, for example. Additionally, none of the MOS capacitors, in contrast to conventional junction capacitors, have grounded terminals and hence have no constraints with respect to application of bias voltages.

[0077] Figure 16 is a graphical representation 1600 illustrating the measured return loss (Sπ), for the phase detector 1200 using a control voltage on the control line 1012 approximately equal to 0.0 volts, 1.0 volts, and 2.0 volts. The return loss is better than approximately 15dB over the full range of control voltages.

[0078] Figure 17 is a graphical representation 1700 illustrating the measured insertion losses and phase shift ranges between 12.5GHz and 13GHz at different control voltages are 9dB ± 2dB and 20°-22°, respectively, from the phase detector 1200. In the illustrated embodiment, the measured loss and phase shift for the phase shifter 1200 is determined by the tuning range of the varactor 1224.

[0079] Embodiments of the present invention may be implemented using hardware, software, or a combination thereof. In implementations using software, the software may be stored on a machine-accessible medium.

[0080] A machine-accessible medium includes any mechanism that may be adapted to store and/or transmit information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine- accessible medium includes recordable and non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), as recess as electrical, optical, acoustic, or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).

[0081] In the above description, numerous specific details, such as, for example, particular processes, materials, devices, and so forth, are presented to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the embodiments of the present invention may be practiced without one or more of the specific details, or with other methods, components, etc. In other instances, structures or operations are not shown or described in detail to avoid obscuring the understanding of this description.

[0082] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, process, block, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification does not necessarily mean that the phrases all refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0083] The terms used in the following claims should not be construed to limit embodiments of the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of embodiments of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

CLAIMS What is claimed is:

1. A phase shifter, comprising: a directional coupler having an input terminal to receive a signal carried on an electromagnetic wave, the directional coupler further having an output terminal to output the signal; a first reflective load coupled to the directional coupler, the first reflective load having a control terminal to receive a control voltage, the control voltage to control an impedance of the first reflective load, the first reflective load having further a negative resistance; and a second reflective load coupled to the directional coupler, the second reflective load having a control terminal to receive the control voltage, the control voltage to control an impedance of the second reflective load, the second reflective load having further a negative resistance.

2. The phase shifter of claim 1, wherein the directional coupler further comprises: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, each capacitor having a first terminal and a second terminal; and a first inductor and a second inductor, each inductor having a first terminal and a second terminal, wherein the first terminals of the first, second, third, and fourth capacitors are coupled to ground, wherein the second terminal of the first capacitor, the first terminal of the first inductor, and the first terminal of the fifth capacitor form a first node at the input terminal, wherein the second terminal of the third capacitor, the first terminal of the second inductor, the second terminal of the fifth capacitor form a second node at the output terminal.

3. The phase shifter of claim 2, wherein the second terminal of the second capacitor, the second terminal of the first inductor, and the first terminal of the sixth capacitor are coupled to the first reflective load.

4. The phase shifter of claim 3, wherein the first reflective load further comprises: a first, a second, a third, and a fourth metal -oxide-semiconductor (MOS) transistor, each MOS transistor having a gate, a source, and a drain; a third inductor having a first terminal and a second terminal; and a seventh and an eighth capacitor, each capacitor having a first terminal, a second terminal, and a third terminal, the third terminal to receive the control voltage, the control voltage to control capacitance of the seventh and the eighth capacitors, wherein the second terminals of the seventh and eighth capacitors are coupled to ground, wherein the first terminal of the seventh capacitor, the first terminal of the third inductor, the drain of the first MOS transistor, the gate of the second MOS transistor, the drain of the third MOS transistor, and the gate of the fourth MOS transistor are coupled to the second terminal of the second capacitor, the second terminal of the first inductor, and the first terminal of the sixth capacitor.

5. The phase shifter of claim 4, wherein the first reflective load further comprises a fifth MOS transistor having a gate, a source, and a drain, wherein the source of the fifth MOS transistor is coupled to the ground, the drain of the fifth MOS transistor is coupled to the sources of the third and fourth MOS transistors, and the gate of the fifth MOS transistor is coupled to receive a voltage to bias the first, second, third, and fourth MOS transistors.

6. The phase shifter of claim 5, wherein the second reflective load further comprises: a sixth, a seventh, an eighth, and a ninth MOS transistor, each MOS transistor having a gate, a source, and a drain; a fourth inductor having a first terminal and a second terminal; and a ninth and a tenth capacitor, each capacitor having a first terminal, a second terminal, and a third terminal, the third terminal to receive the control voltage, the control voltage to control capacitance of the ninth and a tenth capacitors, wherein the second terminals of the ninth and tenth capacitors are coupled to ground, wherein the first terminal of the ninth capacitor, the first terminal of the fourth inductor, the drain of the sixth MOS transistor, the gate of the seventh MOS transistor, the drain of the eighth MOS transistor, and the gate of the ninth MOS transistor are coupled to the second terminal of the fourth capacitor, the second terminal of the second inductor, and the second terminal of the sixth capacitor.

7. The phase shifter of claim 6, wherein the second reflective load further comprises a tenth MOS transistor having a gate, a source, and a drain, wherein the source of the tenth MOS transistor is coupled to the ground, the drain of the tenth MOS transistor is coupled to the sources of the eight and ninth MOS transistors, and the gate of the tenth MOS transistor is coupled to receive a voltage to bias the sixth, seventh, eighth, and ninth MOS transistors.

8. The phase shifter of claim 1 , further comprising a phase-locked loop (PLL) to generate the control voltage, the PLL comprising: a phase-frequency detector (PFD) having a reference input to receive a reference clock signal and a feedback input to receive a feedback clock signal; a loop filter; a voltage control oscillator (VCO); a divider; a sigma-delta modulator; wherein the PFD is to output a difference signal to indicate a difference in phase and/or frequency between the reference clock signal and the feedback clock signal, wherein the loop filter is to generate the control voltage from the difference signal, where in the VCO is to generate a VCO clock signal using the control voltage, wherein the divider is to generate the feedback clock signal using the VCO clock signal, wherein the sigma-delta modulator is to control the division factor of the divider.

9. The phase shifter of claim 8, wherein the VCO comprises a replica of the first and/or the second reflective load.

10. The phase shifter of claim 4, wherein the seventh capacitor comprises an accumulation n-channel MOS (NMOS) capacitor.

11. A phase shifter, comprising: a coplanar waveguide, the coplanar waveguide having a signal conductor, a first ground wire, and a second ground wire; and an accumulation n-channel metal oxide semiconductor (NMOS) capacitor disposed proximate to the coplanar waveguide, the accumulation NMOS capacitor having a gate, a drain, and a source, wherein the signal conductor of the coplanar waveguide is coupled to the gate of the accumulation NMOS capacitor, wherein the first ground wire of the coplanar waveguide is coupled to the source of the accumulation NMOS capacitor, and wherein the second ground wire of the coplanar waveguide is coupled to the drain of the accumulation NMOS capacitor.

12. The phase shifter of claim 11, wherein the coplanar waveguide further comprises a first terminal coupled to the first ground wire, the first terminal to apply a first bias voltage to the first ground wire.

13. The phase shifter of claim 12, wherein the coplanar waveguide further comprises a second terminal coupled to the second ground wire, the first terminal to apply a second bias voltage to the second ground wire.

14. The phase shifter of claim 11, wherein the signal conductor of the coplanar waveguide is to receive a signal carried on an electromagnetic wave.

15. The phase shifter of claim 14, wherein the drain of the accumulation NMOS capacitor is to receive a bias voltage, a capacitance of the accumulation NMOS capacitor to change in response to the bias voltage.

16. The phase shifter of claim 15, wherein a phase of the signal carried on an electromagnetic wave is to change in response to the change in capacitance of the accumulation NMOS capacitor.