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WO2005048327A1 - Procede d'exposition et dispositif d'exposition - Google Patents

Procede d'exposition et dispositif d'exposition Download PDF

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Publication number
WO2005048327A1
WO2005048327A1 PCT/JP2004/017043 JP2004017043W WO2005048327A1 WO 2005048327 A1 WO2005048327 A1 WO 2005048327A1 JP 2004017043 W JP2004017043 W JP 2004017043W WO 2005048327 A1 WO2005048327 A1 WO 2005048327A1
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WO
WIPO (PCT)
Prior art keywords
exposure
pattern
original
sensitive substrate
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2004/017043
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English (en)
Japanese (ja)
Inventor
Noriyuki Hirayanagi
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Nikon Corp
Original Assignee
Nikon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp filed Critical Nikon Corp
Priority to JP2005515488A priority Critical patent/JPWO2005048327A1/ja
Publication of WO2005048327A1 publication Critical patent/WO2005048327A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
    • H01J37/3175—Projection methods, i.e. transfer substantially complete pattern to substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30—Electron or ion beam tubes for processing objects
    • H01J2237/317—Processing objects on a microscale
    • H01J2237/3175—Lithography
    • H01J2237/31777—Lithography by projection
    • H01J2237/31788—Lithography by projection through mask

Definitions

  • the present invention relates to an exposure method and an exposure apparatus for exposing and transferring a fine device pattern such as a semiconductor.
  • an original pattern is formed on a mask (original plate) by dividing it into a number of small areas, and the charged particle beam is deflected and the stage is moved. Is exposed.
  • this small area is called a collective exposure area or a subfield, and an aggregate of a large number of collective exposure areas on a mask is called an exposure area.
  • a perforated mask in which an original pattern is formed as an opening on the mask.
  • this stencil mask it is not possible to form a pattern (called a donut pattern) that is surrounded by linear holes and is like a remote islet that is not connected to the surrounding area.
  • the pattern is divided into shapes that do not become a donut pattern and formed in separate exposure areas (the divided patterns are called complementary patterns), and the entire exposure area is sensitive.
  • Complementary patterns are connected by overlapping exposure on a substrate (wafer).
  • the present invention has been made in order to solve such a problem, and in a case where a pattern to be subjected to a desired process is unevenly distributed, a mask cost is reduced and a throughput at the time of exposure is increased. It is an object of the present invention to provide an improved exposure method and an exposure apparatus.
  • the exposure method of the present invention comprises: dividing an original pattern of a device pattern to be formed on a sensitive substrate into a plurality of collective exposure regions to form on a master; and irradiating the master with an energy beam for each of the collective exposure regions. Projecting and forming an energy beam having passed through each collective exposure area on the sensitive substrate; On a plate, an exposure method for forming the entire device pattern by joining images of the patterns in each collective exposure area, wherein a pattern that requires complementary division at the time of forming the original pattern is included in the device pattern.
  • the pattern is complementarily divided in only a part of the original using the collective exposure area as a minimum unit, and the complementary divided original pattern is overlaid on the corresponding area on the sensitive substrate and exposed. It is characterized by doing.
  • the production cost of the mask can be reduced and the throughput during exposure can be prevented from lowering. it can.
  • the exposure is performed while the original plate and the sensitive substrate are mechanically continuously moved (mechanical scanning), and an area exposed by one mechanical scanning is provided.
  • a plurality of (mechanical stripes) are provided, and a complementary original pattern is arranged at an end of a set of mechanical stripes, and the divided original patterns can be overlaid and exposed on the sensitive substrate. it can. In this case, the mechanical positioning of the stage is adjusted and the complementary patterns are superimposed.
  • the energy beam is a charged particle beam
  • a Comprinnontari original pattern is arranged in an area on an original that can be overlapped on the sensitive substrate by a charged particle beam deflector; By deflecting the charged particle beam, the complementary pattern images can be superimposed on the sensitive substrate.
  • Complementary patterns can also be superimposed using both mechanical scanning and charged particle beam deflection.
  • the energy beam is a charged particle beam
  • the complementary divided original patterns are arranged side by side in the scanning direction at an end (or in the middle) of a region exposed by one mechanical scan.
  • a constant deflection operation is performed in synchronization with the continuous mechanical movement (mechanical scanning) between the original and the sensitive substrate, and complementary division is performed.
  • a pattern image which is not exposed is exposed on the sensitive substrate.
  • the deflection operation of the charged particle beam deflector is changed, and the speed between the original and the sensitive substrate in the mechanical scanning is changed. Exposure can be performed by changing the ratio so that the complementary pattern images overlap on the sensitive substrate.
  • an original pattern of a device pattern to be transferred onto a sensitive substrate is divided into a plurality of batch exposure regions (mask subfields) arranged in a grid on the original (mask, reticle).
  • a charged particle beam (illumination beam) is sequentially applied to the subfield, and the charged particle beam (projection beam) passing through each subfield is sequentially applied to a corresponding exposure area (wafer subfield) on the sensitive substrate.
  • a group of a plurality of subfields arranged in the form of a lattice is referred to as a mechanical karlist stripe, and one direction of the lattice is defined as an X direction, and the other direction is defined as a Y direction.
  • the illumination beam is deflected to scan the beam, and in the Y direction, the exposure is performed while mechanically continuously moving (mechanical scanning) the master and the sensitive substrate.
  • the original image and the sensitive substrate are aligned by mechanical scanning, and a transfer image of one of the complementary divided original patterns of the mask subfield array at the end of each mechanical stripe is formed by the mechanical scanning.
  • the exposure is performed so as to overlap a transfer image of the complementary original divided other pattern in a predetermined subfield sequence on the sensitive substrate.
  • an original pattern of a device pattern to be transferred onto a sensitive substrate is arranged in a plurality of batch exposure areas (mask subfields) arranged in a grid on the original (mask or reticle).
  • a charged particle beam (illumination beam) is sequentially applied to the subfield, and the charged particle beam (projection beam) passing through each subfield is exposed to a corresponding exposure area (wafer subfield) on the sensitive substrate.
  • a group of a plurality of subfields arranged in a grid pattern is called a mechanical stripe, one direction of the grid is defined as an X direction, and the other direction is defined as a Y direction.
  • the illumination beam is deflected in the X direction to scan the beam, and in the Y direction, the master and the sensitive substrate are mainly continuously moved mechanically (mechanical scanning).
  • a charged particle beam exposure method for transferring the entire device pattern on the sensitive substrate by connecting the images of the patterns of the respective mask sub-finesses.
  • the exposure mode in the subfield row in the Y direction changes the deflection operation in the X direction of the charged particle beam, so that a transfer image of one of the complementary divided original patterns in the above row is formed.
  • the exposure mode in the subfield row in the X direction is changed so as to overlap the transfer image of the other complementary divided original pattern of the predetermined wafer subfield row on the sensitive substrate, and the charged particle beam Y
  • the deflection operation in the direction is changed, and the speed ratio between the original and the sensitive substrate in the mechanical scanning is changed, so that a transfer image of one of the complementary divided original patterns in the row is formed on the sensitive substrate.
  • a change can be made so as to overlap a transfer image of the other original pattern of the predetermined wafer subfield row that has been complementarily divided.
  • the subfield row in which the complementary divided pattern is arranged may be formed at an end of the mechanical stripe.
  • an original pattern of a device pattern to be transferred onto a sensitive substrate is divided into a plurality of collective exposure areas (mask subfields) arranged in a grid.
  • An original stage for moving and positioning the formed original (reticle and mask), an illumination optical system for sequentially applying a charged particle beam (illumination beam) to each subfield of the original, and passing through each subfield of the original
  • a projection optical system for sequentially projecting and imaging the charged particle beam (projection beam) onto a corresponding exposure area (wafer subfield) on the sensitive substrate, wherein the plurality of subfields arranged in a grid pattern are provided.
  • the illumination beam is deflected in the X direction to perform beam scanning.
  • the master and the sensitive substrate are exposed while mechanically continuously moving (mechanical scanning), and the image of the pattern of each mask subfield is joined on the sensitive substrate.
  • a plurality of the mechanical stripes are arranged on the original, and the two adjacent ones are arranged on the original.
  • the original stage and the sensitive substrate stage are aligned so that the transferred image of the mask subfield array at the end of the mechanical force-callus stripe overlaps the single wafer subfield array on the sensitive substrate. It is characterized by that.
  • an original pattern of a device pattern to be formed on a sensitive substrate is formed on an original, the original is illuminated with an energy beam, and the illuminated original pattern is projected and formed on the sensitive substrate.
  • Examples of the desired processing include complementary division, phase shift processing, and double exposure processing.
  • the overlap exposure of the complementary patterns is limited to a part of the entire device pattern, so that the cost for mask fabrication and the decrease in throughput can be suppressed.
  • the pattern to be complementarily divided is unevenly distributed around the chip and high exposure accuracy is required inside the chip, a decrease in the exposure accuracy of the pattern inside the chip can be suppressed.
  • FIG. 1 is a plan view (A) schematically showing two exposure areas on a mask, and a plan view (B) showing an image in which the two exposure areas on the mask are transferred onto a wafer.
  • FIG. 2 is a diagram schematically showing an image forming relationship in the exposure method according to the first embodiment of the present invention.
  • FIG. 3 is a view schematically showing an exposure method according to the second embodiment of the present invention.
  • FIG. 4 is a plan view (A) schematically showing an exposure area on a mask and a plan view (B) showing an image of the exposure area transferred onto a wafer.
  • FIG. 5 is a diagram schematically showing an image forming relationship in the exposure method according to the second embodiment of the present invention.
  • FIG. 6 is a plan view (A) showing an exposure area on a mask and a plan view (B) showing an image of the exposure area transferred onto a wafer.
  • FIG. 7 is a diagram showing an example in which a complementary pattern area extending in the Y direction is provided.
  • FIG. 8 is a diagram showing an outline of an imaging relationship and a control system in the entire optical system of the electron beam projection exposure apparatus of the division transfer system.
  • FIG. 9 is a diagram schematically showing an example of the configuration of a mask for electron beam projection exposure, wherein (A) is a plan view of the whole, (B) is a partial perspective view, and (C) is one small membrane. It is a top view of a Ren area.
  • FIG. 10 is a perspective view schematically showing the pattern transfer from the mask to the wafer.
  • FIG. 11 is a diagram schematically showing a chip pattern to be transferred to a wafer formed on a mask.
  • FIG. 8 is a diagram showing an outline of an imaging relationship and a control system in the entire optical system of the electron beam projection exposure apparatus of the division transfer system.
  • the electron gun 1 which is located at the uppermost stream of the optical system, directs the electron beam downward. Radiate. Below the electron gun 1, two condenser lenses 2 and 3 are provided, and the electron beam is converged by these condenser lenses 2 and 3 and a crossover C.O. Form an image.
  • a rectangular opening 4 is provided below the second-stage condenser lens 3.
  • This rectangular aperture (illumination beam shaping aperture) 4 allows only an illumination beam that illuminates one subfield (a pattern small area to be one unit of exposure) of a mask (including a reticle) 10 to pass.
  • the image of the aperture 4 is formed on the mask 10 by the lens 9.
  • a blanking deflector 5 is arranged below the beam forming aperture 4.
  • the deflector 5 deflects the illumination beam when necessary and hits the non-opening of the blanking opening 7 so that the beam does not hit the mask 10.
  • An illumination beam deflector (main deflector) 8 is arranged below the blanking opening 7.
  • the deflector 8 mainly scans the illumination beam sequentially in the horizontal direction (X direction) in FIG. 8 to illuminate each subfield of the mask 10 within the field of view of the illumination optical system.
  • An illumination lens 9 is disposed below the deflector 8. The illumination lens 9 forms an image of the beam shaping aperture 4 on the mask 10. .
  • the mask 10 actually extends in the plane perpendicular to the optical axis (the XY plane) (described later with reference to FIG. 9), and has a large number of subfields.
  • a pattern (chip pattern) forming a semiconductor device chip as a whole is formed on the mask 10.
  • a pattern forming one semiconductor device chip may be divided and arranged on a plurality of masks.
  • the mask 10 is placed on a movable mask stage 11, and by moving the mask 10 in the direction perpendicular to the optical axis (XY direction), the mask 10 spreads over a wider area than the field of view of the illumination optical system. Each subfield on the mask can be illuminated.
  • the mask stage 11 is provided with a position detector 12 using a laser interferometer so that the position of the mask stage 11 can be accurately grasped in real time.
  • Projection lenses 15 and 19 and a deflector 16 are provided below the mask 10.
  • the electron beam passing through one subfield of the mask 10 is imaged at a predetermined position on the wafer 23 by the projection lenses 15 and 19 and the deflector 16.
  • An appropriate resist is applied on the wafer 23, a dose of an electron beam is given to the resist, and the pattern on the mask is reduced and transferred onto the wafer 23.
  • a crossover C.O. is formed at a point that internally divides the mask 10 and the wafer 23 at a reduction ratio, and a contrast opening 18 is provided at the crossover position.
  • the opening 18 blocks the electron beam scattered by the non-pattern portion of the mask 10 from reaching the wafer 23.
  • the backscattered electron detector 22 is disposed immediately above the wafer 23.
  • the reflected electron detector 22 detects the amount of electrons reflected by the surface to be exposed and the mark on the stage. For example, by scanning the mark on the wafer 23 with a beam that has passed through the mark pattern on the mask 10 and detecting the reflected electrons from the mark at that time, the relative position between the mask 10 and the wafer 23 is determined. You can know the relationship.
  • the wafer 23 is placed on a wafer stage 24 movable in the X and Y directions via an electrostatic chuck (not shown). By synchronously scanning the mask stage 11 and the wafer stage 24 in directions opposite to each other, it is possible to sequentially expose each part in the chip pattern extending beyond the field of view of the projection optical system. Note that the wafer stage 24 is also provided with a position detector 25 similar to the above-described mask stage 11.
  • Each coil power supply control unit 2a, 3a, 9a, 15a, 19a and 5a, 8a, 16a is controlled by the controller 31 via the controller. Further, the mask stage 11 and the wafer stage 24 are also controlled by the controller 31 via the stage controllers 1 la and 24 a.
  • the stage position detectors 12 and 25 send signals to the controller 31 via interfaces 12a and 25a including an amplifier and an A / D converter.
  • the reflected electron detector 22 also sends a signal to the controller 31 via a similar interface 22a.
  • the controller 31 grasps a control error of the stage position and a position error of the pattern beam, and corrects the error by the image position adjusting deflector 16.
  • the reduced image of the subfield on the mask 10 is accurately transferred to a target position on the wafer 23.
  • the subfield images are joined on the wafer 23, and the entire chip pattern on the mask is transferred onto the wafer.
  • FIG. 9 is a diagram schematically showing a configuration example of a mask for electron beam projection exposure.
  • FIG. 9 (A) is a plan view of the whole
  • FIG. 9 (B) is a partial perspective view
  • FIG. 9 (C) is a plan view of one small membrane region.
  • Such a mask can be manufactured, for example, by performing electron beam drawing and etching on a silicon wafer.
  • FIG. 9 (A) shows the entire pattern divided arrangement state on the mask 10.
  • the area indicated by a large number of squares 41 in the figure is a small membrane area including a pattern area corresponding to one subfield (corresponding to the above-described batch exposure area, having a thickness of 0.1 ⁇ m to Several ⁇ m).
  • the small membrane region 41 is located in the central pattern region (sub-region).
  • Field) 4 2 and a frame-shaped non-pattern area (skirt 4 3) around the field 4 2.
  • Subfield 42 is a portion where a pattern to be transferred is formed.
  • the scar 43 is an area where no pattern is formed, and corresponds to the edge of the illumination beam.
  • One sub-field 42 has a size of about 1 mm square on a mask at present.
  • the reduction ratio of the projection is 1/4, and the size of the projected image in which the subfield is reduced and projected on the wafer is 0.25 mm square.
  • An orthogonal lattice-like minor flat portion 45 around the small membrane region 41 is a beam having a thickness of, for example, about 0.5 to 1 mm to maintain the mechanical strength of the mask.
  • the width of the minors flat 45 is, for example, about 0.1 mm.
  • the width of the skirt 43 is, for example, about 0.05 mm.
  • a number of small membrane regions 41 are arranged side by side in the horizontal direction (X direction) to form one group (electrical stripes 44), and such an electrical stripe is formed.
  • a number of lines 44 are arranged in the vertical direction (Y direction) in the figure to form one mechanical stripe 49 (corresponding to the above-described exposure area).
  • the length of the electrical stripes 44 (the width of the mechanical stripes 49) is limited by the size of the deflectable field of view of the illumination optical system.
  • a plurality of mechanical stripes 49 exist in parallel in the X direction.
  • the wide beams shown as major struts 47 between adjacent mechanical stripes 49, are intended to keep the overall mask deflection small.
  • the major strut 47 is integrated with the minor strut 45.
  • a row of subfields 42 in the X direction within one mechanical strip 49 (electrical strips) Steps 4 4) are sequentially exposed by electron beam deflection.
  • the rows in the Y direction in the stripe 49 are sequentially exposed by the continuous stage run.
  • FIG. 10 is a perspective view schematically showing the pattern transfer from the mask to the wafer.
  • One mechanical stripe 49 on the mask 10 is shown at the top of the figure. As described above, a large number of sub-fields 42 (the scar is not shown) and minor struts 45 are formed in the mechanical stripe 49. At the bottom of the figure, the wafer 23 facing the mask 10 is shown.
  • the sub-fino red (mask subfield) 42-1 in the left corner of the electrica / restripe 44 on the foreground of the mechanical canopy strip 49 on the mask 10 is controlled by the illumination beam IB from above. It is illuminated. Then, the pattern beam PB passing through the mask subfield 4 2-1-2 is operated by a two-stage projection lens (reference numerals 15 and 19 in FIG. 8) and an image position adjusting deflector (reference numeral 16 in FIG. 8). Predetermined area on 23 ( ⁇ ⁇ Hasfield) 5 2-1 is reduced and projected.
  • the transfer position of the mask subfield image on the wafer 23 is determined by the above-described image position adjusting deflector provided in the optical path between the mask 10 and the wafer 23, by a pattern corresponding to each pattern small area 42.
  • the transfer small area (wafer subfield) 52 is adjusted so as to be in contact with each other. That is, simply converging the pattern beam PB passing through the pattern small area 42 on the mask onto the wafer 23 by the first projection lens and the second projection lens is not limited to the pattern small area 42 of the mask 10. Even the image of the minor strut 45 and the image of the skirt are transferred at a predetermined reduction rate, and a non-exposed area corresponding to the non-pattern area such as the minor strut 45 is generated between the small areas 52 to be transferred. To avoid this, it is equivalent to the width of the non-pattern area. The image transfer position is shifted.
  • FIG. 1 (A) is a plan view schematically showing two exposure regions on a mask
  • FIG. 1 (B) is a plan view showing an image transferred to a wafer.
  • the reduction ratio is drawn as 1.
  • the exposure area on the mask shown in Fig. 1 (A) is composed of two mechanical stripes I and II (the area that can be exposed by one stage scan operation).
  • FIG. 2 is a diagram schematically showing an imaging relationship in an exposure method using a mask having such a configuration.
  • the mechanical stripes (1, II) are actually reduced and transferred to the wafer, but are shown in the same size as the mechanical stripe images ( ⁇ ′, ⁇ ) for convenience.
  • the width of the main force two callus tripe I, II image (I ,, II ') width W, the image of the complement main emission streams pattern regions A have A 2 of on the wafer (A, A 2,) Is d.
  • the mechanical stripe I on the mask 10 is exposed and transferred onto the wafer 23.
  • complementary Bruno, ° Turn-down area A i is transferred to the 'right end A x' of the image I of the mechanical stripe on the wafer 2 3.
  • each complementary pattern regions A have A 2, (in the example of figure shows a simplified like a dashed line) complement Mentha Li divided patterns P and P 2 are formed Have been. As shown in FIG.
  • one linear pattern (P + P 2 ′) is formed by overlapping so as to fill the gap between the broken lines.
  • the complementary pattern area is provided on the vertical side of the figure, but may be provided in the horizontal direction. If the chip boundary exists in the middle of the mechanical stripe (when the pattern corresponding to one chip ends in the middle of the mechanical stripe), the vertical length of the mechanical stripe is set to the chip length. You may need to adjust to size.
  • FIG. 3 is a diagram for explaining an exposure method according to an embodiment of the present invention using a mask of a complementary division system as a second example.
  • the mask is complementary divided pattern is formed in the sub-field a have a 2 of the deflection region end on the (reticle), an image of the a had a 2 overlap each other on the wafer Exposure as follows.
  • FIG. 3 (B) (in the figure, semicircular) complementary pattern included in the sub-field (mask subfield) a have a 2 on the mask image of the CP and CP 2 are on the wafer are joined together, ⁇ subfields on E wafer (wafer subfield) a + a 2 'circumferentially pattern CP + CP 2' is formed.
  • FIG. 3 (C) is a plan view schematically showing an exposure area on a mask
  • FIG. 4 (A) is a plan view schematically showing an exposure area on a mask
  • FIG. 4 (B) is a plan view showing an image of the exposure area transferred onto a wafer.
  • This embodiment is suitable for forming a square wiring pattern WP around the periphery of the chip as shown in FIG. 4 (B).
  • WP square wiring pattern
  • Figure 4 The four sides of the main force two callus tripe of (A), the completion main printer Li pattern area (the left side I have I 2, the right side J have J 2, sides K have K 2 above, the lower edge L 2 ) Is placed.
  • FIG. 5 is a diagram schematically showing an image forming relationship in an exposure method using such a mask.
  • the exposure area is actually reduced and transferred to the wafer, but for convenience, the exposure area is shown to be approximately the same size as the image of the exposure area.
  • an exposure method using such a mask will be described.
  • the mechanical stripe is exposed from the upper end of Fig. 4 ( ⁇ ).
  • the deflection mode of the optical system and the speed ratio of the mask stage and wafer stage hereinafter referred to as the exposure mode
  • the exposure mode are temporarily changed and transferred to the wafer.
  • exposing the ⁇ 2 so as to overlap with the image K ⁇ 'of.
  • FIG. 4 urchin by which (A), a have respective complementary pattern region I I 2, J 1, J 2, ⁇ , the K 2, L l L 2, broken-line complementary patterns are formed. These complementary patterns are superimposed on the wafer so as to fill the gaps between the broken lines, and as shown in FIG. 4B, a frame-shaped wiring pattern WP ( Ix '+ I 2 ', J!' + J 2 ⁇ K 1 '+ K 2 ,, L 1 ' + L 2 ').
  • a chip layout with a high degree of freedom can be realized.
  • FIG. 6 ( ⁇ ) is a plan view showing an exposure area on the mask.
  • FIG. 3 is a plan view showing an image of an exposure area transferred onto a wafer.
  • Konpurime emissions Tali pattern region (U have U 2, have V 2) is provided so as to extend in the X direction, rather than the end of the mechanical striped, inside Is provided.
  • the mode is changed to a mode for exposing the same line on the wafer in the middle of the mechanical striping, and the complementary pattern is exposed. That is, when exposing the complementary pattern area (! ⁇ And!; ⁇ V and V 2 ), the deflection mode of the optical system and the speed ratio between the mask stage and the wafer stage are temporarily changed. Thereby, complementary pattern exposure is performed.
  • a mechanical stripe is exposed from the upper end of FIG.
  • the deflection mode of the optical system and the speed ratio of the mask stage and the wafer stage (hereinafter referred to as exposure mode) are temporarily changed, and the image of exposing the U 2 to overlap the.
  • continued exposure Replace the exposure mode, after exposing the complementary pattern region V i, temporarily change the exposure mode again, exposing the V 2 so as to overlap with the V image of on the wafer. Then, the exposure mode is returned again to perform the exposure.
  • the pattern area 11 + U 2 'and V + V 2' is formed on the wafer.
  • the complementary pattern region on the mask is provided so as to extend in the X direction, but may be a complementary pattern region extending in the X direction.
  • FIG. 7 is a diagram showing an example in which a complementary pattern region extending in the ⁇ direction is provided.
  • a complementary divided pattern of another complementary area may be arranged in such a subfield and used for overlapping with a pattern of another area.
  • the complementary divider pattern of a subfield sequence of a region on the side opposite the P 2 region if there is such a region in the P region.
  • FIG. 11 is a diagram schematically showing a chip pattern to be transferred to a wafer formed on a mask used in an exposure method according to a fourth embodiment of the present invention.
  • semiconductor chips incorporate various functions into one chip, so high-precision exposure is required in some places, and in other places, very high-precision exposure may not be necessary.
  • Area A is an area where high-precision exposure is required, and it is necessary to perform predetermined processing to perform high-resolution exposure.
  • Area B is an area where relatively low-precision exposure is sufficient.
  • the predetermined processing is, in addition to the above-described complementary division, mask processing for publicly known high-resolution exposure, such as phase shift processing (see, for example, US Pat. No. 6,249,335).
  • phase shift processing only one mask is required.
  • the number of masks may be plural.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Electron Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Dans un premier temps, une bande mécanique I présente sur un masque (10) est transférée par exposition sur une plaquette (23). Une zone à motif complémentaire A1 est alors transférée sur l'extrémité droite A1' de l'image de la bande mécanique I' sur la plaquette (23). Ensuite, une bande mécanique II présente sur le masque (10) est transférée par exposition sur la plaquette (23). Par balayage de l'étage du masque et de l'étage de la plaquette, l'image II' de la bande mécanique est alors superposée à I' uniquement sur une largeur d, de sorte que l'image A2' de la zone à motif complémentaire A2 soit superposée à A1' sur la plaquette (23). Ainsi il est possible, lorsque des motifs à diviser sont concentrés au niveau d'une position donnée, de mettre en oeuvre un procédé d'exposition permettant de supprimer le coût lié au masque et d'améliorer la production.
PCT/JP2004/017043 2003-11-13 2004-11-10 Procede d'exposition et dispositif d'exposition Ceased WO2005048327A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008065320A (ja) * 2006-08-14 2008-03-21 Asml Masktools Bv 回路パターンを複数の回路パターンに分離する装置および方法
US8111901B2 (en) 2006-08-14 2012-02-07 Asml Masktools B.V. Apparatus and method for separating a circuit pattern into multiple circuit patterns

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JPH1126372A (ja) * 1997-07-08 1999-01-29 Nikon Corp 縮小転写方法及び縮小転写用マスク
JP2000250201A (ja) * 1999-03-03 2000-09-14 Nikon Corp パターン転写用マスクの製造方法及びパターン転写用マスク
JP2001308004A (ja) * 2000-02-16 2001-11-02 Nikon Corp 半導体装置の製造方法及び電子線露光方法
JP2001332468A (ja) * 2000-05-19 2001-11-30 Nikon Corp マスク、荷電粒子線露光方法、荷電粒子線露光装置及びデバイス製造方法
JP2003031485A (ja) * 2001-07-19 2003-01-31 Nikon Corp ステンシルマスク及び露光方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1126372A (ja) * 1997-07-08 1999-01-29 Nikon Corp 縮小転写方法及び縮小転写用マスク
JP2000250201A (ja) * 1999-03-03 2000-09-14 Nikon Corp パターン転写用マスクの製造方法及びパターン転写用マスク
JP2001308004A (ja) * 2000-02-16 2001-11-02 Nikon Corp 半導体装置の製造方法及び電子線露光方法
JP2001332468A (ja) * 2000-05-19 2001-11-30 Nikon Corp マスク、荷電粒子線露光方法、荷電粒子線露光装置及びデバイス製造方法
JP2003031485A (ja) * 2001-07-19 2003-01-31 Nikon Corp ステンシルマスク及び露光方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008065320A (ja) * 2006-08-14 2008-03-21 Asml Masktools Bv 回路パターンを複数の回路パターンに分離する装置および方法
US8111901B2 (en) 2006-08-14 2012-02-07 Asml Masktools B.V. Apparatus and method for separating a circuit pattern into multiple circuit patterns

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