WO2004112149A1

WO2004112149A1 - Trench-gate semiconductor devices

Info

Publication number: WO2004112149A1
Application number: PCT/IB2004/001908
Authority: WO
Inventors: Keith A. Jaggers; Stephen W. Hodgskiss; Mark A. Gajda
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2003-06-14
Filing date: 2004-06-04
Publication date: 2004-12-23
Anticipated expiration: 2005-12-14
Also published as: GB0313857D0

Abstract

A trench-gate semiconductor device is provided which includes a semiconductor body (10) comprising an active area (2) surrounded by an edge termination region (4). The semiconductor body defines a plurality of gate trenches (20) arranged in a stripe geometry across the active area (2) and groove (41) parallel to and between the gate trenches (20) extending through the source region (13) in the channel-accomodating region (15). A moated source configuration is employed to enable the source electrode (23) to contact the channel-accommodating region (15) of the device. An end trench portion (51) is provided towards each end of the gate trenches (20), beyond the ends (41a) of the grooves (41), which extends transversely with respect to the gate trenches and through the source region (13) to disconnect electrically the portions of the source region on opposite sides thereof. This prevents the formation of a parasitic transistor at the edges of the source and channel-accommodating regions (13,15).

Description

DESCRIPTION

TRENCH-GATE SEMICONDUCTOR DEVICES

The present invention relates to trench-gate semiconductor devices, for example insulated-gate field effect power transistors (commonly termed

"MOSFETs"), or insulated-gate bipolar transistors (commonly termed "IGBTs").

Known trench-gate devices comprise active device cells in a cellular active area of a semiconductor body. The active area is surrounded by an edge termination region to avoid premature breakdown at the perimeter of the active area. In a typical configuration, the active area comprises a source region and a drain region of a first conductivity type which are separated by a channel-accommodating region. Insulated gate electrodes are provided in trenches which extend through the source and channel-accommodating regions. The gate electrodes are arranged for controlling current flow in a conduction channel between the source region and the drain region in a conductive state of the device. The drain region may comprise a drain drift region and a drain contact region, with the drain drift region between the channel-accommodating region and the drain contact region, and the drain drift region doped to a lesser extent than the drain contact region.

Various gate trench geometries are known in such devices, including close-packed hexagonal or square geometries, for example. Another example is an elongate stripe geometry, in which parallel and mutually spaced gate trenches extend across the active area. The stripe geometry is particularly favoured in device applications in which an important requirement is minimisation of switching losses. It provides a low gate-drain capacitance, relative to a hexagonal geometry for example, which leads to relatively low power losses during switching.

The source region may be defined in each active device cell by a masked implantation step using a dedicated mask. Alternatively, the implantation may be a blanket implantation. Contact between the source metallisation over the semiconductor body and the channel-accommodating region to avoid parasitic bipolar action is then facilitated by etching grooves between the trenches which extend through the blanket source implanted region, to the underlying channel-accommodating region. Processing costs may be reduced by the latter approach by avoiding the need for the dedicated source mask step. Examples of such a "moated source" technique are disclosed in EP-A-620588 (our reference PHB33836) and EP-A-0889511 , and the whole contents of both documents are hereby incorporated herein as reference material. It enables the source regions to be defined in a self- aligned manner and so allows for an increase in cell packing density. The applicants sought to develop a trench-gate device which combined a stripe geometry with a moated source configuration, to obtain a device benefiting from the advantages of both approaches. However, they found that the performance of the prototype devices fabricated in this way suffered from surprisingly poor breakdown characteristics. Also, the gate threshold voltage was unexpectedly low and was not raised by varying the doping level of the channel-accommodating region.

It is an object of the present invention to provide a trench-gate device structure which overcomes the above problems. According to the invention, a trench-gate semiconductor device includes a semiconductor body comprising an active area surrounded by an edge termination region, the semiconductor body defining a plurality of gate trenches arranged in a stripe geometry across the active area, each gate trench having an insulated gate electrode therein, the active area comprising a source region and a drain region of a first conductivity type which are separated by a channel-accommodating region of a second opposite conductivity type, the gate trenches extending from a surface of the body through the source and channel-accommodating regions into the underlying drain region, the gate electrodes being arranged for controlling current flow in a conduction channel between the source region and the drain region in a conductive state of the device, the semiconductor body also defining grooves extending from the surface thereof and substantially parallel to and between the gate trenches, each groove being bounded by surface areas of the source region and the channel-accommodating region, wherein an end trench portion is provided towards each end of the gate trenches, with its outer side wall beyond the ends of the grooves, which extends transversely with respect to the gate trenches and through the source region to disconnect electrically the portions of the source region on opposite sides thereof.

The applicants believe that the poor performance of their prototype devices was caused by the formation of parasitic transistors at the edges of the source and channel-accommodating implanted regions. These parasitic transistors had channels significantly shorter than the device cells in the active area of the device, leading to the measured poor characteristics.

The end trench portions of the present invention, extending transversely with respect to the gate trenches, serve to break the connection between the source electrode and the parasitic transistors. This may be achieved without requiring an additional mask step to limit the extent of the source implanted region to prevent formation of the parasitic transistors.

In a preferred embodiment, each end trench portion extends through the channel-accommodating region to disconnect electrically the portions of the channel-accommodating region on opposite sides thereof. Preferably, the end trench portions are defined in the same process step as the definition of the gate trenches. Thus an additional mask step is not required to form the end trench portions.

The end trenches may be lined with a layer of insulating material and filled with the same material as is used to form the trenched gate electrodes. This material may be doped polycrystalline silicon for example. In this way, the end trenches can be filled without requiring any additional processing steps.

A prior art device and embodiments of the invention will now be described by way of example and with reference to the accompanying schematic drawings, wherein: Figure 1 shows a plan view of one example of a known trench-gate semiconductor device;

Figure 2 shows an enlarged plan view of a portion of the device of Figure 1 ; Figure 3 shows a perspective cross-sectional view of the device shown in Figure 2, cross-sectioned along mutually perpendicular lines A-A and B-B shown in Figure 2;

Figure 4 shows an enlarged plan view of a portion of a device embodying the present invention; Figure 5 shows a perspective cross-sectional view of the device shown in Figure 4, cross-sectioned along mutually perpendicular lines C-C and D-D shown in Figure 4; and

Figure 6 shows a similar cross-sectional view to that of Figure 5, showing a further embodiment of the invention.

It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

Figures 1 to 3 show one example of a known stripe trench-gate semiconductor device.

As shown in the plan view of Figure 1 , the device is divided into an active area 2 and a surrounding edge termination region 4. A cross-sectional view through the active cellular area 2 of this device is shown in Figure 3. Its structure is similar to the moated source configuration shown in EP-A-889511 referred to above. The process flow described in that document with reference to Figures 1 to 9 thereof is an example of a suitable method for the manufacture of a device having an active area of the form shown in Figure 3 of the present specification. It will be appreciated that the present invention is applicable to other moated source geometries and/or methods for the manufacture thereof. Each transistor cell has a channel-accommodating region 15 of a second conductivity type (p-type in this example) that separates source and drain regions 13 and 14, respectively, of a first conductivity type (n-type in this example). The drain region 14 is common to all the cells. The device has a trench-gate 11 in an insulated trench 20 that extends through the regions 13 and 15 into an underlying portion of the drain region 14. The gate 11 is capacitively coupled to the region 15 by an intermediate dielectric layer 17 at the walls of the trench 20. The application of a voltage signal to gate 11 in the on-state of the device serves in known manner for inducing a conduction channel 12 in the region 15 and for controlling current flow in this channel 12 between the source and drain regions 13 and 14.

The source region 13 is located adjacent to the top major surface 10a of the device body 10, where regions 13 and 15 are contacted by a source electrode 23. The trench-gate 11 is insulated from the overlying electrode 23 by an intermediate dielectric overlayer 33. Typically the MOSFET of Figures 1 to 5 is a vertical power device structure. The region 14 is a drain-drift region, which may be formed by an epitaxial layer of high resistivity on a more highly-doped substrate 14a of the same conductivity type. The substrate 14a is contacted at the bottom major surface of the device body 10 by a drain electrode (not shown). A groove or moat 41 extends from the top major surface 10a, through the source region 13, to the channel-accommodating region 15. Thus, the groove is defined and bounded by surface areas of the source region and channel- accommodating region. This allows the source electrode 23 form a good contact with the source region at the side walls of the groove 41. The source electrode also contacts the channel-accommodating region at the bottom of the groove.

The edge termination region 4 comprises a field relieving structure 24 for preventing premature breakdown at the edge of the device when operating in blocking mode. In the illustrative example of Figure 3, the field relieving means comprises a field plate 25. Peripheral trench 27 accommodates an electrode 29 over insulating layer 17, the electrode being integral with the field plate 25. The electrode 29 and field plate 25 may be formed of doped polycrystalline silicon for example. It will be apparent that the edge termination structure shown in Figure 3 is just one of many edge termination configurations known in the art and that the applicability of the invention is not limited to any particular configuration. Another approach is described in WO2003/021684 (our reference PHGB010192), the whole contents of which are hereby incorporated herein as reference material. In this approach, the polysilicon layer 25 is divided into fingers extending over the active area instead of having a continuous sheet of polysilicon. The polysilicon fingers may be used to reduce manufacturing costs or to overcome various design constraints.

Field plate 25 is insulated from the source electrode 23 by the intervening dielectric layer 33, formed of tetra-ethyl-ortho-silicate (TEOS) for example.

The embodiment shown in Figure 3 also includes a p region 35 in the field relieving structure 24 of the edge termination region 4, which extends from the top major surface 10a to a boundary 37 shown by a dashed line in Figure 3. It is deeper than, and may have about the same or a marginally higher doping level than the channel-accommodating region 15. In this embodiment, the innermost edge of p region 35 may be considered to define the perimeter of the active area 2 and the start of the edge termination region 4. It will be appreciated that other termination configurations may not include such a region.

Figure 2 shows a plan view of the structure shown in Figure 3, with the dielectric layer 33 and source electrode 23 removed to reveal the underlying features for the purposes of illustration.

The inventors believe that a parasitic transistor having a channel 43 may be formed by the configuration of Figure 3, where the source and channel- accommodating region implantations terminate at top major surface 10a. An NPN transistor is formed (or a PNP transistor in an embodiment with reverse conductivities relative to Figure 3) which exhibits a normal gated MOS transistor action, with field plate 25 acting a gate. However, its channel 43 is somewhat shorter than the channels 12 of the active area transistors. This is because no mask is used during the implants which form the source region 13 and channel- accommodating region 15 in a moated source approach, and diffusion of these implants underneath polysilicon layer 25 results in tapering of the channel- accommodating region 15 towards the top major surface 10a at the edges of the implanted regions. Certain device parameters (such as breakdown voltage, gate threshold voltage, for example) are degraded in the parasitic transistor relative to the transistors formed in the active area 2 of the device. The performance of the device as a whole is thereby degraded.

Although one might expect the formation of a parasitic transistor in this way to be prevented by the deep p region 35 included in Figure 3, this is not observed in practice because of the complex three-dimensional nature and uncontrolled diffusion of regions 13 and 15 under the polysilicon layer 25. The very short channel 43 shown in Figure 3 is only one possible location of the resulting parasitic transistor. There may for example be other such transistors formed near to or at the end of each gate trench on the vertical sidewalls of the trench. Figures 4 and 5 correspond to the views shown in Figures 2 and 3, respectively, but show a device modified in accordance with an embodiment of the invention. An additional end trench 51 is provided in the semiconductor body 10. It is substantially rectilinear, and extends substantially perpendicular to, and intersects with, the gate trenches 20. Its outer side wall 51b (that is, the side wall further from the active area) is located beyond the ends 41a of grooves 41 , in a direction parallel with the grooves. It extends vertically through the source region 13 and channel-accommodating region 15, into the underlying drain drift region 14. However, it would be sufficient for the end trench to extend through the source region but not the channel- accommodating region in order to prevent the parasitic transistor action. In the example of Figure 4, it is also extends into and partway through the deep p region 35. In other embodiments, it may extend completely through region 35. The end trench 51 serves to disconnect the source and channel- accommodating regions 13a and 15a on the outer side of the end trench from the source and channel-accommodating regions 13 and 15 of the active area 2. The regions 13 and 15 on the inner side of the end trench are electrically connected to the source electrode 23 at the groove 41. Regions 13a and 15a are electrically isolated by the end trench from the source electrode 23, which does not contact the upper surface of the region 13a owing to the presence of the overlying dielectric layer 33. The end trench 51 thereby prevents the parasitic transistor action at the edges of the source and channel- accommodating region implants exhibited by the structure of Figures 2 and 3.

In the embodiment illustrated in Figure 5, the end trench 51 is located in the edge termination region 4 of the device, between the active area 2 and the field relieving structure 24, within the area of p region 35. As shown, it is spaced from the end 41a of the groove 41. However, it may be provided closer to the active area than p region 35. So long as its outer wall 51b is beyond the end of grooves 41 , the end trench will provide the required disconnection of the source electrode contacted region 13 and the outer source region 13a.

For processing convenience, the end trench 51 , a dielectric layer 53, and filler material 55 are formed in the same processing steps as the gate trenches 20, dielectric layer 17 and gates 11 , respectively. However, in more complex manufacturing process flows (for example, in smart power devices), the end trench 51 and/or dielectric layer 53 may be formed in different stages to the trenches 20 and dielectric layer 17 of the main trench network of the device.

The location of the end trench longitudinally along the gate trenches may vary across the device, for example, to accommodate localised additional features in the edge termination region. The distance to which the gate trenches extend beyond the end trench may also be varied across the device to suit particular requirements. Furthermore, whilst the end trench is shown in Figure 4 as rectilinear, it will be apparent that other geometries may be suitable in other configurations.

In the configuration of Figure 5 (and also Figures 3 and 6), the groove 41 is shown as extending laterally into the area over which p region 35 extends. However, in other embodiments, the groove may stop short of region 35. In that case, as noted above, end trench 51 may also be located outside region 35. In some devices, it may be sufficient for end trenches 51 to be provided across the ends of the gate trench stripes and not along the edges of the active area parallel with the stripes. In particular, the outermost gate trenches may be arranged such that the source electrode does not make contact with the source region 13 on the outer side of these gate trenches, thereby avoiding formation of parasitic transistors in the manner described above along these edges. Alternatively, in configurations where the source electrode does contact these outer source regions, the end trench may be arranged to extend around the entire periphery of the active area 2, surrounding it to prevent the formation of parasitics.

It will be apparent to those skilled in the art that the end trench structure of the present invention is compatible with fabrication in the same process steps as features of a variety of active area configurations. For example, the thickness of the insulating layer over the bottom and sidewalls of the end trench may be varied without affecting the function of the end trenches. It may be desirable to include a thicker insulating layer at the bottom of the gate trenches in the active area, which may serve to reduce the gate-drain capacitance of the active area transistors, reducing the level of switching power losses in those devices. This particular example is illustrated in Figure 6. The layer 53 of dielectric material over the bottom 51a of the end trench 51 is thicker than over at least a portion of the side walls 51b, 51c of the end trench. The thickness of dielectric layer 17 in the gate trenches 20 is varied in the same manner.

From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the art, and which may be used instead of or in addition to features already described herein.

The particular examples described above are n-channel devices, in which the source and drain regions 13 and 14 are of n-type conductivity, the channel-accommodating body region 15 is of p-type conductivity, and an electron inversion channel 12 is induced in the region 15 by the gate 11. By using opposite conductivity type dopants, a p-channel device can be made which embodies the invention. In that case, regions 13 and 14 are of p-type, the region 15 is of n-type, and a hole inversion channel is induced in the region 15 by the gate 11. Semiconductor materials other than silicon may be used for devices in accordance with the invention, for example, silicon carbide.

Although Claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

The Applicants hereby give notice that new Claims may be formulated to such features and/or combinations of such features during the prosecution of the present Application or of any further Application derived therefrom.

Claims

1. A trench-gate semiconductor device including a semiconductor body (10) comprising an active area (2) surrounded by an edge termination region (4), the semiconductor body defining a plurality of gate trenches (20) arranged in a stripe geometry across the active area, each gate trench having an insulated gate electrode (11) therein, the active area (2) comprising a source region (13) and a drain region (14) of a first conductivity type which are separated by a channel-accommodating region (15) of a second opposite conductivity type, the gate trenches (20) extending from a surface (10a) of the body through the source and channel-accommodating regions into the underlying drain region, the gate electrodes (11) being arranged for controlling current flow in a conduction channel (12) between the source region and the drain region in a conductive state of the device, the semiconductor body also defining grooves (41) extending from the surface (10a) thereof and substantially parallel to and between the gate trenches (20), each groove being bounded by surface areas of the source region (13) and the channel- accommodating region (15), wherein an end trench portion (51) is provided towards each end of the gate trenches, with its outer side wall (51b) beyond the ends (41a) of the grooves (41), which extends transversely with respect to the gate trenches and through the source region to disconnect electrically the portions of the source region on opposite sides thereof.

2. A device of Claim 1 wherein each end trench portion (51) extends through the channel-accommodating region (15) to disconnect electrically the portions of the channel-accommodating region on opposite sides thereof.

3. A device of any preceding Claim wherein the end trench portions (51) are formed in the same process step as the gate trenches (20).

4. A device of any preceding Claim wherein the end trench portions (51) are substantially rectilinear.

5. A device of any preceding Claim wherein the end trench portions (51) are part of an end trench which surrounds the active area (2) and extends through the source region (13) to disconnect electrically the portions of the source region on opposite sides thereof.

6. A device of any preceding Claim wherein a layer (53) of insulating material is provided over the side walls (51b, 51c) and bottom (51a) of the end trench portions (51), and the layer is thicker over the bottom than over at least a portion of the side walls.