WO2004038917A1 - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit arranged at the front and back state of a combination logical circuit and having a latch circuit capable of latching input data according to a clock signal from a clock pulse generator. It is possible to eliminate the affect of indeterminateness of the clock edge by setting the signal transfer delay time Tcq in the latch circuit based on the rise of the clock pulse, the setup time Tsetup in the latch circuit, the signal transfer delay time Tdq from the input terminal to the output terminal of the latch circuit, indeterminateness at the rise edge of the clock pulse ± Tskew1, indeterminateness at the trailing edge of the clock pulse ± Tskew2, and the pulse width Tw of the clock pulse so as to satisfy the relationship of Tw ≥ Tcq + Tsetup + Tskew1 + Tskew2 - Tdq.

Description

 Description Semiconductor integrated circuit technology

 The present invention relates to a semiconductor integrated circuit and, more particularly, to a high-speed and low-power technology therein. Background art

 An important elemental circuit for improving the performance and reducing the power of a semiconductor integrated circuit is a storage element represented by a flip-flop (hereinafter abbreviated as “FF”) circuit or a latch circuit. Therefore, various circuits and clock systems have been proposed for the purpose of increasing the speed and lowering the power of FF circuits or latch circuits.

 For example: Single-phase clock using an FF circuit 'edge trigger system (referred to as "first known circuit") or two-phase clock / latching system using level sense latch circuit (referred to as "second known circuit") For example, see “A. Chandrakasan, et al.,“ Design of High-Performance Microprocessor Circuits, ”IEEE Press, pp. 207-234, 2001”.

 The first known example circuit is a technology adopted by many semiconductor manufacturers in Japan and overseas, and is widely used because of its design simplicity and compatibility with DFT (Design For Test).

On the other hand, in the second known example circuit, STA (Static Timing Analysis) becomes complicated, and a two-phase clock is required. ing. · Also, there is known a technology related to a single-phase clock / pulse trigger latch system (referred to as a “third known example circuit”) in which an FF circuit is replaced with a pulse trigger latch. For example, "L. Clark," An Embedded 3Z-b

Microprocessor Core for Low-Power and High-Performance

Application, "IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1599-1608, Nov. 2001". This technique provides a function similar to that of an FF circuit by supplying a very short pulse pulse to the latch. Although it is a latch-based system, it has features such as a single-phase, rather than two-phase, and the ability to handle STAs in the same way as FF circuit systems.

 It is known that the output of the master latch is used for a path with a long delay, and the output of the slave latch is used for a path with a small delay. For example,

See Japanese Patent Application Publication No. 8-97685.

It is known that a single-phase clock-age trigger system using an FF circuit needs to satisfy a predetermined relational expression in order for the system to operate properly. See, for example, S. Unger, et al., "Clocking Schemes for High-Speed Digital Systems ₅ ^M IEEE Transactions on Computers, Vol. C-35, pp. 880-895, Oct. 1986".

In addition, a system using an FF circuit uses a FF circuit that operates on the rising edge of the clock signal during normal operation of the circuit, and uses an FF circuit that operates on the rising and falling edges during scanning in series. In a circuit (for example, see Japanese Patent Application Laid-Open No. H10-2697994), in a normal mode of the circuit, the slave is bypassed to output data from the master and the slave, and in the diagnostic mode, there is an FF that operates as a slave. 2. Description of the Related Art A semiconductor integrated circuit (for example, see Japanese Patent Application Laid-Open No. Hei 5-191222) is known. In this specification, “flip-flop (FF)” and “latch I” The terms are used in the following definitions. “Flip-flop (FF)” refers to a memory element that captures an input signal at the rising edge of the clock. “Latch” transmits an input signal to the output while the clock is “H” and the clock is “L”. This is a so-called level sense type circuit that holds the output signal for a period of ".

 Here, in the circuit of the first known example, the clock signal CK has a cycle time represented by Tcycle, and its rising edge is caused by the jitter component of the clock generator and the skew in the clock distribution system. It has certainty. The time from when the clock signal CK rises to when the signal is output from the output terminal (Q) is Tcq, and the setup time of the FF circuit (clock after the input signal from the data input terminal (D) is determined Let Tsetup be the time margin required for the signal CK to rise, and Thold the hold time (the time during which the input signal must be held from the rise of the clock signal CK). When the delay time of the combinational logic circuit between F F and F F is Tlogic, the following two equations must be satisfied for the system to operate properly. These derivations are described in, for example, "S. Unger, et al.," Clocking Schemes for High-Speed Digital Systems, "IEEE Transactions on Computers, Vol. C-35, pp. 880-895, Oct. 1986. familiar with j.

Tcycle ≥ Tcq + Tlogic + Tsetup + 2Tskewl-(1)

Tlogic> Thold + 2Tskewl-Tcq-(2)

Equation (1) is a relational expression representing the maximum delay constraint, and equation (2) is a relational expression representing the minimum delay constraint. Note that the maximum delay constraint is a condition that specifies the minimum cycle time of the system, and the minimum delay constraint is a condition for preventing race-through between pipeline stages. Consider the minimum delay constraint expressed by equation (2) You. In general, Thold-Tcq appearing on the right side of equation (2) is often very small. Therefore, the minimum delay time Tlogic of the combinational logic circuit required to guarantee the minimum delay can be a relatively small value. For example, in the case where two FF circuits are coupled, a circuit having a delay time of about 2 Tskewl can be inserted between them to easily avoid the inconvenience of the minimum delay. And this is one of the major factors that makes single-phase clock edge triggering systems mainstream today. It should be noted, however, that in equation (1), the right-hand side contains the uncertain component Tskewl of the clock edge. That is, the minimum cycle time Tcycle in the first known example circuit increases by the uncertainty of the clock edge. The third term on the right side includes the setup time Tsetup of the FF circuit, which also increases the minimum cycle time Tcycle. Furthermore, the FF circuit tends to increase the load on the clock terminal CK, which tends to increase power consumption and clock skew. Therefore, it is considered that the first known example circuit is not suitable for increasing the speed of the semiconductor integrated circuit.

 A third known example circuit is configured by taking advantage of the first known example circuit and the second known example circuit. By replacing the FF circuit with a latch circuit and supplying the clock signal CK having a very short Tw during the "H" period to the latch circuit, the same function as the edge trigger operation by the FF circuit can be realized. Thus, when Tw is very small, the relation between the minimum cycle time and the minimum delay constraint is as follows.

Tcycle ≥ Tcq + Tlogic + Tsetup + Tskewl + Tskew2 -TwT '(3) Tlogic> Thold + Tskewl + Tske 2 Tcq + Tw-(4)

Equation (3) is a relational expression defining the lower limit of the cycle time, and equation (4) is a relational expression representing the minimum delay constraint. Compare expressions (3) and (1) It can be seen that the value of equation (3) is smaller by the last term on the right side. Although it is not clear from the equation, the latch circuit generally has a smaller Tcq + Tsetup than the FF circuit, and therefore the lower limit of the cycle time can be reduced by using the latch circuit. . However, there is an inconvenience about the minimum delay constraint. Comparing Eqs. (4) and (2), it can be seen that Eq. (4) has a larger value for the last term on the right side. In other words, the delay time of the circuit inserted to guarantee the minimum delay increases according to the width Tw of the peak pulse. It should be noted here how the Tw term affects the minimum cycle time and the minimum delay constraint. According to equation (3), the lower limit of the cycle time can be reduced by increasing the pulse width Tw. On the other hand, according to equation (4), increasing the pulse width Tw does not guarantee the minimum delay. This leads to an increase in the delay amount of the delay circuit required for this. The minimum delay is a very dangerous factor, and if any circuit does not observe this restriction, the system will never work. Therefore, the designer has to make a conservative design for the minimum delay, and as a result, the effect of Tw on improving the cycle time is impaired. According to the equations (1) and (3), the minimum cycle time Tcycle of both the first known example circuit and the second known example circuit increases under the influence of clock skew. Therefore, in order to improve the performance of the system, it was necessary to dedicate much time and effort to reduce the clock skew, resulting in an increase in design cost and design time. Even with such a clock system designed with much effort and time, it is almost impossible physically to set the clock skew to zero.

According to Japanese Patent Application Laid-Open No. Hei 8-97765, the output of the master latch is used for the path having a large propagation delay time of the combinational logic. For small passes, the output of the thread latch is used. This aims to speed up the circuit and avoid inconveniences related to minimum delay. It also states that even if the clock edge slightly shifts due to clock skew, no over-delay will occur. However, according to a detailed study by the inventor, whether or not the clock skew is completely absorbed is determined by the clock pulse width, the latch setup time, the clock skew amount, and the like. It has been found that the configuration described in Japanese Patent Application Publication No. 75685 is not immediately determined. In addition, it is difficult to design without minimum criteria even for the minimum delay constraint, and as a result, design guidelines that secure a large design margin must be followed, making efficient design difficult.

 An object of the present invention is to provide a technique for eliminating the influence of clock edge uncertainty on a circuit that determines the maximum operation speed of a semiconductor integrated circuit.

 Another object of the present invention is to provide a technique for improving the operation speed of the entire circuit and at the same time reducing power consumption.

 The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings. Disclosure of the invention

 The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, a clock pulse generator that generates a pulsed clock signal, a predetermined combinational logic circuit, and a circuit arranged before or after the combinational logic circuit, and capable of latching input data based on a clock signal from the clock pulse generator Semiconductor integrated circuit including a simple latch circuit The signal propagation delay time in the latch circuit with reference to the rising edge of the clock pulse is Tcq, the setup time in the latch circuit is Tsetup, and the signal propagation delay from the input terminal to the output terminal of the latch circuit. When the time is Tdq, the uncertainty at the rising edge of the clock pulse is Tskewl, and the uncertainty at the falling edge of the clock pulse is Tskew2, the pulse of the clock pulse is such that the following equation is established. Setting the width Tw eliminates the effects of clock edge uncertainty.

 Tw ≥ Tcq + Tsetup + Tskewl + Tskew2- Tdq Brief description of drawings

 FIG. 1 is a block diagram of a configuration example of a latch system included in a combination system as an example of a semiconductor system according to the present invention. FIG. 2 is an operation waveform diagram of a main part in the latch system. FIG. 3 is a detailed circuit diagram of a main part in FIG.

 FIG. 4 is a detailed circuit diagram of a main part in FIG.

 FIG. 5 is a detailed circuit diagram of a main part in FIG.

 FIG. 6 is an operation waveform diagram of a main part in the latch system shown in FIG.

 FIG. 7 is an operation waveform diagram of a main part in the latch system shown in FIG.

 FIG. 8 is an operation waveform diagram of a main part in the latch system shown in FIG.

 FIG. 9 is an operation waveform diagram of a main part in the latch system shown in FIG.

FIG. 10 shows the operation of the main part in the latch system shown in FIG. It is a waveform diagram <

 FIG. 11 is an operation waveform diagram of a main part in the latch system shown in FIG. 1,

 FIG. 12 is an operation waveform diagram of a main part in the latch system shown in FIG. 1,

 FIG. 13 is an operation waveform diagram of a main part in the latch system shown in FIG.

 FIG. 14 is a block diagram of another configuration example of the latch system. FIG. 15 is an operation waveform diagram of the system shown in FIG. FIG. 16 is a block diagram showing another example of the configuration of the latch system. FIG. 17 is a circuit diagram of a configuration example of a main part in FIG.

 FIG. 18 is a circuit diagram showing an example of the configuration of the FF circuit included in the latch system.

 FIG. 19 is a block diagram showing a configuration example of the computer system. FIG. 20 is an explanatory diagram of a list of various parameters used in the latch system. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 19 shows a combination system which is an example of the semiconductor system according to the present invention. The system 1101 shown in FIG. 19 is a central processing unit (abbreviated as “CPU”) 1100 that performs arithmetic processing according to a predetermined program, and is not particularly limited. And peripheral circuits. The peripheral circuits include, but are not limited to, an external memory controller 1104, a cache memory 1105, and an external memory 1106. The CPU 111 and the external memory controller 1103 and the cache memory 1105 communicate with each other via the bus 1103. Are communicatively coupled to

 The bus 1103 includes an address bus for transmitting an address signal and a data bus for transmitting a data signal. The external memory controller 1104 controls the read / write of the external memory 1106. The external memory 1106 is a dynamic random access memory (abbreviated as “DRAM”) including, but not limited to, a dynamic memory element. The DRAM 1106 stores programs executed by the CPU 1101 and various data used for arithmetic processing. Then, such programs and various data are read into the CPU 1101 under the control of the external memory controller 1104. The programs and data read from the external memory 1106 are temporarily stored in the cache memory 1105. When a program or data is requested again by the CPU 1101, the cache memory 1105 is accessed prior to the external memory 1106. If a program or data re-requested by the CPU 1101 exists in the cache memory, it is used so that the program download can be performed faster than accessing the external memory 1106 via the external memory controller 1104. You can get an overnight. If the program data requested again by the CPU 1101 does not exist in the cache memory, the external memory 1106 is accessed via the external memory controller 1104.

The CPU 1101, the external memory controller 1104, the cache memory 1105, and the external memory 1106 are each formed of, but not limited to, a semiconductor integrated circuit. In the CPU 1101, the external memory controller 1104, the cache memory 1105, and the external memory 1106, a combinational logic for performing a predetermined logical operation is provided. A latch circuit that includes a logic circuit and a latch circuit that is arranged before or after that and that can hold input data based on a clock pulse is used everywhere.

 FIG. 1 shows a main configuration of a latch system applied to the CPU 1101 and its peripheral circuits (1104, 1105, 1106). FIG. 20 shows a list of definitions of various parameters used in this example. Further, FIG. 2 shows the operation waveforms of the main part and the various parameters in the latch system shown in FIG.

 An FF circuit-based edge trigger system is easy to design with minimal delay constraints, but is not suitable for high-speed operation due to the effects of clock edge uncertainty and the delay time of the FF circuit itself. In addition, the latch circuit-based pulse trigger system has a small delay time of the latch circuit itself, but does not ignore the care of the minimum delay and the effects of clock edge uncertainty. In contrast, the latch system shown in Fig. 1 combines the minimum delay resistance of the edge trigger system with the high-speed / low power characteristics of the pulse trigger system, and is not affected by clock edge uncertainty. Is done. '

 The latch system 10 shown in FIG. 1 includes, but is not limited to, a clock pulse generation circuit 100 and latch circuits 101, 102, and 103. The clock pulse generator 100 generates a pulsed clock signal CK. The generated clock signal CK is supplied to the latch circuits 101, 102, and 103.

 Assuming that a period in which the clock signal CK is at a logically high potential level (hereinafter referred to as “H” level) is Tw, this period Tw is

T ≥ Tcq + Tsetup + Tskel + Tskew2-Tdq-(5)

Meet the relationship. Here, Tcq is output from the clock pin (CK). It means the signal propagation time to the input terminal (Q), and is the value assuming that the input signal D arrives fast enough to the rising edge of the clock signal CK. Tsetup means setup time. Tskewl is the uncertainty of the clock rising edge due to skew and jitter, and Tskew2 is the uncertainty of the clock falling edge due to skew and jitter. Tdq means the propagation delay time from the data terminal (D) to the output terminal (Q). The value is based on the assumption that the clock signal CK goes to the "H" level sufficiently early with respect to the changing point of the data terminal (D).

 The output of the latch circuit 101 is input to the combinational logic circuit 113, and is input to the latch circuit (102) after the propagation delay time (Tlogic-max) in the combinational logic circuit 113 . Here, Tlogic-max represents the combination logic circuit with the longest propagation delay time. Of the two output terminals (Q, QD) of the latch circuit 102, the side whose value is output in synchronization with the falling edge of the clock signal CK (QD) is connected to the combinational logic circuit 114 and propagated. It is input to the latch circuit 101 after the delay time Tlogicjnin. Here, logic 1 min represents the combinational logic circuit with the shortest propagation delay time.

Note that, in the configuration example shown in FIG. 1, the output of the combinational logic circuit 113 is input to the latch circuit 102, but this is not so limited. It may be input to 101. The output of the combinational logic circuit 114 may also be connected to the latch circuit 102, but if the propagation delay time Tlogic_min is included in the range of the equation (6), the output of the combinational logic path The starting point starts from the output terminal (QD) of the latch circuit 102. If the propagation delay time Tlogic_max falls within the range of the equation (7), the starting point of the combinational logic path is the output of the latch circuit 101 or Of the two output terminals of the latch circuit 102 The signal must start at the output terminal (Q) on the side that is transparent while the clock signal C is at the "H" level.

Tcycle-1 2Tskew2-Tcqd-Tsetup> Tlogic-min> Thold + 2 Tskew2-Tcqd ~ (6)

Tcycle-Tdq> Tlogic— max> Thold + Tskewl + Tskew2-Tcq + Tw-(7)

 FIG. 3 shows a configuration example of the latch circuit 102 in FIG. The latch circuit 102 includes, but is not limited to, inverters 210 to 218, n-channel MOS transistors 202 and 203, and p-channel MOS transistors 201 and 204. The first tri-state buffer 221 is formed by connecting the n-channel MOS transistor 203 and the p-channel MOS transistor 201 in parallel, and the n-channel MOS transistor 202 and the p-channel MOS transistor 201 are connected. A second tri-state buffer 222 is formed by connecting the transistor 204 in parallel.

 The logic of the clock signal input via the clock pin (CK) is inverted at the inverter 211, and further inverted at the subsequent inverter 211. The operation of the p-channel type MOS transistor 201 and the n-channel type MOS transistor 203 is controlled by the output signal of the above-mentioned inverter 210. The operation of the p-channel type MOS transistor 204 and the n-channel type MOS transistor 202 is controlled by the output signal of the above-mentioned inverter 211. As a result, the first tri-state buffer 221 and the second tri-state buffer 222 are turned on complementarily.

The first latch portion 231 is formed by connecting the inverters 213 and 214 in a loop, and the second latch portion 232 is formed by connecting the inverters 215 and 216 in a loop. Input from data terminal (D) The data thus input is input to the first latch unit 231 via the receiver 212 and the tristate buffer 221. The output signal from the first node N1 of the first latch unit 231 is output from the output terminal (Q) via the inverter 217, and the output signal from the second node N2 of the first latch unit 231 is output. The signal is input to the second latch unit 232 via the second tri-state buffer 222. Then, the output signal of the second latch unit 232 is output from the output terminal (QD) via the receiver 218 at the subsequent stage. During the period when the clock terminal (CK) is at the “H” level, the signal level input to the data terminal (D) is transmitted to the output terminal (Q), and the clock signal CK is at a logically low potential level (hereinafter “ When the signal level becomes “L” level), the signal level input to the data terminal (D) is held until immediately before, and the signal level is continuously output from the output terminal (Q). When the clock signal CK changes from "H" level to "L" level, the signal level input to the data terminal (D) is transmitted to the output terminal (QD), and then it is held . Therefore, the circuit shown in FIG. 3 is a level sense latch circuit when viewed from the output terminal (Q), and is a negative edge trigger flip-flop circuit when viewed from the output terminal (QD). '

 FIG. 4 shows a configuration example of the latch circuits 101 and 103 in FIG.

 Latch circuits 101 and 103 are

313, 314, 317, an n-channel MOS transistor 303, and a p-channel MOS transistor 321. The n-channel MOS transistor 303 and the p-channel MOS transistor 32 1 are connected in parallel to form a tri-state buffer 32 1, and the latch circuits 331 and 314 are formed in a loop to form the latch circuit 331. Is done. The logic of the clock signal input via the clock pin (CK) is inverted by the inverter 311 and further inverted by the subsequent inverter 311. The operation of the p-channel type MOS transistor 301 and the n-channel type MOS transistor 303 are controlled by the output signal of the above-mentioned inverter 310.

 This circuit is a so-called level sense latch circuit. While the clock terminal (CK) is at the "H" level, the signal level input to the data terminal (D) is transmitted to the output terminal (Q), and the clock signal CK Becomes low voltage level (hereinafter referred to as "L" level), keeps the signal level input to the data terminal (D) until immediately before, and continues to output it from the output terminal (Q) .

 FIG. 5 shows a configuration example of the clock pulse generator 100 in FIG.

The clock pulse generator 100 obtains a NAND circuit of a delay circuit (DE LAY) 400 for determining the pulse width of the clock signal CK, an output signal of the delay circuit 400, and a global clock signal GCK 2 It comprises an input NAND circuit 401 and an inverter 402 arranged downstream thereof. The control signal EN is input to the delay circuit 400. When the control signal EN is in the enable state, the output of the clock signal CK is enabled by operating the delay circuit 400. When the global clock signal GC changes from "L" level to "H" level, the clock signal CK changes from "L" level to "H" level. Then, after the propagation delay time of the delay circuit 400, the clock signal CK changes to "L" level. Since the propagation delay time of the delay circuit 400 determines the pulse width of the clock signal CK, the delay time of the delay circuit 400 is adjusted so that the clock pulse width Tw satisfies the expression (5). The latch system 10 having the above configuration can operate at higher speed and lower power than the above-mentioned known example circuit. The reason is described below.

 First, how the minimum cycle time (maximum operating frequency) of the latch system 10 is determined will be described.

 As shown in FIG. 6, the data fetched by the latch circuit 101 in the first cycle started at time t = 0 passes through the combinational logic circuit 113, and in the second cycle, the data of the next latch circuit 102 In order to be input to the latch circuit 102, the input signal from the data terminal (D) in the latch circuit 102 must be determined by the time shown by the equation (8).

t = Tcycle + Tw-(Tsetup + Tske 2) '' (8)

 Equation (8) is the minimum rule for the correct operation of the circuit. Here, there are two cases according to the arrival time of the input signal in the first cycle.

 <When the input signal from the data terminal (D) is determined quickly>

 FIG. 7 shows a case where the input signal from the data terminal (D) in the first cycle is determined sufficiently before the rising edge of the clock signal CK.

 The worst case for the delay time Tlogic—max of the combinational logic circuit 1 13, 1 14 is that the clock signal CK rises to t = Tskewl due to skew, and the next clock falls to t = Tcycle + Tw—Tskew2 It is the case.

 At this time, the conditions under which the system operates are expressed by equation (9).

Tcq + Tlogic— max ≤ Tcycle + Tw-(Tsetup + Tskew2)-Tskewl-(9)

By transforming equation (9), equation (10) is derived.

Tcycle ≥ Tcq + Tlogic_max + Tsetup + Tskewl + Tskew2-Tw ~ (10)

Equation (10) is used when the input signal from the data terminal (D) is determined quickly. This defines the lower limit of the cycle time.

 <When the input signal from the data terminal (D) is determined slowly>

 FIG. 8 shows a case where the input signal from the data terminal (D) in the first cycle arrives during the period when the clock signal CK is "H". In this case, the conditions under which the system operates are shown in equation (11).

 Tdq + Tlogic_max ≤ Tcycle + Tw-(Tsetup + Tske 2)-[Tw — (Tsetup + Tskew2)]-(1 1)

 By transforming equation (11), equation (12) is obtained.

Tcycle ≥ Tdq + Tlogic—max to (12)

 Equation (12) defines the lower limit of the cycle time similarly to equation (10), but in practice, the larger of the right-hand side of equation (10) and the right-hand side of equation (12) Defines the lower limit of the cycle time.

 Here, attention is paid to the magnitude relation between the right side of the equation (10) and the right side of the equation (12). By subtracting the right side of equation (10) from the right side of equation (12), equation (13) is obtained.

 Tdq + Tlogic— max-(Tcq + Tlogic_max + Tsetup + Tskewl + Tske 2-T) Two Tw + Tdq One Tcq-Tsetup One Tskewl-Tskew2 .- (13)

 In general, it is not possible to determine whether equation (13) has a positive or negative value. However, when equation (13) is 0 or more, that is, when the relationship of equation (14) holds, the cycle time Is defined by equation (12).

Tw ≥ Tcq + Tsetup + Tskewl + Tskew2— Tdq-(14)

 In addition, when the expression (13) is equal to or less than 0, that is, when the relationship of the expression (15) holds, it is understood that the cycle time is defined by the expression (10). Tw Ku Tcq + Tsetup + Tskewl + Tskew2 One Tdq ~ (15)

Here, attention is again paid to equation (12). The clock on the right side of equation (12) Items related to the page (Tcq, Tsetup ヽ TskewK Tskew2) are not included. That is, in the system in which the cycle time is defined by the equation (12), the effects of the clock skew, the jitter, and the like do not appear in the minimum cycle time. From the above, it is concluded that the condition for the cycle time to be defined by Eq. (12) is that the clock pulse width Tw satisfies Eq. (14) (same as Eq. (5)). You.

 Next, the minimum delay constraint in this example will be described.

 As shown in Fig. 9, in order for data latched in the first cycle starting at time t = 0 to not be latched in the next cycle in the same cycle, The input signal from the data terminal (D) in the latch must be designed to change after the time shown in equation (16).

t = Tw + Thold + Tskew2-(16)

 Here, the following two cases are classified according to the arrival time of the input signal from the data terminal (D) in the first cycle.

 <When the input signal from the data terminal (D) is determined quickly>

 FIG. 10 shows a case where the input signal to the data terminal (D) of the latch in the first cycle is determined sufficiently before the rise of the clock signal CK.

 The worst case for the minimum delay constraint is when the clock signal C rises at t = _Tskewl due to skew, and the next clock falls at t = Tw + Tskew2. At this time, the condition for avoiding the occurrence of loss-through is expressed by equation (17).

Tcq + Tlogic—min> Tskewl + Tw + Thold + Tskew2-(17)

 By transforming this, equation (18) is obtained.

Tlogic one min> Thold + Tskewl + Tske 2 one Tcq + Tw-(18) <When input signal D is settled slowly>

 FIG. 11 shows a case where the input signal to the data terminal (D) of the latch in the first cycle arrives during the period when the clock signal CK is "H". In this case, the condition for preventing race-through from occurring is expressed by equation (19).

 TO + Tdq + Tlogic one min> Tw + Thold + Tskew2-(19)

 Here, TO represents the arrival time of the input signal D. By transforming this, equation (20) is obtained.

 Tlogic—min> Tw + Thold + Tskew2-Tdqichi TO-(20)

 Equation (20) expresses the minimum delay constraint similarly to equation (18). However, as is clear from FIGS. 10 and 11, Equation (18) has more severe conditions than Equation (20)). Therefore, it can be considered that equation (18) represents the minimum delay constraint. Now, in this example, the path shown in Fig. 3 is used as the latch circuit at the beginning of the path where the minimum delay constraint is severe, and the output terminal (QD) is used instead of the output terminal (Q) Please pay attention to that. The output terminal (Q) is the output of the latch circuit, while the output terminal (QD) is the output of the negative edge trigger flip-flop. Considering the minimum delay constraint based on Fig. 12, the conditions are as shown in Eq. (21).

 Tw + Thold + Tskew2 K Tw-TskewZ + Tcqd + Tlogic— min ~ (21)

By transforming equation (21), equation (22) is obtained.

Tlogic—min> Thold + 2Tskew2 one Tcqd-(22)

In other words, the path starting from the output terminal (QD) has strong minimum delay resistance like the conventional edge trigger system. The point here is selective for paths with strict minimum delay constraints. In this case, the output terminal (QD) is used. In the circuit of the third known example, the latch output is used even for the path where the minimum delay is severely restricted, and as a result, the circuit is weak to the minimum delay. However, since the maximum delay time and minimum delay time of a certain combinational logic circuit can be grasped at the time of design, it is considered possible to selectively switch the output terminal (Q) and output terminal (QD) based on that information. Can be By doing so, the minimum delay constraint in equation (18) can be replaced with equation (22), and the minimum delay tolerance, which is the largest concern in prior art example 3, is raised to a level that does not cause inconvenience It becomes possible.

 Next, in order to explain what criteria should be used to determine the assignment of the output terminal (Q) and output terminal (QD), the maximum delay constraint when using the output terminal (QD) is explained. think of.

 As can be understood from Fig. 13, the condition that the output path from the output terminal (QD) does not specify the minimum cycle time (that is, does not become a critical path) is expressed by equation (23).

 Tcycle + Tw> Tw + 2Tskew2 + Tcqd + Tlogic—min + Tsetup-(23)

By transforming equation (23), equation (24) is obtained.

Tlogic—min <Tcycle-2Tskew2I Tcqd-Tsetup-(24)

 Equation (22) shows the sum of this and the minimum delay constraint (22).

 Tcycle-2Tskew2-Tcqd-Tsetup> Tlogic-min> Thold + 2 Tskew2-Tcqd-(22)

 Equation (22) expresses the delay time range of the combinational logic that can be connected to the output terminal (QD).

Next, regarding the output path from the output terminal (Q), the maximum delay constraint is expressed by equation (12), and the minimum delay constraint is expressed by equation (18). From this, it can be seen that the expression (23) is the delay time range of the combinational logic.

 Tcycle-Tdq> Tlogic—max> Thold + Tskewl + Tskew2-Tcq + Tw (23)

 According to the above embodiment, the following effects can be obtained.

 (1) The delay time of the delay circuit 400 in the clock pulse generator 100 is set so that the clock pulse width Tw satisfies the expression (14) (same as the expression (5)). Has the minimum cycle time determined by Eq. (12). Since there is no term related to clock skew in equation (12), the operating frequency in this example is not affected at all by the uncertainty of the clock edge.

 (2) A signal is supplied from the output terminal (QD) of the latch circuit 102 to the combinational logic circuit 114 having a very short delay time. Doing so greatly eases the minimum delay constraint, making design easier. Whether to use the output terminal (Q) or the output terminal (QD) can be determined by using equations (22) and (23), which greatly simplifies the design. Furthermore, since it is based on a latch circuit that is faster and smaller in circuit scale than the FF circuit, it is possible to reduce the power consumption of the entire circuit.

 FIG. 14 shows another configuration example of the main part of the latch system 10, and FIG. 15 shows the operation timing of the main part in the latch system 10. As shown in FIG.

The major difference between the circuit shown in FIG. 14 and that shown in FIG. 1 is that a latch circuit 802 is interposed between the combinational logic circuits 113 and 114. And that a delay circuit 805 is interposed between the combinational logic circuit 114 and the latch circuit 103. The latch circuit 802, like the latch circuits 101 and 103, The circuit shown in Fig. 4 applies. The output signal of the combinational logic circuit 114 is delayed by the delay circuit 805 before being transmitted to the subsequent latch circuit 103.

 The pulse width Tw of the clock signal CK is set to the delay time of the delay circuit 400 in the clock pulse generator 100 so as to satisfy the equation (5), similarly to the circuit shown in FIG. You.

 Now, in this example, the same considerations as in the case shown in FIG. 1 can be made, and as a range of the propagation delay time Tlogic-max in the combinational logic circuit, Expression (23) is derived.

 Here, the propagation delay time in the combinational logic circuit 1 1 4

Assume that Tlogicjnin is smaller than the right-hand side of the equation (23). In this case, if the output signal of the combinational logic circuit 114 is directly input to the latch circuit 103, a minimum delay violation will occur, and this circuit will not operate. Therefore, by delaying the signal with the delay circuit 805, Tlogicjiin + Tdelay satisfies the equation (23). The delay amount of Tdelay may be selected within a range satisfying the expression (24). In this circuit, the operating frequency is not affected by the uncertainty of the clock edge at all. In addition, since the design is based on the latch circuit, the power consumption is lower than in the conventional example based on the FF circuit.

Tdelay> Thold + Tskewl + Tskew2-Tcq + Tw-Tlogic—min- (24) FIG. 16 shows still another example of the main configuration of the latch system 10 described above. In this configuration example, all the latch circuits are to be scanned. Also in this example, the clock signal CK has a clock pulse width satisfying the expression (5). The propagation delay time of the combinational logic circuit 113 is representative of the combinational logic circuit having the largest delay time among the combinational logic circuits included in this example. The propagation delay time of the combinational logic circuit 1 1 4 is It represents the one with the shortest delay time on the road. The scan-out terminal (S0) of the latch circuit 901 is the scan-in terminal of another latch circuit.

(S I). The SCAN_ENABLE signal is input to the control signal terminal (SE) of the latch. When the SCAN_ENABLE signal is at "L" level, the normal logic circuit operation is performed. When the SCAN_ENABLE signal is at "H" level, the logic circuit operates via the scan-in terminal (SI) and the scan-art terminal (S0) of the latch circuit. The scan operation is performed for scanning in and out of the pattern data for circuit diagnosis.

 FIG. 17 shows a configuration example of the latch circuits 901, 902, and 903.

 The latch circuits 901, 902, and 903 are not particularly limited. 18, comprising n-channel type MOS transistors 1202 and 1203, and p-channel type MOS transistors 1201 and 120. The n-channel MOS transistor 1203 and the p-channel MOS transistor 1201 are connected in parallel to form the first 3-state buffer 1221, and the n-channel MOS transistor 1202 and the p-channel MOS transistor 1201 are connected. The second tri-state buffer 1222 is configured by connecting the second tri-state buffer 1222 in parallel with 1204.

The selector 1003 selectively selects an input signal from the data terminal (D) and an input signal from the scan-in terminal (SI) based on a signal input via the control terminal (SE), and selectively outputs the signal to the first stage of the subsequent stage. It has a function of transmitting to the state buffer 122 1. To achieve such a function, two AND gates and a NOR gate for obtaining the NOR logic of their output signals -Combined with The control signal from the control terminal (SE) is directly transmitted to one of the AND gates, and the control terminal is transmitted to the other AND gate so that only one of the two AND gates is activated. The control signal from (SE) is inverted after logical inversion at 1001 and transmitted. As a result, when the control signal from the control terminal (SE) is at the "L" level, the data from the data terminal (D) is selected, and the control signal from the control terminal (SE) is at the "H" level. In this case, data from the scan terminal (SI) is selected.

The logic of the clock signal input via the clock pin (CK) is inverted at the inverter 1211 and further inverted at the latter stage 1211. The operations of the p-channel MOS transistor 1201 and the ri-channel MOS transistor 1203 are controlled by the output signal of the above-described inverter 1210. The operation of the P-channel type MOS transistor 1204 and the n-channel type MOS transistor 1202 are controlled by the output signal of the above-described member 121 1. As a result, the first tri-state buffer 1221 and the second tri-state buffer 1222 are turned on complementarily. A first latch circuit 1231 is formed by connecting the inverters 1213 and 1214 in a loop, and a second latch circuit 1232 is formed by connecting the inverters 1215 and 1216 in a loop. The data input from the data terminal (D) is input to the first latch circuit 1231 via the selector 1003 and the third state buffer 1221. The output signal from the first node N1 of the first latch circuit 1231 is output from the output terminal (Q) via the inverter 1217, and the second node N2 of the first latch circuit 1231 is output. The output signal is input to the second latch circuit 1232 via the second tri-state buffer 1222. The output signal of the second latch circuit 1232 is output to the subsequent The signal is output from the output terminal (QD) through the NOR gate 1004 and output from the scan-out terminal (SO) through the NOR gate 1004.

 In the above configuration, when the control signal SE is at "L" level, the input signal from the data terminal (D) is transmitted to the output terminal (Q) or the output terminal (QD). When the control signal SE is at "H" level, the data is transmitted to the output terminal (Q) and the output terminal (QD). When the scan-out terminal (SO) is connected to the scan-in terminal (S I) of another latch circuit and the clock signal CK transits while the control signal SE is at "H" level, it functions as a shift register. The NOR gate 1004 is designed so that the delay time from the falling edge of the clock signal CK to the output of the scan-out terminal (S0) is increased, and the race-through from the scan-gate terminal (SO) to the next-stage latch circuit is performed. Does not occur. In other words, the scan right terminal (SO) is designed so that the rightmost side of Eq. (22) has a zero or negative value. Therefore, in the configuration example shown in FIG. 17, high-speed, low-power operation and easy test by scanning are realized at the same time, and the design of the semiconductor integrated circuit is further simplified.

 Note that the selector circuit 1003 is not limited to the combination of the NAND gate and the NOR gate. A selector using a transmission gate or a tristate inverter may be used.

The CPU 1101 and its peripheral circuits in FIG. 19 can include a master-slave FF circuit in addition to the latch circuits shown in FIGS. 3, 4, and 17, respectively. Although there is no particular limitation on the master FF circuit, as shown in FIG. 18, the inverters 510 to 518, the n-channel MOS transistors 501 and 5047, and the p-channel MOS transistor 503, 517. The first tri-state buffer 521 is formed by connecting the n-channel MOS transistor 501 and the p-channel MOS transistor 503 in parallel, and the n-channel MOS transistor 504 The second tri-state buffer 522 is formed by connecting the p-channel MOS transistor 5 17 in parallel with the p-channel MOS transistor 5 17. The clock signal (CK) from the clock pulse generator 100 is supplied to the clock terminal (CK).

 In the above configuration, when the clock signal CK from the clock pulse generator 100 is at "L" level, the input data is held in the first latch section 531, and the clock signal CK becomes "H". At the time of the level, the output data of the first latch section 531 is held in the second latch section 532. Then, the held value of the second latch part 532 is output from the output terminal (Q).

 Thus, the clock signal CK supplied to the latch circuit having the configuration shown in FIGS. 3, 4, and 17 is supplied as it is to the master slave FF circuit in FIG. Therefore, there is no need to provide a separate clock pulse generator dedicated to the master slave FF circuit. The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof. Industrial applicability

 The present invention can be widely applied to various semiconductor integrated circuits.

Claims

The scope of the claims  1. A clock pulse generator that generates a pulse-like clock signal, a predetermined combinational logic circuit, and a clock signal generator that is arranged before or after the combinational logic circuit and that receives input data based on a clock signal from the clock pulse generator. And a latch circuit capable of latching  Tcq is the signal propagation delay time in the latch circuit based on the rising edge of the pulse, Tsetup is the setup time in the latch circuit, and Tsetup is the signal propagation delay time from the input terminal to the output terminal of the latch circuit. Tdq, the uncertainty at the rising edge of the clock pulse is Tskewl, and the uncertainty at the falling edge of the clock pulse is Tskew2, and the pulse width Tw of the clock pulse is T ≥ Tcq + Tsetup + Tskewl + Tskew2- Tdq A semiconductor integrated circuit characterized by satisfying the following relationship:  2. The semiconductor integrated circuit according to claim 1, wherein said clock pulse generator includes a delay circuit for determining a pulse width of said clock pulse.  3. When the minimum cycle time is Tcycle and the hold time of the latch circuit is Thold, the signal propagation delay time Tlogic in the combinational logic circuit is 3. The semiconductor integrated circuit according to claim 2, wherein a relationship of Tcycle-Tdq> Tlogic> Thold + Tskewl + Tskew2-Tcq + Tw is satisfied.  4. The semiconductor integrated circuit according to claim 3, further comprising a level sense latch circuit capable of outputting an input signal during an "H" level period of said clock pulse. 5. When the above clock pulse is "L" level, the input data is held Claims: 1. A master slave flip-flop circuit comprising: a first latch unit; and a second latch unit that holds output data of the first latch unit while the clock pulse is at "H" level. A semiconductor integrated circuit according to claim 4, wherein 6. A clock pulse generator that generates a pulse-like clock signal, a predetermined combinational logic circuit, and a clock signal generator that is arranged before or after the combinational logic circuit and that is based on a clock signal from the clock pulse generator. A latch circuit capable of latching the evening and a negative edge trigger flip-flop circuit in which the signal level input to the input terminal is transmitted to the output terminal when the output pulse changes from the high level to the output level. Including,  The signal propagation delay time in the latch circuit based on the rising edge of the clock pulse is Tcq, the setup time in the latch circuit is Tsetup, and the signal propagation delay time from the input terminal to the output terminal of the latch circuit is When Tdq, the uncertainty at the rising edge of the clock pulse is Tskewl, and the uncertainty at the falling edge of the clock pulse is Tskew2, the pulse width Tw of the clock pulse is Tw ≥ Tcq + Tsetup + Tskewl + Tskew2- Tdq Satisfy the relationship  Assuming that the minimum cycle time is Tcycle, the latch hold time is Thold, and the signal propagation delay time in the negative edge trigger flip-flop circuit with respect to the falling edge of the clock pulse is Tcqd, Propagation delay time Tlogic is Tcycle-Tdq>Tlogic> Thold + Tskewl + Tskew2 When one Tcq + Tw is satisfied, a signal is supplied to the combinational logic circuit from the output of the latch circuit, When the relationship of Tcycle-2Tskew2-Tcqd-Tsetup>Tlogic> Thold + 2 Tskew2-Tcqd is satisfied, the combinational logic circuit is characterized by being supplied with a signal from the output of the negative edge trigger flip-flop circuit. Integrated circuit. 7. The semiconductor integrated circuit according to claim 6, wherein said pulse generator includes a delay circuit for determining a pulse width of said pulse.  8. The semiconductor integrated circuit according to claim 7, wherein a signal used for a scan test is output from the negative tip trigger flip-flop circuit.  9. A semiconductor system in which a central processing unit for performing a predetermined exercise process and its peripheral circuit are combined, and at least one of the central processing unit and the peripheral circuit is provided in any one of claims 1 to 9. A semiconductor system comprising the semiconductor integrated circuit according to claim 8.