WO2004095470A1 - Nonvolatile semiconductor memory - Google Patents

Abstract

A transmission transistor for transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls a program operation for increasing the threshold voltage of the memory cell and a verify operation conducted before and after the program operation for ascertaining the threshold voltage of the memory cell. A drain switch circuit connects the gate of the transmission transistor to a first voltage line for supplying a first voltage during a verify operation and to a second voltage line for supplying a second voltage during a program operation. Since the second voltage is supplied to the transmission transistor only by the switch operation (selection operation) of the drain switch circuit, the program operation can be started in a short time after the verify operation. As a result, the time taken to write data in the memory cell is shortened.

Description

 Description Non-volatile semiconductor memory Technical field

 The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a method for generating a high voltage when writing data. Background art

 A nonvolatile semiconductor memory such as a flash memory stores a logic value of write data as a threshold voltage of a memory cell. For example, a binary memory sensor stores “logic 1” when the threshold voltage is low, and stores “logic (T) when the threshold voltage is high. In general, the operation of lowering the threshold voltage is The operation of raising the threshold voltage is referred to as "erasing" and "writing" or "programming".

 In NOR flash memory, the control gate of the memory cell is connected to a word line selected according to the address. The drain of the memory cell is connected to a bit line selected according to the address. The sources of the memory cells are connected to a common source line.

 The data write operation requires a verify operation for confirming the threshold voltage of the memory cell and a program operation for increasing the threshold voltage of the memory cell. In the belly-eye operation, for example, a high voltage (for example, 5 V) is supplied to the gate of the memory cell, and a power supply voltage (for example, 1.8 V) is supplied to the gate of the transmission transistor connected to the bit line. . A voltage lower than the power supply voltage by the threshold voltage of the transmission transistor is supplied to the drain of the memory cell via the transmission transistor. Then, the threshold voltage of the memory cell is confirmed by the current flowing through the memory cell. That is, the memory cells that need to be programmed are identified.

In a program operation, a high voltage (for example, 9 V) is supplied to the gate of the memory cell, and a high voltage (for example, 5.5 V) is supplied to the drain of the memory cell via the transfer transistor. To ensure that the drain voltage is transmitted, High voltage (for example, 9 V). Then, charges are trapped in the charge storage layer of the memory cell, and the threshold voltage increases. Thereafter, the verify operation and the program operation are repeatedly performed until the threshold voltage of each memory cell reaches a desired value.

 The above-mentioned brush memory has a plurality of boosting circuits for generating a plurality of types of high voltages. The booster circuit starts operation in response to a write command, and stops operation in response to completion of the write operation (for example, Japanese Patent Application Laid-Open No. 2002-230985).

 As described above, the write operation is performed by repeatedly performing the verify operation and the program operation. At this time, the gate voltage of the memory cell and the gate voltage of the transmission transistor must be largely changed between the verify operation and the program operation. In particular, the gate voltage of the transfer transistor must be increased from 1.8 V to 9 V when transitioning from the verify operation to the program operation. The boost time until the boost circuit generates 9 V is long, and the write cycle time is long.

 Recently, non-volatile multi-level semiconductor memories that store multiple bits of data in one memory cell have been developed. In this type of multi-valued memory cell, in order to set the threshold voltage accurately, the program operation is executed in multiple steps (step program method). In the step program method, the read margin is improved because the distribution width of the threshold voltage is reduced. That is, multi-value data can be stored in the memory cell without fail. On the other hand, in the step program method, one write operation is performed by repeating the verify operation and the program operation a plurality of times. Verify operation power ^ Since the transition to the program operation occurs multiple times during one write operation, the above-mentioned boosting time has a large effect.

 Hereinafter, prior art documents related to the present invention are listed.

 (Patent Document)

 (1) Japanese Unexamined Patent Application Publication No. 2000-230209 discloses the invention

An object of the present invention is to reduce the write operation time of a nonvolatile semiconductor memory. is there.

 In one embodiment of the nonvolatile semiconductor memory of the present invention, a transmission transistor for transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. The operation control circuit controls a program operation for increasing the threshold voltage of the memory cell, and a verify operation performed before and after the program operation to check the threshold voltage of the memory cell. The drain switching circuit connects the gate of the transmission transistor to the first voltage line to which the first voltage is supplied during the verify operation. The drain switching circuit connects a gate of the transmission transistor to a second voltage line to which a second voltage is supplied during a program operation. Since the second voltage can be supplied to the transfer transistor only by the switching operation (selection operation) of the drain switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data to the memory cells can be reduced.

 In another embodiment of the nonvolatile semiconductor memory according to the present invention, the first booster circuit starts operation during a verify operation before a program operation, and generates a second voltage on a second voltage line. Since the second voltage line can be set to the second voltage before the program operation, the second voltage can be supplied to the gate of the transmission transistor at the start of the program operation. As a result, the program operation time can be reduced.

 In another embodiment of the nonvolatile semiconductor memory of the present invention, the operation control circuit repeatedly executes the verify operation and the program operation until the threshold voltage of the memory cell reaches a desired value. The first booster circuit continues to generate the second voltage on the second voltage line during execution of the verify operation and the program operation. For this reason, the frequency of operation and stop of the first booster circuit can be reduced, and control of the operation control circuit becomes easier.

In another embodiment of the nonvolatile semiconductor memory of the present invention, the good switching circuit connects the control gate of the memory cell to the third voltage line to which the third voltage is supplied during the verify operation. The gate switching circuit is connected to a fourth voltage line to which the fourth voltage is supplied during the program operation. Since the fourth voltage can be supplied to the control gate of the memory cell only by the switching operation (selection operation) of the gate switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data to the memory cells can be reduced. In another aspect of the nonvolatile semiconductor memory of the present invention, the second booster circuit starts operation during a verify operation before a program operation, and generates a fourth voltage on a fourth voltage line. Since the fourth voltage line can be set to the fourth voltage before the program operation, the fourth voltage can be supplied to the control gate of the memory cell at the start of the program operation. As a result, the program operation time can be reduced.

 In another embodiment of the nonvolatile semiconductor memory of the present invention, the operation control circuit repeatedly executes the verify operation and the program operation until the threshold voltage of the memory cell reaches a desired value. The second booster resets the fourth voltage line to the initial voltage every time the program operation is completed. In other words, the second booster circuit generates the fourth voltage based on the initial voltage for each verify operation. For this reason, the fourth voltage can be accurately set for each program, and the threshold voltage of the memory cell can be accurately set to a desired value.

 In another aspect of the non-volatile semiconductor memory of the present invention, the operation control circuit sets the fourth voltage generated by the second booster circuit to be sequentially higher for each repeatedly executed program operation. That is, the nonvolatile semiconductor memory has a so-called step program function. Since the program voltage (fourth voltage) required for each step can be accurately generated, the threshold voltages of a plurality of memory cells can be distributed in a desired region. As a result, the write operation time can be reduced without reducing the read margin.

In another embodiment of the nonvolatile semiconductor memory of the present invention, the third booster circuit generates the fifth voltage during the verify operation and generates the sixth voltage during the program operation. The output node of the third booster circuit is connected to the drain of the transfer transistor. The gate switching circuit selects the fifth voltage as the third voltage during the verify operation. That is, the fifth voltage generated by the third booster circuit during the verify operation can be shared by the drain voltage of the transfer transistor and the control gate voltage of the memory cell. Generally, the voltage supplied to the control gate of the memory cell during the verify operation (the fifth voltage) is close to the voltage supplied to the drain of the transfer transistor during the program operation (the sixth voltage). For this reason, the third booster circuit can change the generated voltage from the fifth voltage to the sixth voltage in a short time at the transition from the verify operation to the program operation. As a result, a program operation can be started in a short time after a verify operation, and data can be written to a memory cell. Time can be reduced. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram showing a first embodiment of the nonvolatile semiconductor memory of the present invention.

 FIG. 2 is a circuit diagram showing details of the booster circuit VDPP shown in FIG.

 FIG. 3 is a circuit diagram showing details of the booster circuit VPPP shown in FIG.

 FIG. 4 is a circuit diagram showing details of the booster circuit VPPIP shown in FIG.

 FIG. 5 is a circuit diagram showing details of the multiplexer XMUX and the row decoder XDEC shown in FIG.

 FIG. 6 is a circuit diagram showing details of the multiplexer YUX and the column decoder YDEC shown in FIG.

 FIG. 7 is a waveform diagram showing a write operation of the flash memory of the present invention. FIG. 8 is a waveform diagram showing a write operation of the flash memory before the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. A part of the block to which the bold line is connected is composed of a plurality of circuits. Use the same sign as the signal name for the signal line through which the signal (voltage) is transmitted.

 FIG. 1 shows an embodiment of the nonvolatile semiconductor memory of the present invention. This nonvolatile semiconductor memory is formed as a NOR flash memory chip on a silicon substrate using a CMOS process.

 The flash memory has an operation control circuit 0P (:, a booster circuit VPPP, VPDP, VPPIP, a multiplexer XUX, a YMUX, a row decoder XDEC, a column decoder YDEC, and a memory sensor array ARY.

The operation control circuit 0PC outputs a timing signal and a control signal to a main circuit in response to a command signal CMD (a chip enable signal / CE, a write enable signal / WE, etc.) supplied from the outside. The booster circuit VPPP (second booster circuit) operates in synchronization with the timing signal from the operation control circuit 0PC, and generates a high voltage VPP (fourth voltage) on the high voltage line VPP (fourth voltage line). The booster circuit VPDP (third booster circuit) operates in synchronization with the timing signal from the operation control circuit 0PC, and generates a high voltage VPD (fifth or sixth voltage) according to the control signals VSEL and PSEL. Generate on line VPD (third voltage line). The booster circuit VPPIP (first booster circuit) operates in synchronization with the timing signal from the operation control circuit 0PC, and generates a high voltage VPPI (second voltage) on the high voltage line VPPI (second voltage line).

 The multiplexer XMUX (gate switching circuit) outputs one of the high voltage VPP or the high voltage VPD as the gate voltage VG to the gate decoder XDEC according to the control signal SEL3 from the operation control circuit 0PC. The multiplexer YMUX (drain switching circuit) switches the power supply voltage VCC (first voltage) or the high voltage VPPI supplied to the power supply line VCC (first voltage line) according to the control signal SEL4 from the operation control circuit 0PC. One is output to the gate of the transmission transistor TT in the column decoder YDEC.

 The row decoder XDEC has a circuit for supplying a gate voltage VG to a read line WL selected by a decode signal of an address signal XADD supplied from outside the flash memory. The column decoder YDEC has a transmission transistor TT for supplying a drain voltage VD to a bit line BL selected by a decode signal of an address signal YADD supplied from outside the flash memory.

 The memory cell array ARY includes a plurality of memory cells MC arranged in a matrix, a word line WL connected to a control gate G of the memory cells arranged in the horizontal direction in the figure, and a drain D of the memory cells arranged in the vertical direction in the figure. And a source line connected to the source S of the memory cell. The memory cell MC is composed of a transistor (cell transistor) having a trap gate for storing charges. The trap gate is formed of an insulating film such as a nitride film. Therefore, the charges trapped in the trap gate do not move in the trap gate. Using this, the threshold voltage of the cell transistor can be changed locally. In this embodiment, the memory cell MC operates as an electrically rewritable binary memory cell by putting charge into and out of only one location of the trap gate.

FIG. 2 shows details of the booster circuit VPDP shown in FIG. In the figure, diagonal lines The transistor with the mark is a pMOS transistor, and the transistor without hatching is an nMOS transistor. The capacitance is formed by connecting the source and drain of the nMOS transistor to each other.

 The booster circuit VPDP has a pump unit PUMP for generating a boosted voltage and an adjusting unit ADJ for setting the high voltage VPD to a predetermined voltage. The pump unit PUMP boosts the power supply voltage VCC (1.8 V) by pumping the pump node PND, which is clamped to a predetermined positive voltage by the clamp circuit, with the clock signal CLK1 through the capacitor C1, and charges the boosted charge. Transfer to boost node BND. The clock signal CLK1 is generated by the oscillator inside the booster circuit VPDP according to the control signal from the operation control circuit 0PC.

 The adjustment unit ADJ compares the comparison voltage DIV obtained by dividing the high voltage VPD with the reference voltage VREF, controls the gate of the discharge transistor DCT according to the comparison result, and sets the high voltage VPD to a predetermined voltage. The reference voltage VREF is generated by a reference voltage generation circuit formed in the flash memory. The reference voltage VREF is common to the boost circuits VPDP, VPPP, and VPPIP. The adjustment unit ADJ connects the capacitor C2 to the node DIV when the control signal VSEL is at a high level, and connects the capacitor C1 to the node DIV when the control signal PSEL is at a high level. The capacitance value of the capacitance C1 is larger than the capacitance value of the capacitance C2. The operation control circuit 0PC shown in Fig. 1 sets the control signals VSEL and PSEL to high level and low level respectively during the verify operation, and sets the control signals VSEL and PSEL to low level and high level respectively during the program operation. Set. Node DIV is set to a voltage according to the capacitance division of the two capacitors connected between high node VPD and ground line VSS. The high-voltage VPD is boosted to 5 V (fifth voltage) and 5.5 V (sixth voltage) using the power supply voltage VCC (1.8 V) during the verify operation and the program operation, respectively. . The difference between the high voltage VPD for the verify operation and the program operation is 0.5 V. Therefore, the high-voltage VPD can be set quickly when transitioning from the verify operation to the program operation.

 FIG. 3 shows details of the booster circuit VPPP shown in FIG.

The booster circuit VPPP has the capacity to set the voltage of the node DIV in multiple ways. The connection between these capacitors and the node DIV is controlled by control signals PSEL1, PSEL2,..., PSELn, respectively. Control signals PSEL1, PSEL2, PSELn is output from the operation control circuit OPC. During the write operation, the booster circuit VPPP raises the high voltage VPP to 9 V, 9.1 V ヽ 9.2 V,... In accordance with the control signals PSEL1, PSEL2,.

 FIG. 4 shows details of the booster circuit VPPIP shown in FIG.

 In the booster circuit VPPIP, only two capacitors are connected in series via the node DIV. The other logical configuration is the same as the booster circuit VPDP shown in Fig. 2. Therefore, there is only one type of high voltage VPPIP generated when the booster circuit VPPIP operates. Specifically, when the booster circuit VPPIP operates, the high voltage VPPI rises from 1.8 V (= VCC) to 9 V.

 FIG. 5 shows details of the multiplexer XMUX and the row decoder XDEC shown in FIG. '

 When the control signal SEL3 is at a low level (verify operation), the multiplexer MUX turns on the transistor PM12 and outputs the high voltage VPD (third voltage) as the gate voltage VG. When the control signal SEL3 is at a high level (program operation), the multiplexer UX turns on the transistor PM10 and outputs the high voltage VPP (fourth voltage) as the gate voltage VG.

 The output decoder XDEC outputs the gate voltage VG to the lead line WL when the decode signal D (negative logic) of the address signal XADD is at a low level, and outputs the ground voltage to the lead line WL when the decode signal XD is at a high level. Output. That is, the gate voltage VG is supplied to the lead line WL selected by the address signal XADD.

 FIG. 6 shows details of the multiplexer YMUX and the column decoder YDEC shown in FIG.

 When the control signal SEL4 is at a low level (verify operation), the multiplexer YMUX turns on the transistor PM20 and outputs the power supply voltage VCC (first voltage) as the drain voltage VD. When the control signal SEL4 is at a high level (program operation), the multiplexer YMUX turns on the transistor PM22 and outputs the high voltage VPPI (second voltage) as the drain voltage VD.

The column decoder TOEC has a transmission transistor TT for transmitting the high voltage VPD to the bit line BL. The transmission transistor TT is used to decode the address signal YADD. Turns on when signal YD (positive logic) is high, transmitting high voltage VPD to bit line BL (drain of memory cell MC). That is, the high voltage VPD is supplied to the bit line BL selected by the address signal YADD. The transmission transistor TT is turned off when the decode signal YD is at a low level, and the bit line BL floats. In practice, the voltage transmitted to the bit line BL is the maximum value obtained by subtracting the threshold voltage of the transmission transistor TT from the gate voltage of the transmission transistor TT.

 FIG. 7 shows a write operation of the flash memory of the present invention.

 Here, the write operation is an operation of programming “logic (T) to the memory cell MC. In the present embodiment, the write operation is performed by repeating the verify operation and the program operation, and gradually increasing the threshold voltage of the memory cell MC. A step program method is used, which raises the value and sets it to the expected value.

 First, in the first verify period VRF, a verify operation is performed to check the threshold voltage of the memory cell MC. In the verify operation, the booster circuit VPDP generates 5 V at the node VPD (Fig. 7 (a)). The manoplexer X 丽 selects the node VPD for the verification period VRF. Therefore, the row decoder XDEC selected according to the address signal XADD changes the corresponding word line WL to 5V. Then, the gate voltage GATE of the memory cell MC is set to 5 V (FIG. 7 (b)).

 The multiplexer YMUX outputs the power supply voltage VCC (1.8 V) to the node VD during the verify period VRF (FIG. 7 (c)). The column decoder YDEC selected according to the address signal YADD sets the gate of the transmission transistor TT to the power supply voltage VCC. For this reason, the drain voltage DRAIN (bit line BL) of the memory cell MC is set to a value obtained by subtracting the threshold voltage of the transfer transistor from the power supply voltage VCC (FIG. 7 (d)). Then, the memory cell MC to be programmed is determined according to the current flowing through the memory cell MC.

During the verify period VRF, the booster circuits VPPIP and VPPP start operation and generate high voltages VPPI and VPP, respectively (Fig. 7 (e, f)). By starting the generation of the high voltages VPPI and VPP required for the program operation in advance during the verify operation before the program operation, the program operation can be started quickly. After the verify operation, a program operation is performed on the memory cell MC to which data needs to be written. During the program period PRG during which the program operation is performed, the boost circuits VPPIP and VPPP have already generated the boost voltages VPPI and VPP, respectively (Fig. 7 (g, h)). The multiplexer MUX stops selecting the boosted voltage VPD according to the control signal SEL ³ and starts selecting the boosted voltage VPP. Then, the boost voltage VPP (9 V) is output to the node VG. The row decoder XDEC selected according to the address signal XADD changes the corresponding word line WL to the boost voltage VPP. Then, the gate voltage GATE of the memory cell MC is set to 9 V (FIG. 7 (i)).

 The boost circuit VPDP changes the boost voltage VPD from 5 V to 5.5 V according to the control signals VSEL and PSEL (Fig. 7 (j)). The multiplexer YMUX stops selecting the power supply voltage VCC according to the control signal SEL4 and starts selecting the boosted voltage VPPI. Then, the boost voltage VPPI (9 V) is output to the node VD (Fig. 7 (k)). The column decoder YDEC selected according to the address signal YADD sets the gate of the transmission transistor TT to the boost voltage VPPI. Therefore, the drain voltage DRAIN (bit line BL) of the memory cell MC is set to the boost voltage VPD (5.5 V) (FIG. 7 (1)). Then, the program operation for increasing the threshold voltage is performed on the memory cell MC selected by the read line WL and the bit line BL.

 In the program period PRG, the boost voltages VPP and VPPI are generated in advance in the verify period VRF. Also, the voltage required for the booster circuit VPDP to be newly boosted is about 0.5 V, and the boosted voltage VPD rises to 5.5 V in a short time. Therefore, the period T1 required for setting the gate voltage GATE and the drain voltage DRAIN depends only on the switching period of the multiplexers XMUX and YMUX. In other words, the period required to generate the boost voltages VPP and VPPI is not included in the program period PRG. Therefore, the program period PRG is shortened, and the write operation time is shortened.

Next, after the discharge period DSC, the verify operation for confirming the threshold voltage of the memory cell MC is performed again. In the verify operation, when it is determined that the threshold voltage of the memory cell MC to be programmed is low, the program operation (not shown) is executed again (step program method). In the discharge period DSC, the boosted voltages VPD and VPP are reset to the power supply voltage VCC. The boost voltage VPPI is Maintains 9 V without being reset. Gate voltage GATE and drain voltage DRAIN are set to ground voltage VSS.

 By resetting the boost voltage VPP to the power supply voltage VCC, it is possible to accurately generate the gate voltage GATE that needs to be increased by 0.1 V every program operation. In addition, since the boost voltage VPPI is maintained at 9 V, the boost circuit VPPIP does not need to operate and stop repeatedly during one write operation. Therefore, control of the operation control circuit 0PC becomes easy.

 FIG. 8 shows a write operation of the flash memory before the present invention.

 In the step-program type flash memory before this explanation, the generation of boosted voltages VPPI, VPD, and VPP is started in response to the start of the program operation. Therefore, in the program period PRG, the period T1 required for setting the gate voltage GATE and the drain voltage DRAIN depends on the period during which the booster circuit generates the boosted voltages VPPI, VPD, and VPP. Therefore, the period T1 is longer than that in FIG. 7 described above, and the program period PRG is longer. In particular, in the step program method, since the period T1 exists a plurality of times, the influence on the write operation time is large.

 As described above, in the present embodiment, in the data write operation, the booster circuit VPPIP starts generating the boosted voltage VPPI in the verify period VRF before the program period PRG. Therefore, the multiplexer YMUX can supply the boosted VPPI to the gate of the transfer transistor TT during the program period PRG only by performing the switching operation according to the control signal SEL4. Therefore, the program operation can be started immediately after the verify operation. As a result, the time for writing data to the memory cell MC can be reduced.

 Similarly, in the data write operation, the booster circuit VPPP starts generating the boosted voltage VPP in the verify-eye period VRF before the program period PRG. Therefore, the multiplexer XMUX can supply the boost voltage VPP to the control gate of the memory cell MC and the program period PRG simply by performing the switching operation in accordance with the control signal SEL3. Therefore, the program operation can be started immediately after the verify operation. As a result, the time for writing data to the memory cell MC can be reduced.

In a flash memory using the step programming method, the booster circuit VPPIP keeps generating the boosted voltage VPPI during the write operation. Therefore, the boost Road The frequency of VPPIP operation and stop can be reduced, and the operation control circuit 0PC can be easily controlled.

 The operation control circuit 0PC sequentially sets the boosted voltage VPP generated by the booster circuit VPPP higher by 0.1V for each repeatedly executed program operation. The booster circuit VPPP resets the boosted voltage VPP to the power supply voltage VCC each time the program operation is completed. For this reason, by generating the boost voltage VPP for each program based on the power supply voltage VCC, the boost voltage VPP (program voltage) required for each step can be set accurately, and the threshold voltage of the memory cell MC is set to a desired value. Can be set exactly to the value of.

 The booster circuit VPDP generates a 5 V boost voltage VPD to supply to the control gate of the memory cell MC during the verify period VRF, and generates a 5.5 V boost voltage VPD to supply to the drain of the memory cell MC during the program period PRG. Generates boost voltage VPD. By using the booster circuit VPDP for both the gate voltage GATE and the drain voltage DRAIN of the memory cell MC, the booster voltage used for the verify operation and program operation can be efficiently generated.

 The difference between the gate voltage GATE used for the verify operation and the drain voltage DRAIN used for the program operation is close to 0.5 V. For this reason, the booster circuit VPDP can change the boosted voltage VPD from 5 V to 5.5 V in a short time when shifting from verify-eye operation to program operation. As a result, the program operation can be started in a short time after the verify operation, and the time for writing data to the memory cells can be reduced.

 In the above-described embodiment, an example has been described in which the present invention is applied to a flash memory chip. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a flash memory core mounted on a system LSI. In the above-described embodiment, an example has been described in which the present invention is applied to a flash memory having a binary memory cell. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a flash memory having multi-level memory cells. In the above-described embodiment, an example in which the present invention is applied to a NOR flash memory has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a flash memory of a NAD type or a virtual ground type.

In the above-described embodiment, the present invention is applied to the writing of a memory cell having The example applied to only the operation is described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a write operation of a memory cell having a floating gate.

 As described above, the present invention has been described in detail. However, the above-described embodiment and its modifications are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the present invention. Industrial potential

 In the nonvolatile semiconductor memory of the present invention, since the second voltage can be supplied to the transmission transistor only by the switching operation (selection operation) of the drain switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data to the memory cells can be reduced.

 In the nonvolatile semiconductor memory of the present invention, since the second voltage line can be set to the second voltage before the program operation, the second voltage can be supplied to the gate of the transfer transistor at the start of the program operation. As a result, the program operation time can be reduced. In the nonvolatile semiconductor memory of the present invention, the frequency of the operation and stop of the first booster circuit can be reduced, and the control of the operation control circuit is facilitated.

 In the nonvolatile semiconductor memory of the present invention, since the fourth voltage can be supplied to the control gate of the memory cell only by the switching operation (selection operation) of the gate switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data to the memory cells can be reduced.

 In the nonvolatile semiconductor memory of the present invention, since the fourth voltage line can be set to the fourth voltage before the program operation, the fourth voltage can be supplied to the control gate of the memory cell at the start of the program operation. As a result, the program operation time can be reduced. In the nonvolatile semiconductor memory of the present invention, the fourth voltage can be accurately set for each program, and the threshold voltage of the memory cell can be accurately set to a desired value.

In the nonvolatile semiconductor memory of the present invention, the threshold voltages of a plurality of memory cells can be distributed in a desired area. As a result, the write operation time can be reduced without reducing the read margin. In the nonvolatile semiconductor memory according to the present invention, the third booster circuit can change the generated voltage from the fifth voltage to the sixth voltage in a short time when shifting from the verify operation to the program operation. As a result, the program operation can be started in a short time after the verify operation, and the time for writing data to the memory cell can be reduced.

Claims

The scope of the claims (1) an electrically rewritable nonvolatile memory cell having a control gate, a drain, and a source;  A transmission transistor having a source connected to the drain for transmitting a drain voltage to the drain of the memory cell;  An operation control circuit for controlling a program operation for increasing the threshold voltage of the memory cell, and a verify operation performed before and after the program operation to check the threshold voltage of the memory cell;  A drain connected to a first voltage line to which a first voltage is supplied during the verify operation, and a drain connected to a second voltage line to which a second voltage is supplied during the program operation; A nonvolatile semiconductor memory comprising a switching circuit.  (2) In the nonvolatile semiconductor memory according to claim 1,  A non-volatile semiconductor memory, comprising: a first booster circuit that starts an operation during the verify operation before the program operation and generates the second voltage on the second voltage line.  (3) In the nonvolatile semiconductor memory according to claim 2,  The operation control circuit repeatedly executes the above-described program operation until the threshold voltage of the memory cell reaches a desired value,  The non-volatile semiconductor memory according to claim 1, wherein the first boosting circuit continues to generate the second voltage on the second voltage line during execution of the verify program operation.  (4) In the nonvolatile semiconductor memory according to claim 1,  The control gate of the memory cell is connected to a third voltage line to which a third voltage is supplied during the verify operation, and a fourth voltage is supplied to the memory cell during the program operation. A nonvolatile semiconductor memory including a gate switching circuit connected to a voltage line.  (5) In the nonvolatile semiconductor memory according to claim 4, Start operation during the verify operation before the program operation; and A nonvolatile semiconductor memory comprising a second booster circuit for generating the fourth voltage on a line.  (6) In the nonvolatile semiconductor memory according to claim 4,  The operation control circuit repeatedly executes the verify program operation until the threshold voltage of the memory cell reaches a desired value,  The nonvolatile semiconductor memory according to claim 2, wherein the second booster circuit resets the fourth voltage line to an initial voltage every time the program operation is completed.  (7) In the nonvolatile semiconductor memory according to claim 6,  The non-volatile semiconductor memory, wherein the operation control circuit sequentially sets the fourth voltage generated by the second booster circuit to be higher each time the program operation is repeatedly executed.  (8) In the nonvolatile semiconductor memory according to claim 4,  A third booster circuit that generates a fifth voltage during the verify operation, generates a sixth voltage during the program operation, and has an output node connected to a drain of the transfer transistor;  The non-volatile semiconductor memory, wherein the gate switching circuit selects the fifth voltage as the third voltage during the verify operation.