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WO2004086240A1 - Systeme de traitement de donnees avec une unite de commande d'acces direct en memoire pour stocker le descripteur du canal actif - Google Patents

Systeme de traitement de donnees avec une unite de commande d'acces direct en memoire pour stocker le descripteur du canal actif Download PDF

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Publication number
WO2004086240A1
WO2004086240A1 PCT/IB2004/050326 IB2004050326W WO2004086240A1 WO 2004086240 A1 WO2004086240 A1 WO 2004086240A1 IB 2004050326 W IB2004050326 W IB 2004050326W WO 2004086240 A1 WO2004086240 A1 WO 2004086240A1
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WO
WIPO (PCT)
Prior art keywords
dma
memory
descriptor
ddp
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2004/050326
Other languages
English (en)
Inventor
Sanjeev M. Sreedharan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of WO2004086240A1 publication Critical patent/WO2004086240A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the invention relates to a data processing system.
  • the invention further relates to a method for transmitting data.
  • USB Universal Serial Bus
  • Figure 1 schematically shows an arrangement comprising a host controller USBH, a system on chip SOC coupled via a USB cable USBC to the host device and
  • the system on chip comprises a USB device function
  • USBDC USB DC
  • memory controller MC which are mutually coupled to an internal bus, for example a AHB bus as shown.
  • Other devices may be coupled to the internal bus as well.
  • the USB device function includes a DMA controller.
  • the host establishes a transfer pipe to the endpoints.
  • the host will send data to or receive data from endpoints implemented inside the device through the USB cable USBC.
  • endpoints EP1 and EP3 will receive data from the Host. They are referred as OUT endpoint.
  • EP2 and EP4 are capable of sending the data towards the host and are referred as IN endpoints.
  • the data transfer is done in packets whose format is defined in the USB protocol.
  • endpoint will have a buffer, which is capable of holding at least one packet of data corresponding to the endpoint.
  • Each endpoint will have an assigned space in the system memory MEM, which will act as the destination or source for the data packet.
  • the logical view of the data transfer from the endpoint to the memory is shown by the dotted lines. Physical data transfer happens through the AHB bus and memory controller MC.
  • An OUT endpoint should transfer the packet data it received from the host USBH to the system memory. MEM before the next packet arrives. From there it may be transferred to another destination if desired. Similarly an IN endpoint should retrieve one packet of data from the system memory MEM before the request for the data from the host arrives.
  • Data can be transferred from the endpoint buffer to the system memory MEM through the processor of the SOC or Direct Memory Access (DMA).
  • DMA Direct Memory Access
  • the Endpoints directly transfer the data to or from the memory through the DMA Controller implemented inside the USB Device core.
  • Figure 2 illustrates a conventional implementation of a DMA Controller.
  • DMA Controller comprises a DMA control logic DMAC, and a set of registers DMAREGS comprising information used by the DMA controller.
  • the sets of registers are indicated as EP1_DMAREGS for Endpoint 1; EP2_DMAREGS for endpoint 2 and so on.
  • the following information is comprised in the registers: The start address of the DMA buffer in the system memory MEM, (EP1_B,
  • the length of the DMA Buffer in the system memory MEM Control information, such as the DMA-mode used and the maximum packet length, DMA count information (Number of bytes transferred) DMA status information
  • a DMA transfer can be characterised by a structure describing these parameters. To support continuous transfer of data on an endpoint the DMA controller should keep the above information for the current and next buffers.
  • the set of DMA registers for each endpoint will comprise:
  • DMA Start Address register current (32 bit wide)
  • DMA Start Address register next (32 bit wide)
  • DMA length Register current (16 bit wide)
  • DMA length Register next (16 bit wide)
  • a major drawback of this conventional implementation is that the number of registers required inside the DMA controller increases proportionally with the number of * endpoints. This will cause a corresponding increase in gate count (silicon area). This is schematically illustrated in Figure 3. As shown therein the gate count is about 12K for a single endpoint and increases with about 0.8K for each succeeding end-point.
  • a data processing system according to the invention is described by claim 1.
  • a method according to the invention is described by claim 2.
  • the proposed architecture uses a single physical resource to serve multiple endpoints in a time division multiplexed basis.
  • the DMA controller uses the system memoiy itself to keep the information for the DMA transfers. DMA_REGS will not be implemented inside the DMA controller.
  • the required number of gates is relatively low and independent of the allowable number of end -points.
  • it has a set of place-holder registers for keeping the status of a running DMA operation.
  • the information need to conduct a DMA transfer will be distributed inside the memory as DMA descriptors (DD).
  • DD DMA descriptors
  • Software create the DD and distribute it in the memory.
  • the place-holder registers will be filled with the contents of DD when the DMA transfer is required.
  • Figure 1 shows a conventional data processing device
  • Figure 2 shows a conventional DMA controller
  • Figure 3 shows the relation between the required number of gates and the number of end -points in the conventional DMA controller
  • Figure 4 shows a data processing device according to the invention
  • Figure 5 shows a method for transmitting data according to the invention
  • Figure 6 shows the relation between the required number of gates and the number of end -points in the DMA controller of the data processing device according to the invention.
  • FIG. 4 schematically shows a data processing system according to the invention.
  • the data processing system comprises a USB interface USBDC for communicating with a USB host device USBH.
  • the USB host is for example a PC
  • the data processing system is for example a mobile consumer product, such as a portable digital assistant PDAs, mobile phone, a digital camera, or a portable storage device.
  • the data processing system further comprises a DMA controller DMAC for enabling direct access to a memory MEM and a storage facility MEM for storing control information DD-EPO, DD-EP31 relating to the DMA transmission.
  • the control information includes at least information indicative for the location of a buffer space dma_buffer_start_addr to be used by one or more DMA transmissions.
  • the data processing system is characterized in that the control information is stored in a memory (MEM).
  • the memory further comprises reference information (DDP-EPO, ..., DDP-EP31) indicating the location of the control information.
  • the DMA controller has a single set of registers (TDREG) for storing a copy of the control information related to the active DMA stream.
  • the control information information DD-EPO, DD-EP31 is stored in a memory area called USB Device Communication Area (UDCA) of the memory MEM, in which the DMA controller and the USB controller further store the device driver software.
  • UDCA USB Device Communication Area
  • Each endpoint is assigned a reserved location in this area which holds a pointer (DDP) to the location where the data descriptor DD for that endpoint is kept.
  • DDP pointer
  • the start address of the UDCA area is defined in the location UDCA_Head defined in the DMA Controller.
  • the location for the DDP are derived from the endpoint number and the UDCA head register value. In practice the location is derived by adding the endpoint number multiplied by 4 to the UDCA head register value, when using word aligned addresses.
  • a DMA descriptor DD represents one DMA transfer unit for the endpoint.
  • the DD When the buffer indicated by the DD is full the DD will be moved to the retired status.
  • DMA descriptors for an endpoint form a linked list, i.e. one DD points to the next DD to be serviced.
  • the DMA controller is capable of fetching the next DD. Consequently the DMA transfer can go on for an indefinite period of time.
  • a DMA transfer can be characterised by a structure describing the parameters controlling the DMA . This structure is called the DMA Descriptor.
  • the DD is a structure consisting of 4 words (16 bytes). The fields are defined as below.
  • the descriptor belongs to an isochronous endpoint. max_packet_size
  • the DMA controller will stop using this descriptor when this limit is reached and will look for the next descriptor dma_buffer_start_addr
  • DD_status The address from where the data has to be picked up or to be stored. This field is updated packet- wise by DMA controller. DD retired This bit is set when the DMA controller finishes the current Descriptor. This will happen when the end of the buffer is reached or a short packet is transferred (no isochronous endpoints) or an error condition is detected. DD_status
  • the status of the DMA transfer is encoded in this field. packet valid
  • This bit indicates that the last packet transferred to the memory is received with errors or not present dma count
  • the number of bytes transferred by the DMA controller at any point of time is updated packet-wise by the DMA controller when it updates the descriptor.
  • a method for transmitting data according to the invention is illustrated with reference to Figure 5.
  • the DMA controller fetches a DMA descriptor pointer DD corresponding to an end-point in step a.
  • the DMA descriptor is fetched from the location pointed to by the
  • step c it is checked whether the DMA descriptor is in a retired state. Subsequently in step d the DMA descriptor is copied in a set of registers TDREG, provided that the DMA descriptor is not in Retired state. If DD is in a retired state DDP is updated in step e by the 'next_dd_pointer' in the currently fetched DD. Then steps b and c are repeated.
  • step f a packet transfer is executed using the data copied into the set of registers TDREG,
  • step g the copied DMA descriptor is updated to take into account the changes in the status of the transfer for the selected endpoint,
  • step h the updated DMA descriptor is written back to the memory location from where it was read.
  • the host will send the packets in a multiplexed fashion to the device.
  • the first packet may belong to endpoint EP2 the second one from endpoint EP4 etc.
  • the serviced endpoint changes from packet to packet.
  • a case may occur, where a plurality of packets originate from the same endpoint, e.g. EP2.
  • the flag is reset when the endpoint is different or DD is retired.
  • Figure 6 schematically illustrates that the data processing system and the method for transferring data according to the invention allow an arbitrary number of end points using an architecture having a relatively low number of gates, the number being independent of the number of end-points.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

Le système décrit de traitement de données comprend une fonction de dispositif USB (USBDC) pour communiquer avec un hôte de commande USB (USBH), une unité de commande d'accès direct en mémoire (DMAC) pour donner un accès direct à une mémoire (MEM) et des moyens de stockage (MEM) pour stocker des données et des informations de commande (DD-EP0,..., DD-EP31) relatives à la transmission d'accès direct en mémoire. Les informations de commande comprennent des informations indicatives de la localisation d'une zone tampon (dma_buffer_start_addr) à utiliser avec une ou plusieurs transmissions d'accès direct en mémoire. Selon l'invention, les informations de commande sont stockées dans une mémoire (MEM) qui contient en outre des informations de contrôle (DDP-EP0, , DDP-EP31) qui indiquent la localisation des informations de commande.
PCT/IB2004/050326 2003-03-28 2004-03-24 Systeme de traitement de donnees avec une unite de commande d'acces direct en memoire pour stocker le descripteur du canal actif Ceased WO2004086240A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100820 2003-03-28
EP03100820.4 2003-03-28

Publications (1)

Publication Number Publication Date
WO2004086240A1 true WO2004086240A1 (fr) 2004-10-07

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PCT/IB2004/050326 Ceased WO2004086240A1 (fr) 2003-03-28 2004-03-24 Systeme de traitement de donnees avec une unite de commande d'acces direct en memoire pour stocker le descripteur du canal actif

Country Status (1)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007003985A1 (fr) * 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Dispositif et procede pour la commande d'une pluralite de taches d'acces direct en memoire
WO2007054763A1 (fr) * 2005-11-09 2007-05-18 Nokia Corporation Dispositif, procede et projiciel permettant de serialiser des donnees au moyen d'un controleur a acces memoire direct
US8001430B2 (en) 2005-06-30 2011-08-16 Freescale Semiconductor, Inc. Device and method for controlling an execution of a DMA task
US8572296B2 (en) 2005-06-30 2013-10-29 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
CN116244232A (zh) * 2023-02-02 2023-06-09 北京奕斯伟计算技术股份有限公司 Dma装置和数据传输方法
CN120179588A (zh) * 2025-05-22 2025-06-20 山东云海国创云计算装备产业创新中心有限公司 一种直接内存访问控制方法、系统、电子设备及存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828903A (en) * 1994-09-30 1998-10-27 Intel Corporation System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
US6182165B1 (en) * 1998-06-01 2001-01-30 Advanced Micro Devices, Inc. Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system
US6266715B1 (en) * 1998-06-01 2001-07-24 Advanced Micro Devices, Inc. Universal serial bus controller with a direct memory access mode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828903A (en) * 1994-09-30 1998-10-27 Intel Corporation System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
US6182165B1 (en) * 1998-06-01 2001-01-30 Advanced Micro Devices, Inc. Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system
US6266715B1 (en) * 1998-06-01 2001-07-24 Advanced Micro Devices, Inc. Universal serial bus controller with a direct memory access mode

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"USB UNIVERSAL SERIAL BUS SPECIFICATION VERSION 1.0", UNIVERSAL SERIAL BUS (USB), XX, XX, 15 January 1996 (1996-01-15), pages 1 - 268, XP002917782 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007003985A1 (fr) * 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Dispositif et procede pour la commande d'une pluralite de taches d'acces direct en memoire
US7930444B2 (en) 2005-06-30 2011-04-19 Freescale Semiconductor, Inc. Device and method for controlling multiple DMA tasks
US8001430B2 (en) 2005-06-30 2011-08-16 Freescale Semiconductor, Inc. Device and method for controlling an execution of a DMA task
US8572296B2 (en) 2005-06-30 2013-10-29 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
WO2007054763A1 (fr) * 2005-11-09 2007-05-18 Nokia Corporation Dispositif, procede et projiciel permettant de serialiser des donnees au moyen d'un controleur a acces memoire direct
JP2009515269A (ja) * 2005-11-09 2009-04-09 ノキア コーポレイション 直接メモリ・アクセスコントローラによるデータの直列化をもたらす装置、方法およびコンピュータ・プログラム
CN116244232A (zh) * 2023-02-02 2023-06-09 北京奕斯伟计算技术股份有限公司 Dma装置和数据传输方法
CN120179588A (zh) * 2025-05-22 2025-06-20 山东云海国创云计算装备产业创新中心有限公司 一种直接内存访问控制方法、系统、电子设备及存储介质

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