WO2004077561A1 - 電極層および誘電体層を含む積層体ユニット - Google Patents
電極層および誘電体層を含む積層体ユニット Download PDFInfo
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- WO2004077561A1 WO2004077561A1 PCT/JP2004/001829 JP2004001829W WO2004077561A1 WO 2004077561 A1 WO2004077561 A1 WO 2004077561A1 JP 2004001829 W JP2004001829 W JP 2004001829W WO 2004077561 A1 WO2004077561 A1 WO 2004077561A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
- H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
- H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
- H10D1/688—Capacitors having no potential barriers having dielectrics comprising perovskite structures comprising barrier layers to prevent diffusion of hydrogen or oxygen
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
- H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
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- H10W20/496—
Definitions
- the present invention relates to a laminate unit including an electrode layer and a dielectric layer, and more particularly, to a semiconductor unit together with other devices such as a field effect transistor (FET) and a CPU (Central Processing Unit).
- FET field effect transistor
- CPU Central Processing Unit
- the present invention relates to a laminated unit including an electrode layer and a dielectric layer, which is capable of forming a small-sized or large-capacity thin-film capacitor having excellent dielectric characteristics, which is suitable for being incorporated into a body wafer.
- FET field effect transistor
- CPU Central Processing Unit
- Bismuth layered compounds have anisotropic crystal structure and basically exhibit ferroelectric properties.However, in certain orientation axis directions, the properties as ferroelectrics are small and paraelectric It is known to exhibit the property as
- the properties of the bismuth layered compound as a ferroelectric substance are not preferable when the bismuth layered compound is used as a dielectric of a thin film capacitor, because it causes a change in the dielectric constant. It is preferable that the property is sufficiently exhibited.
- the bismuth layer compound has a small ferroelectric property, and has a dielectric layer in which the bismuth layer compound is oriented in the direction of the orientation axis showing the property as a paraelectric substance.
- Central Processing Unit and other developments are required to develop a large-capacity thin film capacitor with excellent dielectric properties suitable for incorporation into a semiconductor wafer. Disclosure of the invention Therefore, the present invention is a small-sized, large-capacity thin-film capacitor excellent in dielectric properties suitable for being incorporated into a semiconductor wafer, together with other devices such as a field-effect transistor (FET) and a CPU (Central Processing Unit). It is an object of the present invention to provide a laminate unit including an electrode layer and a dielectric layer, which can constitute the same.
- This and other objects of the present invention are to provide a semiconductor wafer with a barrier layer, a dielectric material having anisotropy and conductivity, and further comprising a bismuth layered compound.
- An electrode layer formed of a material that can be epitaxially grown and oriented in the [001] direction; and a dielectric material containing a bismuth layered compound formed on the electrode layer by epitaxial growth.
- a dielectric layer made of a dielectric material containing a bismuth layered compound oriented in the [001] direction is achieved by the laminated unit laminated in this order.
- the [001] orientation refers to the [001] orientation in cubic, tetragonal, monoclinic, and orthorhombic.
- the barrier layer is formed on the semiconductor wafer, the components of the electrode layer are prevented from being affected by the semiconductor wafer force s and the electrode layer, such as being diffused into the semiconductor wafer. Therefore, the electrode layer can be formed as desired using a material having anisotropy and high conductivity, and on which a dielectric material containing a bismuth layered compound can be epitaxially grown. , [001] orientation. Further, according to the present invention, the electrode layer is formed of a material having anisotropy and conductivity, and on which a dielectric material containing a bismuth layer compound can be epitaxially grown, Since it is oriented in the [001] direction, it also functions as a buffer layer.
- a dielectric material containing a bismuth layered compound is epitaxially grown on the electrode layer, thereby ensuring that [001] 1] It is possible to form a dielectric layer containing a bismuth layered compound oriented in the direction.
- the present invention it is possible to orient the c-axis of the bismuth layered compound contained in the dielectric layer perpendicularly to the electrode layer. Therefore, for example, when an upper electrode is provided on a dielectric layer and a voltage is applied between the electrode layer and the upper electrode, the direction of the electric field is substantially equal to the c-axis of the bismuth layered compound contained in the dielectric layer. Therefore, it is possible to suppress the property of the bismuth layer compound contained in the dielectric layer as a ferroelectric substance and sufficiently exhibit the property as a normal dielectric substance.
- a large-capacity thin-film capacitor together with other devices into a semiconductor wafer, it becomes possible to produce an integrated device with a semiconductor.
- the dielectric layer made of a dielectric material containing a bismuth layered compound with improved c-axis orientation has high insulating properties, the dielectric layer can be made thinner. According to this, it is possible to further reduce the size of the thin film capacitor, and to further reduce the size of an integrated device with a semiconductor in which the thin film capacitor is incorporated.
- an upper electrode is formed on a dielectric layer and another semiconductor device such as a CPU (Central Processing Unit) is mounted on the manufactured thin-film capacitor
- another semiconductor Since the device is generally formed on a semiconductor wafer, if the semiconductor wafer of another semiconductor device is formed of the same material as the semiconductor wafer of the stacked unit, the thermal expansion of the thin film capacitor will occur. The rate of expansion matches the coefficient of thermal expansion of the other semiconductor device mounted on it, and the difference in the coefficient of thermal expansion between the mounted devices has the effect of damaging the joint of both depises. Can be prevented.
- the dielectric material containing the bismuth layer compound may contain unavoidable impurities.
- the material for forming a semiconductor wafer is not particularly limited as long as it is a material used for manufacturing a semiconductor device incorporating various devices.
- a silicon single crystal Gallium arsenide crystal or the like can be used.
- the laminate unit is formed on a semiconductor wafer by a Paria layer It has.
- the barrier layer has a function of preventing the semiconductor wafer from being affected by the electrode layer, for example, the constituent components of the electrode layer formed on the barrier layer are diffused into the semiconductor wafer.
- the material for forming the barrier layer is not particularly limited as long as the material can prevent the influence of the semiconductor wafer force and the electrode layer.
- silicon oxide is preferably used in order to reduce cost, and in addition, in order to form a parier layer.
- gallium arsenide crystal is used as a semiconductor wafer, from the viewpoint of stability, in order to form the Paglia layer, aluminum oxide (a 1 2 0 3) and magnesium oxide (M g O) is preferably used.
- the barrier layer is formed to a thickness such that the electrode layer formed thereon does not affect the semiconductor wafer or more.
- the laminate unit includes an electrode layer oriented in the [001] direction, that is, in the c-axis direction, on the paria layer.
- the electrode layer is formed of a material having anisotropy and conductivity and capable of epitaxially growing a dielectric material containing a bismuth layered compound thereon. ] Orientation. Therefore, the electrode layer is formed by epitaxially growing a dielectric material containing a bismuth layer compound on the electrode layer, and then bismuth oriented in the [001] direction, that is, in the c-axis direction. It has a function as a buffer layer that ensures that a dielectric layer containing a layered compound can be formed reliably.
- the electrode layer When an electrode layer made of platinum or the like is formed directly on a barrier layer made of silicon oxide, etc., the electrode layer is oriented in the [111] direction. It becomes difficult to epitaxially grow a dielectric layer made of a dielectric material containing a compound to orient the bismuth layered compound in the [001] direction, that is, in the c-axis direction.
- the electrode layer has anisotropy and electrical conductivity, and further comprises a dielectric material containing a pi and smth layered compound.
- the electrode layer is formed of a material that can be epitaxially grown, the electrode layer can be oriented in the [001] direction, and thus, the dielectric material including the bismuth layered compound can be epitaxially grown.
- the bismuth layer compound contained in the dielectric layer can be surely oriented in the [001] direction, that is, in the c-axis direction. .
- the material for forming the electrode layer is a material having anisotropy and conductivity, and on which a dielectric material containing a bismuth layered compound can be epitaxially grown.
- a dielectric material containing a bismuth layered compound can be epitaxially grown.
- an oxide superconductor is preferably used for forming an electrode layer.
- oxide superconductors copper oxide superconductor having a C u 0 2 surface thereof, to form the electrode layers, in particular is preferably used.
- the degree of orientation in the [001] direction of the material having anisotropy and conductivity contained in the electrode layer that is, the degree of c-axis orientation is 100%.
- the degree of c-axis orientation may be 80% or more.
- the c-axis orientation is preferably 90%, and more preferably 95% or more.
- the degree of c-axis orientation of the material having anisotropic conductivity is defined by the following equation (1).
- Equation (1) having a fully random you doing anisotropic and electrically conductive alignment material C-axis orientation ratio, that is, the (0 0-?) Plane of anisotropically conductive material with completely random orientation Reflection intensity from /.
- (k /) ⁇ ) is the c-axis orientation ratio of the anisotropic and conductive material calculated using the X-ray diffraction intensity, that is, from the (0 0) plane of the bismuth layered compound.
- I (h 0 1) from the crystal plane ( ⁇ 7) of the anisotropic conductive material It is the ratio ( ⁇ / (0 0 2) / ⁇ I (hk 1) ⁇ ) to the sum ⁇ I ⁇ hk 1).
- h, i :, and zo can each take any integer value of 0 or more.
- the electrode layer is formed by a vacuum deposition method, a sputtering method, a pulse laser deposition method (PLD), a metal-organic chemical vapor deposition (MOCVD) method, and an organic gold separation angle method.
- organic decomposition (MOD) ⁇ It can be formed using various thin film forming methods such as liquid phase method (CSD method) such as sol-genole method.
- the laminate unit includes a dielectric layer made of a dielectric material containing a bismuth layered compound oriented in the [001] direction, that is, in the c-axis direction, on the electrode layer.
- the dielectric layer is formed by epitaxially growing a dielectric material containing a bismuth layered compound on the electrode layer.
- the dielectric layer is formed by epitaxially growing a dielectric material containing a bismuth layered compound on the electrode layer oriented in the [001] direction, so that the bismuth layer included in the dielectric layer is formed.
- the compound can be reliably oriented in the [001] direction, that is, in the c-axis direction.
- the bismuth layered compound contained in the dielectric layer functions not as a ferroelectric material but as a paraelectric material.
- large-capacity thin-film capacitors with excellent dielectric properties can be incorporated into semiconductor wafers together with other devices.
- the bismuth layered compound forming the dielectric layer a bismuth layered compound excellent in characteristics as a capacitor material is selected.
- the bismuth layered compound has a composition represented by a stoichiometric composition formula: (B i 2 ⁇ 2 ) 2 + (A m — l B m 3m + 1 ) 2 — or B i 2 Am — I have.
- the symbol _m in the stoichiometric composition formula is a positive integer
- each of the bismuth layered compounds has
- Layered perovskite layer 1 consisting of (in-1) perovskite lattices composed of 0 3 la and (B i 2 0 2 ) 2+ layer 2 alternately stacked It has a structure.
- the number of layers of the layered perovskite layer 1 and (B i 2 O 2 ) 2 + layer 2 is not particularly limited, and at least a pair of (B i 2 O 2 ) 2 + layer 2 and It is sufficient to have one layered perovskite layer 1 sandwiched.
- the c-axis of the bismuth layer compound a pair of (B i 2 0 2 ') 2+ layer 2 direction connecting to each other, ie, a [0 0 1] direction.
- the degree of orientation of the [001] orientation of the bismuth layered compound contained in the buffer layer that is, the degree of c-axis orientation is not necessarily 100%, and the degree of c-axis orientation is not necessarily 100%. What is necessary is just 80% or more.
- the c-axis orientation degree F is preferably 90 ° / 0 , and more preferably the c-axis orientation degree F is 95% or more.
- the degree of c-axis orientation of the bismuth layered compound is defined by equation (1).
- the thickness of the dielectric layer is set to, for example, 100 nm or less.
- a thin film capacitor having a relatively high dielectric constant and a low loss (ta ⁇ ⁇ ) can be obtained, a thin film having excellent leakage characteristics, improved withstand voltage, excellent temperature characteristics of dielectric constant, and excellent surface smoothness. It becomes possible to obtain a capacitor.
- the bismuth layered compound contained in the dielectric layer the stoichiometric compositional formula: C a X S r - a composition represented by (1 x) B i 4 T i 4 0 1 5 Have. Where 0 ⁇ ⁇ 1.
- a bismuth layered compound having such a composition is used, a dielectric layer having a relatively large dielectric constant can be obtained, and its temperature characteristics are further improved.
- part of the element represented by the symbol ⁇ or ⁇ contains scandium (Sc;), yttrium (Y), lanthanum ( L a), cerium (C e), praseodymium (P r), neodymium (N d), promethium (Pm), samarium (Sm), europium pium (E u), gadolinium (G d), terbidium (Tb), dysprosium (Dy), holmium (H0), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu). Both are preferably replaced by one element e (yttrium (Y) or a rare earth element).
- the preferable substitution amount depends on the value of _m.
- the Curie temperature of the dielectric layer (the phase transition temperature from ferroelectric to paraelectric) is preferably 100 ° C. or higher, and 100 ° C. or higher.
- the Curie temperature of the dielectric layer is preferably 100 ° C. or higher, and 100 ° C. or higher.
- it can be kept within the range of 50 ° C or more and 50 ° C or less.
- one Curie point is 110 ° C.
- the dielectric constant of the dielectric layer is improved.
- Curie temperature can be measured by DSC (differential scanning calorimetry) or the like. When the Curie point becomes lower than room temperature (25 ° C), ta ⁇ ⁇ further decreases, and as a result, the loss Q value further increases.
- the dielectric layer of the laminate unit according to the present invention has excellent leak characteristics, some of the elements represented by the symbol ⁇ or 5 in the stoichiometric composition formula of the bismuth layered compound are not used. If the element is replaced by element e, the leakage characteristics of the dielectric layer can be further improved, which is preferable. For example, even when a part of the element represented by the symbol ⁇ or in the stoichiometric composition formula of the bismuth layered compound is not replaced by the element? E, the dielectric constant of the laminate unit according to the present invention can be improved.
- a leakage current measured at the electric field intensity 5 0 k V / cm preferably, 1 X 1 0 _ 7 a / cm 2 or less, more preferably, 5 X 1 0- 8 a / cm 2 or less
- the short-circuit rate can be preferably 10% or less, more preferably 5% or less, but the stoichiometric composition of the bismuth layered compound in the stoichiometric composition formula some of the elements represented by the symbol ⁇ or ⁇ is, the element?
- the leakage current when measured under the same conditions preferably, 5 X 1 0 8 a / cm 2 or less , more preferably, 1 X 1 0 - it can be 8 a / c ⁇ 2 below, the short rate It is preferably 5% or less, more preferably 3% or less.
- the dielectric layer is formed by a vacuum deposition method, a sputtering method, a pulse laser deposition method (PLD), a metal-organic chemical vapor deposition (MO-CVD) method.
- organic decomposition: MO D It can be formed using various thin film forming methods such as liquid phase method (CSD method) such as ⁇ zonore and genole method, etc.
- CSD method liquid phase method
- the laminate unit including the electrode layer and the dielectric layer according to the present invention can be used not only as a component of a thin film capacitor but also as a laminate unit for emitting an inorganic EL element. That is, in order to make the inorganic EL element emit light, an insulating layer is required between the electrode layer and the inorganic EL element. However, a dielectric material containing a bismuth layered compound having improved c-axis orientation is required. The dielectric layer has a high insulating property, and therefore, an inorganic EL element is disposed on the dielectric layer, and another electrode is disposed on the inorganic EL element, and is separated from the electrode layer. By applying a voltage between the electrodes and the inorganic EL element, the inorganic EL element can emit light as desired. Will be possible.
- FIG. 1 is a diagram schematically showing the structure of a bismuth layered compound.
- FIG. 2 is a schematic partial cross-sectional view of a laminate unit according to a preferred embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
- FIG. 2 is a schematic partial cross-sectional view of a laminated body cut according to a preferred embodiment of the present invention.
- a laminate unit 1 is formed by laminating a parier layer 3, an electrode layer 4, and a dielectric layer 5 on a support substrate 2 in this order. ing.
- the support substrate 2 of the multilayer unit 1 is formed of silicon single crystal.
- the laminate unit 1 includes a barrier layer 3 formed of silicon oxide on a support substrate 2.
- the barrier layer 3 made of silicon oxide is formed, for example, by thermal oxidation of silicon.
- an electrode layer 4 is formed on the barrier layer 3.
- the electrode layer 4 has a stoichiometric composition formula: Bi 2 Sr 2 C It is formed by BSCCO (bismuth's calcium, calcium, iron oxide) having a thread represented by a Cu 2 O 8 and oriented in the [011] orientation.
- BSCCO bismuth's calcium, calcium, iron oxide
- BS CCO bismuth.strontium.calcium 'kappa.oxide
- the constituents of BSC CO bismuth's-stodium-calcium-carbon-oxide
- the electrode layer 4 is formed of a silicon single crystal.
- the constituent components of BS CCO bismuth strontium canopymium kappa oxide
- BSC CO bismuth 'stopenthium' calcium, kappa, oxide
- the parier layer 3 prevents the constituents of BSC CO (bismuth's calcium, calcium, kappa, and potassium) from diffusing into the silicon single crystal constituting the support substrate 2. Thickness, for example, 10 ⁇ m or more.
- the laminate Yuni' sheet 1 according to this embodiment, on Roh Ria layer 3, the stoichiometric compositional formula: in B i 2 S r 2 C a C u 2 0 8
- the electrode layer 4 is formed by BS CCO (bismuth's-ttrium-calcium'capper 'oxide) having a composition represented by the following formula, and is oriented in the [001] direction.
- BS CCO bismuth's-ttrium-calcium'capper 'oxide
- the electrode layer 4 was formed by epitaxially growing a dielectric material containing a bismuth layer compound on the function as an electrode, and was then oriented in the [001] direction, that is, in the c-axis direction.
- a buffer layer that guarantees that the dielectric layer 5 containing the bismuth layered compound can be formed reliably Function.
- the electrode layer is easily oriented in the [111] direction. It becomes difficult to epitaxially grow a dielectric layer made of a dielectric material containing a bismuth layered compound to orient the bismuth layered compound in the [01] orientation, that is, in the c-axis direction.
- the electrode layer 4 the stoichiometric compositional formula: B i 2 S r 2 C a C u BSC CO ( bismuth 'be sampled port Nchiumu-Kanoreshiumu having a composition represented by the 2 O 8 ⁇ Anisotropic conductive material and formed from a material on which a dielectric material containing a bismuth layered compound can be epitaxially grown. Therefore, the electrode layer 4 can be oriented in the [001] direction. Therefore, a dielectric material containing a bismuth layered compound is epitaxially grown thereon to form the dielectric layer 5.
- the bismuth layered compound contained in the dielectric layer 5 can be surely oriented in the [001] direction, that is, in the c-axis direction.
- the stoichiometric compositional formula B i 2 S r 2 C a C u BS CCO ( bismuth be sampled port inch ⁇ -time calcium Kappa one-Okisai de having a composition represented by 2 O s
- the electrode layer 4 is formed, for example, by pulsed laser deposition (PLD).
- BSCCO pulsed laser deposition method
- Te Niyotsu bismuth 'be sampled port Nchiumu - to form a calcium-force wrapper-Okisai de
- Ru for example, as a raw material
- BSCCO (bi having a composition represented by B i 2 S r 2 C a C u 2 O 8
- the barrier layer 3 made of silicon oxide is maintained at 650 ° C. by using strontium strontium and canoledium oxide as a target, and has a thickness of 100 nm.
- the laminated unit 1 includes a dielectric layer 5 formed on an electrode layer 4.
- the dielectric layer 5 is formed on the electrode layer 4 by metal-organic decomposition (MOD).
- MOD metal-organic decomposition
- a toluene solution of 2-ethylhexanoic acid Sr, a 2-ethylethylhexanoic acid Bi solution of 2-ethylhexanoic acid, and a 2-ethylethylhexanoic acid Ti solution of toluene are mixed.
- Stoichiometric ratio such that 1 mol of 2-ethylhexanoic acid Sr, 4 mol of 2-ethylhexanoic acid Bi and 4 mol of 2-ethylhexanoic acid Ti are mixed with toluene.
- the material solution obtained by dilution is applied onto the electrode layer 4 by spin coating, dried, and calcined at a temperature at which the obtained dielectric layer 5 is not crystallized.
- the same raw material solution is applied on the pre-fired dielectric layer 5 by spin coating, dried, pre-fired, and this operation is repeated.
- the dielectric layer 5 is fully baked, and is coated, dried, and pre-baked until a dielectric layer 5 having a required thickness, for example, a dielectric layer 5 having a thickness of 100 nm is obtained.
- a series of operations consisting of coating, drying, preliminary baking and main baking are repeated.
- the dielectric material containing the bismuth layered compound grows epitaxially, and the dielectric layer 5 oriented in the [001] direction, that is, the c-axis direction is formed.
- the laminate unit 1 includes a support substrate 2 made of a silicon single crystal, and a barrier layer 3, an electrode layer 4, and a dielectric layer 5 laminated on the support substrate 2.
- the supporting substrate 2 made of silicon single crystal can be provided together with other devices such as a field effect transistor and a CPU by providing an upper electrode on the dielectric layer 5.
- a device integrated with a semiconductor can be manufactured.
- the barrier layer 3 is formed by silicon oxide on the support substrate 2 formed of silicon single crystal
- the components of the electrode layer 4 constitute the support substrate 2
- the electrode layer 4 formed thereon, such as being diffused in the silicon single crystal, can be prevented from affecting the silicon single crystal, and thus has anisotropy and conductivity, and Then, the electrode layer 4 is formed as desired using a material capable of epitaxially growing a dielectric material containing a bismuth layered compound, and oriented in the [001] direction, that is, in the c-axis direction. It is possible to make it.
- the dielectric layer 5 made of the dielectric material containing the bismuth layered compound has the [001] orientation, that is, on the electrode layer 4 oriented in the c-axis direction, Since the dielectric material containing the bismuth layered compound is formed by epitaxial growth, the dielectric layer 5 can be surely oriented in the [001] direction and the c-axis orientation can be improved. become. Therefore, according to the present embodiment, the laminate unit 1 has the dielectric layer 5 formed of a dielectric material including a bismuth layered compound oriented in the [001] direction, that is, the c-axis direction.
- an upper electrode is provided on the dielectric layer 5 of the multilayer unit 1 according to the present embodiment to produce a thin film capacitor, and a voltage is applied between the electrode layer 5 and the upper electrode.
- the direction of the electric field almost coincides with the c-axis of the bismuth layered compound contained in the dielectric layer 5, and therefore, the bismuth layered compound contained in the dielectric layer 5 as a ferroelectric Since the properties can be suppressed and the properties as a paraelectric material can be fully exhibited, a small and large-capacity thin-film capacitor, together with other devices such as field-effect transistors and CPUs, can be used in silicon.
- single Support substrate made of crystal Incorporation in 2 makes it possible to produce an integrated device with a semiconductor.
- the laminate unit 1 has the dielectric layer 5 formed of a dielectric material containing a bismuth layered compound oriented in the [001] direction, that is, the c-axis direction.
- the dielectric layer 5 containing the bismuth layered compound with improved c-axis orientation has high insulation properties, the dielectric layer 5 can be made thinner, and therefore, the thin film capacitor can be made more compact. It is possible to further reduce the size, and it is possible to further reduce the size of an integrated device with a semiconductor in which a thin film capacitor is incorporated.
- a dielectric layer 5 formed of a dielectric material containing a bismuth layered compound having excellent characteristics as a denser material is laminated and formed in this order, but the laminated unit 1 is composed of a dielectric material.
- a plurality of unit laminates each including at least the electrode layer 4 and the dielectric layer 5 may be laminated on the layer 5, and the dielectric of the uppermost unit laminate may be formed.
- the top electrode By forming the top electrode on layer 5, It may be form a capacitor.
- the electrode layers included in the unit laminate are When the crystal of the conductive material is epitaxially grown and is not formed, the bismuth layered compound is not oriented even when the dielectric material including the bismuth layered compound is epitaxially grown on the electrode layer.
- the unit laminate is formed on the electrode layer and the electrode layer, [01 1] It is required that the dielectric layer 5 be formed of a dielectric material containing a buffer layer and a bismuth layered compound oriented in the direction, and be formed on the buffer layer.
- One or two or more unit laminates formed of a dielectric material containing a layered compound and composed of a dielectric layer 5 formed on a buffer layer are arranged on the dielectric layer 5 in an arbitrary order.
- the thin film capacitor may be formed by stacking and forming an upper electrode on the dielectric layer 5 of the uppermost unit stack.
- the support substrate 2 of the laminate unit 1 is formed of silicon single crystal, but it is not always necessary to use the support substrate 2 formed of silicon single crystal.
- the material for forming the semiconductor is not particularly limited as long as it is a material used for fabricating a semiconductor device incorporating various devices.For example, gallium arsenide may be used instead of silicon single crystal.
- the support substrate 2 can also be formed by a crystal or the like.
- the laminate unit 1 includes the barrier layer 3 formed of silicon oxide on the support substrate 2, and the barrier layer 3 formed on the support substrate 2 is formed of silicon oxide. It is not always necessary to form the electrode layer 4 on the support substrate 2 to prevent the constituent components of the electrode layer 4 formed thereon from being diffused into the support substrate 2 and to be affected by the electrode layer 4.
- the paria layer 3 may be formed of any material that can be formed.
- the support substrate 2 when arsenide gallium crystal is used, from the viewpoint of stability, in order that form a barrier layer, an aluminum oxide (A 1 2 0 3) and, ⁇ magnesium (M g O) is preferably used.
- the laminate unit 1 includes the paria layer 3 Above stoichiometric composition formula: formed by B i 2 S r 2 C a C u 2 O 8 in represented by BSC CO (. Bismuth 'be sampled port Nchiumu calcium force wrapper-Okisa I Do), that Above, the electrode layer 4 which also functions as a buffer layer for epitaxially growing a dielectric material containing a bismuth layered compound is provided.
- the electrode layer 4 is formed by a stoichiometric composition formula: Bi 2 S r 2 C a C u be formed by represented by BSC CO (bismuth 'scan Toronchi ⁇ -time calcium force wrapper-Okisai de) with 2 O 8 not absolutely necessary, the material forming the electrode layer 4 are different
- the material is not particularly limited as long as it is anisotropic and conductive, and can be used to epitaxially grow a dielectric material containing a bismuth layered compound thereon.
- An oxide superconductor is preferably used as a material having anisotropy and conductivity and on which a dielectric material containing a bismuth layered compound can be epitaxially grown.
- a copper oxide superconductor having two faces is particularly preferably used.
- the copper oxide superconductors having a C u 0 2 side the stoichiometric compositional formula:! B i 2 S r 2 C a n _ C u n 0 2 n + 4 at the indicated by BSC CO ( In addition to bismuth, sodium, calcium, iron, and oxide, a stoichiometric composition formula: YB a 2 Cu 3 ⁇ 7 — ⁇ YB CO (yttrium. Bismuth. Iron) Oxide).
- the electrode layer 4 of the laminate unit 1 is formed by pulsed laser deposition (PLD), but the electrode layer 4 is formed by pulsed laser deposition (PLD).
- the electrode layer 4 is not necessarily required, and the electrode layer 4 can be formed by vacuum evaporation, sputtering, organic metal deposition, or metal composition: K method (metai-organic chemical vapor deposition: MOCVD), and organic metal.
- Stoichiometric composition formula: S r B i 4 T i 40 expressed by ⁇
- a dielectric layer 5 formed of a dielectric material containing a bismuth layered compound having a composition represented by the following formula.On the electrode layer 4, the stoichiometric composition formula of the bismuth layered compound: 4, 3 Bi 2 + S r Stoichiometric composition formula: S r B i 4 T i 40 15
- the dielectric layer 5 can also be formed from a dielectric material containing a compound.
- the dielectric layer 5 of the multilayer unit 1 is formed by the metal-organic decomposition (MOD) method. It is not always necessary to form them by vacuum deposition, sputtering, pulsed laser deposition (PLD), metal-organic chemical vapor deposition (MOCVD),
- the dielectric layer 5 can be formed by another thin film forming method such as any other liquid phase method (CSD method).
- the multilayer unit 1 is used as a component of the thin film capacitor.
- the multilayer unit 1 is not only a component of the thin film capacitor but also includes an inorganic EL element. It can also be used as a laminate unit for emitting light. That is, in order to emit light from the inorganic EL element, an insulating layer is required between the electrode layer 4 and the inorganic EL element.
- a dielectric material containing a bismuth layered compound having improved c-axis orientation is required.
- the dielectric layer 5 has a high insulating property, and therefore, an inorganic EL element is disposed on the dielectric layer 5, and another electrode is disposed on the inorganic EL element. By applying a voltage to the inorganic EL element, the inorganic EL element can emit light as desired.
- a semiconductor device can be used together with other devices such as a field effect transistor (FET) and a CPU (Central Processing Unit).
- FET field effect transistor
- CPU Central Processing Unit
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- Ceramic Engineering (AREA)
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- Inorganic Chemistry (AREA)
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- Semiconductor Memories (AREA)
Description
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005502840A JPWO2004077561A1 (ja) | 2003-02-26 | 2004-02-18 | 電極層および誘電体層を含む積層体ユニット |
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|---|---|---|---|
| US10/375,897 | 2003-02-26 | ||
| US10/375,897 US6885540B2 (en) | 2003-02-26 | 2003-02-26 | Multi-layered unit including electrode and dielectric layer |
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| WO2004077561A1 true WO2004077561A1 (ja) | 2004-09-10 |
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| PCT/JP2004/001829 Ceased WO2004077561A1 (ja) | 2003-02-26 | 2004-02-18 | 電極層および誘電体層を含む積層体ユニット |
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| Country | Link |
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| US (1) | US6885540B2 (ja) |
| JP (1) | JPWO2004077561A1 (ja) |
| WO (1) | WO2004077561A1 (ja) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1598871A1 (en) * | 2003-02-27 | 2005-11-23 | TDK Corporation | Thin-film capacitative element and electronic circuit or electronic equipment including the same |
| KR20060114533A (ko) * | 2005-05-02 | 2006-11-07 | 삼성에스디아이 주식회사 | 평판 디스플레이 모듈의 장착 구조 및 이를 구비한 평판디스플레이 모듈 |
| JP2007095750A (ja) * | 2005-09-27 | 2007-04-12 | Canon Anelva Corp | 磁気抵抗効果素子 |
| JP2007287745A (ja) * | 2006-04-12 | 2007-11-01 | Seiko Epson Corp | 圧電材料および圧電素子 |
| CN110109293A (zh) * | 2019-04-04 | 2019-08-09 | 深圳市华星光电技术有限公司 | 液晶无机配向薄膜的制造方法 |
Citations (2)
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|---|---|---|---|---|
| JPH08335672A (ja) * | 1995-06-05 | 1996-12-17 | Sony Corp | 強誘電体不揮発性メモリ |
| JP2001077323A (ja) * | 1999-07-02 | 2001-03-23 | Toshiba Corp | 半導体装置の製造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5206788A (en) * | 1991-12-12 | 1993-04-27 | Ramtron Corporation | Series ferroelectric capacitor structure for monolithic integrated circuits and method |
| US5248564A (en) | 1992-12-09 | 1993-09-28 | Bell Communications Research, Inc. | C-axis perovskite thin films grown on silicon dioxide |
| US5426075A (en) * | 1994-06-15 | 1995-06-20 | Ramtron International Corporation | Method of manufacturing ferroelectric bismuth layered oxides |
| KR100199095B1 (ko) | 1995-12-27 | 1999-06-15 | 구본준 | 반도체 메모리 셀의 캐패시터 구조 및 그 제조방법 |
| JP3193302B2 (ja) | 1996-06-26 | 2001-07-30 | ティーディーケイ株式会社 | 膜構造体、電子デバイス、記録媒体および強誘電体薄膜の製造方法 |
| JP3195265B2 (ja) * | 1997-01-18 | 2001-08-06 | 東京応化工業株式会社 | Bi系強誘電体薄膜形成用塗布液およびこれを用いて形成した強誘電体薄膜、強誘電体メモリ |
| JP3472087B2 (ja) | 1997-06-30 | 2003-12-02 | Tdk株式会社 | 膜構造体、電子デバイス、記録媒体および酸化物導電性薄膜の製造方法 |
| US5994276A (en) | 1997-09-08 | 1999-11-30 | Mcmaster University | Composite high Tc superconductor film |
| JP3549715B2 (ja) * | 1997-10-15 | 2004-08-04 | 日本電気株式会社 | Bi層状強誘電体薄膜の製造方法 |
| US6096343A (en) | 1997-10-27 | 2000-08-01 | Gerhard Gergely | Instant calcium/soybean granules, their use and process for their preparation |
| JP2001015382A (ja) | 1999-06-29 | 2001-01-19 | Kyocera Corp | 薄膜コンデンサ |
| US6566698B2 (en) * | 2000-05-26 | 2003-05-20 | Sony Corporation | Ferroelectric-type nonvolatile semiconductor memory and operation method thereof |
| JP2003209179A (ja) | 2002-01-15 | 2003-07-25 | Fujitsu Ltd | 容量素子及びその製造方法 |
| JP4036707B2 (ja) * | 2002-08-12 | 2008-01-23 | 三洋電機株式会社 | 誘電体素子および誘電体素子の製造方法 |
-
2003
- 2003-02-26 US US10/375,897 patent/US6885540B2/en not_active Expired - Lifetime
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- 2004-02-18 WO PCT/JP2004/001829 patent/WO2004077561A1/ja not_active Ceased
- 2004-02-18 JP JP2005502840A patent/JPWO2004077561A1/ja not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335672A (ja) * | 1995-06-05 | 1996-12-17 | Sony Corp | 強誘電体不揮発性メモリ |
| JP2001077323A (ja) * | 1999-07-02 | 2001-03-23 | Toshiba Corp | 半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2004077561A1 (ja) | 2006-06-08 |
| US20040165334A1 (en) | 2004-08-26 |
| US6885540B2 (en) | 2005-04-26 |
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