WO2004077163A2

WO2004077163A2 - Method for creating a pattern on a wafer using a single photomask

Info

Publication number: WO2004077163A2
Application number: PCT/IB2004/000444
Authority: WO
Inventors: Jan Willem Gemmink; Patrice Declementi
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2003-02-26
Filing date: 2004-02-11
Publication date: 2004-09-10
Anticipated expiration: 2005-08-26
Also published as: WO2004077163A3

Abstract

The present invention relates to a method for imaging a wafer in the manufacturing of integrated circuits. Said method is based on the use of a single photomask comprising a multiplicity of mask patterns positioned in separate areas on said photomask. A given mask pattern is dedicated to the formation of a given design layer on the wafer. Said imaging method comprises the step of exposing the wafer using the single photomask to form a first level of circuitry on the wafer. It also comprises a step of translating the single photomask and then exposing the wafer using the single photomask to form a second level of circuitry on the wafer, the translation of the photomask being performed in such a way that a predetermined sequence of design layers is achieved.

Description

Method for imaging a wafer using a single photomask

FIELD OF THE INVENTION

The present invention relates to a method for imaging a wafer, based on the use of a single photomask comprising a multiplicity of mask patterns positioned in separate areas on said photomask, a given mask pattern being dedicated to the formation of a given design layer on the wafer.

It also relates to the single photomask for use in such an imaging method.

This invention is particularly relevant for the manufacturing of integrated circuits.

BACKGROUND OF THE INVENTION

The patent US 4,758,863 discloses such a method for imaging wafers in the production of integrated circuits. Such a method utilizes a multi-level reticle, hereinafter referred to as photomask, comprising a multiplicity of integrated circuit mask patterns which are located in separate areas on the photomask, more precisely in separate quadrants. The photomask is adapted to be received in a conventional projection stepper apparatus for projection of light through one of the separate quadrants of the photomask to project a mask pattern onto a substrate such as a wafer. Then the photomask can be rotated about its center so that another of the separate quadrants is placed in proper position for projection of light through another mask pattern onto the substrate. The several mask patterns on the photomask are positioned such that they will project registering images on a substrate when the reticle is rotated about its center. In this manner a single photomask provides multiple image patterns so that an integrated circuit may be produced having various levels of circuitry. Such a method has several drawbacks. Firstly, mask patterns for the design of the different layer levels are deliberately placed rotated on the single photomask. Such a photomask must then be loaded in the exposure tool in a rotated orientation. This can be done by pre-rotation prior to the loading of the photomask or by a rotation handler in the exposure tool. As a consequence, all pre- alignment patterns that are outside the exposure field need to be duplicated for all used orientations. This has an impact on the available image field for device patterns with large image field exposure tools, the so-called scanners, which don't have a circular but a rectangular image field. Secondly, the number of mask patterns, and, as a consequence, the number of levels of circuitry can be 2, 3 or 4 and is limited to 4, the photomask not being divisible in more than 4 quadrants.

Thirdly, rotation concept and overlay improvement are valid only in the case of stepper lenses, in which case, due to the rotation, matching of the same image area is achieved. This aspect is no longer valid in current scan and repeat systems. Moreover, mask writing X/Y differences with respect to pattern fidelity and overlay registration can have an impact on process capability due to the rotation.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a method for imaging a wafer, which is easier to implement, which is more adapted to current scan systems and which can be implemented for any number of levels of circuitry.

To this end, the imaging method in accordance with the invention is characterized in that it comprises the steps of: exposing the wafer using the single photomask to form a first level of circuitry on the wafer, translating the wafer position with respect to the single photomask and then exposing the wafer using the single photomask to form a second level of circuitry on the wafer, the translation of the wafer position with respect to the photomask being performed in such a way that a predetermined sequence of design layers is achieved.

Thus, the mask patterns for achieving the different levels of circuitry are not rotated but merely translated.

Thanks to this translation, the pre-alignment patterns that are outside the exposure field are no longer duplicated and are the same for the different mask patterns. Thus such a multi-level photomask can be used easily with large image fields. Standard pellicles can also be used on said photomask.

Moreover, the number of levels of circuitry is no longer limited to 4 and can be arranged in a matrix with a free choice for the number of columns and the number of rows. This number of columns and rows is limited only by the size of the mask pattern and the size of the image field.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in more detail, by way of example, with reference to the accompanying drawings, wherein:

Fig. 1 shows a multi-level photomask in accordance with the invention, Fig. 2 illustrates a first embodiment of the imaging method in accordance with the invention,

Fig. 3 shows a top view of the result of the first embodiment of the imaging method in accordance with the invention,

Figs. 4a, 4b, 4c and 4d show the different successive layers obtained according to the first embodiment of the imaging method in accordance with the invention, - Fig. 5 illustrates a second embodiment of the imaging method in accordance with the invention at the beginning of the first exposure step,

Fig. 6 illustrates a second embodiment of the imaging method in accordance with the invention at the beginning of the second exposure step, and

Figs. 7a, 7b, 7c and 7d show the different successive layers obtained according to the second embodiment of the imaging method in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a method for imaging a wafer in the manufacturing of integrated circuits. Said imaging method is based on the use of a single photomask. This method is particularly adapted for manufacturing integrated circuits in small quantities, for example for prototyping.

The single photomask comprises a multiplicity of mask patterns positioned in separate areas on said photomask. A given mask pattern located on the photomask is dedicated to the formation of a given design layer on the wafer. In the two following examples, said method is described in the case of a photomask comprising 4 mask patterns in the form of a matrix of 2 x 2. However, it will be apparent to a person skilled in the art that the present invention is not limited to such a photomask, but is also applicable to any matrix comprising 2 or more mask patterns, the number of mask patterns depending on the number of different layers to be made on a wafer.

A first embodiment of the imaging method in accordance with the invention is described in Fig. 1 to Fig. 4d.

As shown in Fig. 1, the single photomask PM comprises 4 mask patterns MPA to MPD aligned on said photomask in the form of a 2 x 2 matrix. A mask pattern MPA is dedicated to the formation of a design layer A on the wafer, a mask pattern MPB to the formation of a design layer B and so on.

The imaging method in accordance with this embodiment comprises a step of exposing the wafer using the single photomask to form a first level of circuitry on the wafer. As shown in Fig. 2, the single photomask is shifted both horizontally and vertically from the width and height of the photomask, respectively, in order to expose the whole wafer. The first level of circuitry obtained according to this first embodiment comprises the four design layers. As shown in Fig. 4a, a given section of the wafer alternatively comprises a design layer A and a design layer B horizontally adjacent to it. The imaging method comprises a first step of translating LT to the left the single photomask from the origin O, the translation distance of said first translating step being equal to the width of a mask pattern. The wafer is then exposed using the single photomask to form a second level of circuitry on the wafer. Thus one sequence of design layers AB is achieved per photomask size, that is for one fourth of the semiconductor devices present on the wafer, as shown in Fig. 4b.

The imaging method comprises a second step of translating upwards UT the single photomask from the origin O, the translation distance of said second translating step being equal to the height of a mask pattern. The wafer is then exposed using the single photomask to form a third level of circuitry on the wafer. Thus a sequence of design layers ABC is achieved for one fourth of the semiconductor devices, as shown in Fig. 4c.

The imaging method comprises a third step of translating ULT the single photomask from the origin O to the left, the translation distance being equal to the width of a mask pattern, and then upwards, the translation distance being equal to the height of a mask pattern. The wafer is then exposed using the single photomask to form a fourth level of circuitry on the wafer. Thus a sequence of design layers ABCD is achieved for one fourth of the semiconductor devices, as shown in Fig.4d, this design layer sequence corresponding to the integrated circuit to be manufactured.

The result of the imaging method is shown in Fig. 3. The locations on the wafer that have undergone exposure with an incorrect sequence of design layers are ignored once the process is completed for the wafer. In the example of Fig. 3, only 8 circuits are usable among the 36 circuits available on the wafer.

The method is particularly easy to implement. Although it wastes a lot of semiconductor devices on the wafer, about 80%, it can save a lot of money for prototyping. In effect, as the quantity required for development purposes (e.g. validation, test program development, quality and reliability tests, seed customer sampling, characterization) is low and the cost of the masks set is huge with regard to wafer cost, the imaging method in accordance with the invention is particularly adapted to reduce the development costs for first prototypes, metal fixes or full re-designs.

A second embodiment of the imaging method in accordance with the invention is described in Fig. 5 to Fig. 7d.

The imaging method according to this embodiment proposes to cover some areas of the photomask during the exposure and to adjust the exposure sequence in such a way that the whole wafer is exposed using only the desired mask pattern of the photomask.

Covering part of the photomask is realized, for example, thanks to an aperture, said aperture comprising aperture blades, which are independently adjustable so that the light of an illuminator only passes through the desired mask pattern of the photomask.

According to this second embodiment of the invention, the photomask is partly covered, i.e. the mask patterns MPB, MPC and MPD are covered, during a first exposure step in such a way that the wafer is exposed using only the mask pattern MPA in order to form a design layer A on the wafer, as shown in Fig. 5. The partly covered single photomask is then shifted both horizontally HS and vertically NS from the width and height of the mask pattern, respectively, in order to expose the whole wafer. The first level of circuitry obtained according to this embodiment comprises only the design layer A as shown in Fig. 7a, for a given section of the wafer.

The single photomask is then translated LT to the left with respect to the origin O and the wafer is exposed using the single photomask. The mask patterns MPA, MPC and MPD are covered during this second exposure step so that the wafer is exposed using only the mask pattern MPB in order to form a design layer B above the design layer A on the wafer, as shown in Fig. 6. The second level of circuitry obtained after complete shifting of the photomask comprises only the design layer B as shown in Fig. 7b, for the given section.

The single photomask is then translated upwards with respect to the origin O and the wafer is exposed using the single photomask. The mask patterns MPA, MPB and MPD are covered during this third exposure step so that the wafer is exposed using only the mask pattern MPC in order to form a design layer C above the design layers A and B on the wafer. The third level of circuitry obtained after complete shifting of the photomask comprises only the design layer C as shown in Fig. 7c, for the given section. Finally, the single photomask is then translated to the left and upwards with respect to the origin O and the wafer is exposed using the single photomask. The mask patterns MPA, MPB and MPC are covered during this fourth exposure step so that the wafer is exposed using only the mask pattern MPD in order to form a design layer D above the design layers A, B and C on the wafer. The fourth level of circuitry obtained after complete shifting of the photomask comprises only the design layer D as shown in Fig. 7d, for the given section.

Such an embodiment of the imaging method can also save a lot of money for prototyping while avoiding the manufacture of semiconductor devices that have an incorrect sequence of design layers on the wafer. In effect, these zones are useless and may, in addition, sometimes cause disruptions in operation when manufacturing the correct integrated circuits. The number of correctly manufactured integrated circuits is thus increased, it is theoretically almost 100% but the time necessary for manufacturing the integrated circuits is longer compared to the time according to the first embodiment of the invention.

Any reference sign in the following claims should not be construed as limiting the claim. It will be obvious that the use of the verb "to comprise" and its conjugations do not exclude the presence of any other steps or elements besides those defined in any claim. The word "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.

Claims

1 A method for imaging a wafer in the manufacturing of integrated circuits, based on the use of a single photomask (PM) comprising a multiplicity of mask patterns (MPA-MPD) positioned in separate areas on said photomask, a given mask pattern (MPA) being dedicated to the formation of a given design layer (A) on the wafer, said imaging method comprising the steps of: exposing the wafer using the single photomask to form a first level of circuitry on the wafer, - translating the single photomask and then exposing the wafer using the single photomask to form a second level of circuitry on the wafer, the translation of the photomask being performed in such a way that a predetermined sequence of design layers (ABCD) is achieved.

2 An imaging method as claimed in claim 1 , wherein the photomask is partly covered during an exposure step in such a way that the wafer is exposed using only one mask pattern (MPA, MPB, MPC or MPD) in order to form a design layer (A, B, C or D) corresponding to said mask pattern.

3 An imaging method as claimed in claim 1, wherein the photomask comprises more than four mask patterns.

4 A device for imaging a wafer in the manufacturing of integrated circuits, based on the use of a single photomask (PM) comprising a multiplicity of mask patterns (MPA-MPD) positioned in separate areas on said photomask, a given mask pattern (MPA) being dedicated to the formation of a given design layer (A) on the wafer, said device comprising: means for exposing the wafer using the single photomask to form a first level of circuitry on the wafer, means for translating the single photomask and then exposing the wafer using the single photomask to form a second level of circuitry on the wafer, the translation of the photomask being performed in such a way that a predetermined sequence of design layers (ABCD) is achieved.

5 A photomask (PM) for the manufacturing of an integrated circuit, comprising: a multiplicity of mask patterns (MPA-MPD) positioned in separate areas on said photomask, a given mask pattern (MPA) being dedicated to the formation of a given design layer (A) on a wafer, - the photomask being adapted to be translated in such a way that a predetermined sequence of design layers (ABCD) is achieved.