[go: up one dir, main page]

WO2004073072A1 - Dispositif semi-conducteur mis et procede de fabrication de celui-ci - Google Patents

Dispositif semi-conducteur mis et procede de fabrication de celui-ci Download PDF

Info

Publication number
WO2004073072A1
WO2004073072A1 PCT/JP2004/001408 JP2004001408W WO2004073072A1 WO 2004073072 A1 WO2004073072 A1 WO 2004073072A1 JP 2004001408 W JP2004001408 W JP 2004001408W WO 2004073072 A1 WO2004073072 A1 WO 2004073072A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric constant
film
high dielectric
semiconductor device
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2004/001408
Other languages
English (en)
Japanese (ja)
Inventor
Noriyuki Miyata
Manisha Kundu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to JP2005504970A priority Critical patent/JPWO2004073072A1/ja
Publication of WO2004073072A1 publication Critical patent/WO2004073072A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10D64/0134—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D64/01338—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Definitions

  • the present invention relates to a MIS type semiconductor device and a method of manufacturing the MIS type semiconductor device.
  • the present invention relates to a MIS type semiconductor device and a method of manufacturing the MIS type semiconductor device, and more particularly to an electrode Z used for a miniaturized MIS type semiconductor device. And technology for forming the Background art
  • MI S Metal Insulator Semiconductor
  • gate insulating film insulating film
  • Hf 0 2 relative permittivity £ ⁇ : 25
  • r Z r 02 £ r: 25
  • L n 2 0 3 £ r: 8 ⁇ 30
  • L n: the run evening Neu de Ta 2 0 3 (£ r: 26)
  • T i 0 2 £ r: 80
  • FIG. 7A to 7D are cross-sectional views in the order of steps showing a conventional method for manufacturing a MIS transistor having a high dielectric constant gate insulating film.
  • Consisting of S I_ ⁇ 2 very thin on the silicon substrate 1 to form a low dielectric constant interlayer 2 made of Hf 0 2 thereon high dielectric constant film 3 Sno Uz evening, vapor deposition, CVD (Chemical Vapor It is formed by using a deposition on factory method, ALD (atomic layer deposition) method (FIG. 7A).
  • ALD atomic layer deposition
  • ion implantation is performed using the gate portion as a mask, and heat treatment for activating the implanted impurities is performed to form an impurity diffusion layer 9 serving as a source / drain region on both sides of the gate portion [7th D Figure].
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2000-2202
  • Patent Document 2 Japanese Patent Application Laid-Open Publication No. 2000-334430
  • the oxidizing species 5 such as O 2 and H 20 remaining in the processing atmosphere are high.
  • the low dielectric constant intermediate layer 2 is grown by diffusing in the dielectric constant film 3 as indicated by the arrow and reaching the interface between the high dielectric constant film and the silicon substrate. The growth of this low-k layer hinders low EOT.
  • concentration of oxidizing species remaining in the atmosphere of the heat treatment differs every time the heat treatment is performed, the dispersion of the formed low dielectric constant layer becomes large, and the dispersion of the characteristics among the wafers becomes large.
  • the oxidized species remaining in the heat treatment atmosphere enter from the side wall of the gate portion, as shown in FIG.
  • the thick low dielectric constant intermediate layer 2 is formed on the side wall side.
  • the low dielectric constant intermediate layer formed on the side wall side is further grown by a subsequent heat treatment for activating the ion implantation.
  • An object of the present invention is to solve the above-mentioned problems of the prior art.
  • diffusion barrier layers formed on high-k films To prevent EOT from becoming thicker.
  • an MIS type semiconductor device in which a gate electrode is formed on a high dielectric constant gate insulating film.
  • An MIS type semiconductor device wherein a reaction layer which is a conductor layer formed by a reaction between an insulating film and a gate electrode is interposed between the gate electrode and the gate electrode. Is done.
  • a method for manufacturing a MIS type semiconductor device comprising:
  • a method for manufacturing a MIS type semiconductor device comprising:
  • a method for manufacturing a MIS type semiconductor device comprising:
  • the treatment may be performed by a heat treatment performed thereafter.
  • the heat treatment for improving the film quality of the high dielectric constant film is performed after the lower diffusion barrier layer is formed on the high dielectric constant film.
  • the low dielectric constant film grows undesirably because the electric conductivity film does not diffuse to reach the surface Will not be done.
  • the lower diffusion barrier layer is made conductive by reacting with the gate electrode material, it is possible to suppress an increase in E ⁇ T due to the formation of the diffusion noria layer.
  • the present invention also provides a heat treatment for repairing damage introduced into the high-dielectric-constant film by processing the gate portion in a state where at least the gate portion is covered with the upper diffusion barrier layer after processing the gate portion. Since the heat treatment is performed, the side surface of the low dielectric constant intermediate layer does not increase by this heat treatment.
  • FIG. 1A to 1F are cross-sectional views in the order of steps for explaining a first embodiment of the present invention.
  • 2A to 2C are cross-sectional views in the order of steps for explaining a second embodiment of the present invention.
  • FIG. 3 is an observation value of the interface S i 0 2 by XPS for explaining the effect of the present invention.
  • FIG. 4 is a graph showing the relationship between the heat treatment time and the thickness of the interface SiO 2 layer for explaining the effect of the present invention.
  • Figure 5 is a graph showing the relationship between the heat treatment time and the 0 2 pressure and incubation time.
  • FIG. 6 is a schematic diagram of a heat treatment apparatus according to an embodiment of the present invention.
  • 7A to 7D are cross-sectional views in the order of steps showing a conventional method for manufacturing a MIS semiconductor device.
  • FIG. 8 is a cross-sectional view for explaining one problem of a conventional manufacturing method.
  • FIG. 9 is a cross-sectional view for explaining another problem of the conventional manufacturing method. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIGS. 1A to 1F are sectional views showing a first embodiment of the present invention in the order of steps.
  • a silicon substrate 1 having a suitable specific resistance after partitioning an active region to form a dielectric isolation region by etc. STI (shallow trench isolation) method, by performing hand thermal oxidation vacuum 0 2 on the substrate surface forming a low dielectric intermediate layer 2 of S i 0 2 very thin (less than 2 atomic layers).
  • This low dielectric constant intermediate layer 2 is not formed aggressively. It may be a natural oxide film that is inevitably formed when the dielectric film 3 is formed.
  • the high dielectric constant film 3 is deposited one or more of the three.
  • the high-dielectric-constant metal oxide may be formed by oxidizing a metal in an oxidizing atmosphere while depositing a metal by a snow-burning method, a laser ablation method, an evaporation method, or the like. Good.
  • a diffusion barrier layer 4 (FIG. 1A).
  • the thickness of the diffusion barrier layer 4 is preferably at least 0.4 nm, more preferably at least 0.6 nm (or at least two atomic layers). If the film thickness is less than this, the function of suppressing oxygen permeation is reduced.
  • the relative dielectric constant of the material forming the diffusion barrier layer 4 is not high, so it is desirable to keep it below 1.5 nm (or below 5 atomic layers) to keep EOT low.
  • heat treatment is performed for the purpose of densifying the high dielectric constant film 3 and removing defects.
  • oxidizing species such as O 2 and H 20 may remain in the atmosphere, but oxidizing species 5 may enter the high dielectric constant film 3 due to the diffusion noria layer 4.
  • Desirable heat treatment temperature is 650-850 ° C.
  • the heat treatment can be performed using a resistance heating furnace or a lamp arrayer, but may be performed continuously in a film forming chamber where the diffusion barrier layer 4 is formed.
  • a gate electrode material film 6a is formed by depositing polysilicon, polycide, refractory metal silicide, refractory metal, and the like by a sputtering method, a CVD method, a vapor deposition method, etc. (FIG. 1C).
  • the gate electrode material film 6a, the diffusion barrier layer 4, the high dielectric constant film 3, and the low dielectric constant intermediate layer 2 other than the gate portion are etched and removed by applying photolithography and RIE.
  • a gate portion having a gate electrode 6 is formed on the gate insulating film 7 (FIG. 1D). In this etching step, the side surfaces of the high dielectric constant film 3 are exposed to plasma, so that charges are injected and damaged.
  • a heat treatment is performed by covering the entire surface including the gate portion with the diffusion nori layer 8.
  • the material, film forming method, film thickness, and the like of the diffusion barrier layer 8 are the same as those of the diffusion barrier layer 4. However, if the barrier layer is removed after heat treatment, It may be a conductive material.
  • the heat treatment conditions are the same as those shown in FIG. 1B. Since the gate portion is covered with the diffusion barrier layer 8, the thickness of the side surface of the low dielectric constant intermediate layer does not increase even after the heat treatment is completed (FIG. 1E).
  • an impurity diffusion layer 9 which is a source / drain region [FIG. 1F] c
  • a metal wiring connected to the source / drain region is formed.
  • the heat treatment in the state shown in FIG. 1E may be omitted, and the heat treatment for activating the implanted impurities may also serve as the heat treatment for damage repair of the high dielectric constant film 3. Further, the diffusion barrier layer 8 may be removed before ion implantation for forming the source and drain regions.
  • FIG. 2A to FIG. 2C are cross-sectional views in the order of steps showing a second embodiment of the present invention.
  • a low dielectric constant intermediate layer 2 and a high dielectric constant film 3 are formed on a silicon substrate 1 by a method similar to that of the first embodiment shown in FIG.
  • the diffusion barrier layer 4 is formed using a material which is low and which becomes a conductive material by reacting with the gate electrode forming material. Then, heat treatment is performed to improve the film quality of the high dielectric constant film (FIG. 2A).
  • a gate electrode material film 6a is formed on the diffusion barrier layer (FIG. 2B), and heat treatment is performed to cause the diffusion barrier layer 4 to react with the gate electrode material film 6a to form a conductive reaction layer 10. [Fig. 2C]. Thereafter, as in the first embodiment, the gate portion is processed to form a source / drain region, and a series of manufacturing steps is completed.
  • Examples of the combination of the diffusion barrier layer 4 and the gate electrode material film 6a include nitride or silicide and a high melting point metal such as aluminum nitride and titanium, silicon nitride and titanium, and silicon carbide and titanium.
  • nitride or silicide and a high melting point metal such as aluminum nitride and titanium, silicon nitride and titanium, and silicon carbide and titanium.
  • O 2 2 xl 0- 6 T orr the (2 6 6 x 1 0- 4 P a.) Atmosphere, by thermal oxidation of 650 C, 10 min, the 0. 3 nm thick S i 0 2 to form a low dielectric constant intermediate layer 2 on the silicon substrate 1, on which, a high dielectric constant film 3 the hf 0 2 film 2. thereby forming the 6 nm thick.
  • HF0 2 film, and the H f in vacuo 0 2 atmosphere deposited by causing electron beams one beam evaporation.
  • FIG. 3 shows the Si 2 p photoelectron spectrum of these examples and comparative examples by XPS (X-ray excitation photoelectron spectroscopy).
  • Figure 4 is 0 2 atmosphere pressure 1 X 10- 5 T orr (1. 33x10 "3 Pa), shows the change in time and the interface S i 0 2 having a thickness of performing heat treatment at 800 ° C are. If there is no a 1 2 0 3 barriers layer interface S i 0 2 layers heating initial stage is growing. On the other hand, if there is burr ⁇ layer up to about 5 minutes increases the interfacial layer (This time is referred to as incubation in the present specification), after which slow growth and growth begin, which is determined by the diffusion of the oxidizing species in the barrier layer, It is thought to depend on the partial pressure of the species.
  • FIG. 5 is a graph showing changes in Inkyube one Chillon against 0 2 pressure and heat treatment temperature. This result, 0 2 pressure does not exceed a fin-incubated over Chillon Knowing Netsusho physical condition, that is, to determine the optimum heat treatment time for the heat treatment temperature.
  • FIG. 6 is a schematic diagram of a heat treatment apparatus configured to perform heat treatment for a desired time at a desired heat treatment temperature.
  • an infrared lamp 13 for irradiating the wafer 11 with infrared rays is arranged.
  • New 2 of which inert gas is supplied, indoor gas is exhausted by the exhaust pump 17.
  • the partial pressure of the oxidizing species in the room is measured by a differential exhaust type mass spectrometer 14 which receives the room gas through the orifice 20 and, based on the measured value, the controller 19 determines the desired heating temperature.
  • a differential exhaust type mass spectrometer 14 which receives the room gas through the orifice 20 and, based on the measured value, the controller 19 determines the desired heating temperature.
  • 15 is a valve and 16 is an exhaust bonnet.
  • the present invention is not limited to these, and can be appropriately changed without departing from the gist of the present invention.
  • the heat treatment for improving the film quality of the high-dielectric-constant film does not necessarily have to be performed alone, but may be performed by a heat treatment performed thereafter.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Selon l'invention, afin d'empêcher le développement d'un film à constante diélectrique basse (un film d'oxyde de silicium) disposé entre un substrat (1) et un film à constante diélectrique élevée (3) dans un MOSFET, le film à constante diélectrique élevée étant utilisé comme film d'isolation de grille, un traitement thermique permettant de modifier les propriétés du film à constante diélectrique élevée (3) est effectué après la formation du film à constante diélectrique élevée (3) et d'une couche barrière de diffusion (4) sur le substrat (1). Un film en matériau d'électrode de grille est ensuite déposé et une électrode de grille (6) est formée par modelage dudit film en matériau d'électrode de grille. Au cours de cette étape de gravure, les surfaces latérales du film à constante diélectrique élevée (3) sont exposées à un plasma et sont ainsi soumises à une injection de charges ou d'autres dommages. Afin de décharger les charges et de réparer les dommages, un traitement thermique est effectué pendant le recouvrement de l'ensemble de la surface, notamment la partie de grille, au moyen d'une couche barrière de diffusion (8). Une couche de diffusion d'impuretés devant constituer une région de source/drain est ensuite formée.
PCT/JP2004/001408 2003-02-17 2004-02-10 Dispositif semi-conducteur mis et procede de fabrication de celui-ci Ceased WO2004073072A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005504970A JPWO2004073072A1 (ja) 2003-02-17 2004-02-10 Ｍｉｓ型半導体装置およびｍｉｓ型半導体装置の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003-038061 2003-02-17
JP2003038061 2003-02-17

Publications (1)

Publication Number Publication Date
WO2004073072A1 true WO2004073072A1 (fr) 2004-08-26

Family

ID=32866381

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2004/001408 Ceased WO2004073072A1 (fr) 2003-02-17 2004-02-10 Dispositif semi-conducteur mis et procede de fabrication de celui-ci

Country Status (2)

Country Link
JP (1) JPWO2004073072A1 (fr)
WO (1) WO2004073072A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005210060A (ja) * 2003-12-26 2005-08-04 Fujitsu Ltd 半導体装置とその製造方法
JP2008514019A (ja) * 2004-09-21 2008-05-01 フリースケール セミコンダクター インコーポレイテッド 半導体デバイス及び同デバイスを形成する方法
JP2008521215A (ja) * 2004-11-15 2008-06-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体構造およびそれを形成する方法（金属酸化物の付着を介して形成されたしきい電圧制御層を含む窒素含有電界効果トランジスタ・ゲート・スタック）
US7892913B2 (en) 2008-04-25 2011-02-22 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225870A (ja) * 1985-03-29 1986-10-07 Fujitsu Ltd Ｍｉｓトランジスタの製造方法
JPH04134866A (ja) * 1990-09-27 1992-05-08 Toshiba Corp 電界効果トランジスタ装置及びその製造方法
JPH05183155A (ja) * 1992-01-06 1993-07-23 Fujitsu Ltd 半導体装置及びその製造方法
JPH11345967A (ja) * 1998-06-02 1999-12-14 Nec Corp Ｍｏｓトランジスタ、その製造方法及びそれを含む集積回路
EP1035564A2 (fr) * 1999-01-13 2000-09-13 Lucent Technologies Inc. Couche de barrière pour des materiaux à constante diéléctrique élevée
US6326670B1 (en) * 1999-03-11 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002184773A (ja) * 2000-12-19 2002-06-28 Nec Corp 高誘電率薄膜の成膜方法及び高誘電率薄膜を用いた半導体装置の製造方法
JP2003008005A (ja) * 2001-06-21 2003-01-10 Matsushita Electric Ind Co Ltd 高誘電率絶縁膜を有する半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225870A (ja) * 1985-03-29 1986-10-07 Fujitsu Ltd Ｍｉｓトランジスタの製造方法
JPH04134866A (ja) * 1990-09-27 1992-05-08 Toshiba Corp 電界効果トランジスタ装置及びその製造方法
JPH05183155A (ja) * 1992-01-06 1993-07-23 Fujitsu Ltd 半導体装置及びその製造方法
JPH11345967A (ja) * 1998-06-02 1999-12-14 Nec Corp Ｍｏｓトランジスタ、その製造方法及びそれを含む集積回路
EP1035564A2 (fr) * 1999-01-13 2000-09-13 Lucent Technologies Inc. Couche de barrière pour des materiaux à constante diéléctrique élevée
US6326670B1 (en) * 1999-03-11 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002184773A (ja) * 2000-12-19 2002-06-28 Nec Corp 高誘電率薄膜の成膜方法及び高誘電率薄膜を用いた半導体装置の製造方法
JP2003008005A (ja) * 2001-06-21 2003-01-10 Matsushita Electric Ind Co Ltd 高誘電率絶縁膜を有する半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005210060A (ja) * 2003-12-26 2005-08-04 Fujitsu Ltd 半導体装置とその製造方法
JP2008514019A (ja) * 2004-09-21 2008-05-01 フリースケール セミコンダクター インコーポレイテッド 半導体デバイス及び同デバイスを形成する方法
JP2008521215A (ja) * 2004-11-15 2008-06-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体構造およびそれを形成する方法（金属酸化物の付着を介して形成されたしきい電圧制御層を含む窒素含有電界効果トランジスタ・ゲート・スタック）
US7892913B2 (en) 2008-04-25 2011-02-22 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and semiconductor device
US7952148B2 (en) 2008-04-25 2011-05-31 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and semiconductor device

Also Published As

Publication number Publication date
JPWO2004073072A1 (ja) 2006-06-01

Similar Documents

Publication Publication Date Title
JP4047075B2 (ja) 半導体装置
US6955973B2 (en) Method for forming a semiconductor device
US7135361B2 (en) Method for fabricating transistor gate structures and gate dielectrics thereof
US6727148B1 (en) ULSI MOS with high dielectric constant gate insulator
US7737511B2 (en) Semiconductor device and method of manufacturing the same
US7115533B2 (en) Semiconductor device manufacturing method
US6762114B1 (en) Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness
US8785272B2 (en) Process to make high-K transistor dielectrics
US20010006843A1 (en) Method for forming a gate insulating film for semiconductor devices
US20040126944A1 (en) Methods for forming interfacial layer for deposition of high-k dielectrics
JPH11135774A (ja) 高誘電率シリケート・ゲート誘電体
JP3746478B2 (ja) 半導体装置の製造方法
JP4489368B2 (ja) 半導体装置およびその製造方法
WO2003088357A1 (fr) Dispositif a semi-conducteur et son procede de fabrication
CN101986421A (zh) 介电膜、使用该介电膜的半导体器件的制造方法和半导体制造设备
US6436840B1 (en) Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process
US6440868B1 (en) Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process
JP2002299607A (ja) Ｍｉｓ型電界効果トランジスタ及びこれの製造方法
US9786762B2 (en) Gate electrode of a semiconductor device, and method for producing same
US6528362B1 (en) Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process
JP2001085427A (ja) 酸窒化膜およびその形成方法
WO2004073072A1 (fr) Dispositif semi-conducteur mis et procede de fabrication de celui-ci
JP2003100995A (ja) 半導体装置およびその製造方法
US20050202627A1 (en) Method for forming a dielectric layer in a semiconductor device
JP2005079563A (ja) 電子デバイスの製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005504970

Country of ref document: JP

122 Ep: pct application non-entry in european phase