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WO2004068665A2 - Technique d'emballage a l'echelle de la tranche pour emballer hermetiquement des elements optiques et emballages hermetiques correspondants - Google Patents

Technique d'emballage a l'echelle de la tranche pour emballer hermetiquement des elements optiques et emballages hermetiques correspondants Download PDF

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Publication number
WO2004068665A2
WO2004068665A2 PCT/US2004/001790 US2004001790W WO2004068665A2 WO 2004068665 A2 WO2004068665 A2 WO 2004068665A2 US 2004001790 W US2004001790 W US 2004001790W WO 2004068665 A2 WO2004068665 A2 WO 2004068665A2
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WIPO (PCT)
Prior art keywords
wafer
front surface
devices
semiconductor die
connections
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PCT/US2004/001790
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English (en)
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WO2004068665A3 (fr
Inventor
Ronald Foster
Ajay P. Malshe
Chad O'neal
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University of Arkansas System
University of Arkansas at Fayetteville
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University of Arkansas System
University of Arkansas at Fayetteville
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Publication of WO2004068665A2 publication Critical patent/WO2004068665A2/fr
Anticipated expiration legal-status Critical
Publication of WO2004068665A3 publication Critical patent/WO2004068665A3/fr
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Definitions

  • This invention is concerned with packaging techniques for optical elements or devices which require electrical and/or optical input signals, actuation or conversion of input signals between optical and electrical domains, and electrical and/or optical outputs.
  • Packaging techniques are flexible, allowing for a variety of devices to be placed in a miniature sealed cavity, and to have external electrical and optical connections. Electrical connections are made in a manner to minimize interference with optical signals. Both single element devices and arrays, of devices may be packaged by the methods disclosed.
  • Optical components have been packaged for many years in a relatively standardized T046 Lens can.
  • Many state-of-the-art optical devices such as Vertical Cavity Surface Emitting Laser (VCSEL) or photodetectors are currently packaged into hermetically sealed T046 packages, which is generally a metal container with a window or lens attached to the top of the package such that light may enter or be emitted from the package.
  • VCSEL Vertical Cavity Surface Emitting Laser
  • these T046 packages may be custom designed in order to facilitate coupling of the light into an optical fiber.
  • These packages are both large and expensive . What is needed is an updated approach that will result in significant reduction in both size and cost of the components, enabling higher packing density of electronics .
  • T046 package is limited..in,ability_to provide for high, frequencies-, due to a number of parasitic capacitances and inductances related to the package itself. Newer packages are required which minimize parasitic capacitance and inductance, and enable further increase in system operating frequencies.
  • packaging methods have typically been developed as hybrid approaches, with subassemblies created and placed into higher level packages.
  • hybrid approaches are expensive, often exposing the semiconductor die or other components to a variety of environmental variables both during assembly and over life.
  • backside connection When applied properly, backside connection may support minimization of parasitic capacitance and inductance. Interconnection lengths are shortened by proper application. Also, substrate losses may be minimized by choice of materials and design.
  • an insulating material such as silicon dioxide or silicon nitride may be deposited following hole formation but prior to depositing a conductive material.
  • a thinner substrate provides a clear advantage in required area for a via , but thinner substrates tend to be fragile, and make fabrication more difficult and costly.
  • the packaging methods are flexible, allowing for a variety of devices to be placed in a miniature sealed cavity, and to have external electrical and optical connections to the completed component . Electrical connections are made in a manner to minimize interference with optical signals.
  • Both single element devices and arrays of devices may be packaged by the methods disclosed.
  • Both passive and active optical elements may be included in the packages .
  • means to incorporate passive optical elements such as lenses or mirrors fabricated by low-cost wafer-level methods. Such optical elements are fundamentally integrated into the component design.
  • means to incorporate active optical elements such as light emitters, moveable mirrors or devices which change index of refraction in response to an applied voltage .
  • Figure 1 is a cross-section view of component fabrication steps up to a point where the wafer assembly is complete.
  • Figure 2 is a cross-section view of component fabrication steps of thinning the wafer to reveal vias, applying terminal metal, testing and dicing.
  • Figure 3 is a plan view of a single component.
  • FIG. 1 To better understand the invention, reference is made to Figures 1 through 3.
  • a silicon substrate or wafer 10 is used. It should be understood by those skilled in the art that other materials may be used such as, for example, a ceramic or glass wafer.
  • the package is shown constructed on a silicon wafer 10.
  • a substrate 10 with ⁇ 100> faceplane orientation is used.
  • the resistivity of the wafer is selected to be very high, such as greater than 1000 ohm-cm. While the dopant may be either N-type or P-type, the high resistivity will insure that a Schottky contact will be formed between any metal that contacts the silicon and the silicon itself. Additionally, electrical current flow between circuit nodes will be minimized by the high resistance of the silicon itself.
  • a layer of silicon dioxide 12 is grown on the wafer 10, patterned and etched in order to form masking material on the front surface. This initial pattern must be well aligned to the crystal plane, which is referenced to the flat on the substrate.
  • an oxide thickness of about 0.5 microns is used, although thickness in the range of approximately 0.05 - 5.0 microns may be used.
  • the wafer 10 is submitted to wet anisotropic etch in order to create regions 14 for through-the-wafer via connections 52 (see Fig. 3) .
  • these regions are etched 1 - 2 mils deep, whereas the total wafer thickness may be 10 - 30 mils.
  • silicon dioxide 12 is removed in street areas 16 by pattern and etch method. This prepares the surface 17 in these areas for anodic bonding.
  • Metal 15 is deposited over the wafer 10 to coat the slope of the anisotropic etch region as well as the top surface.
  • this metal 15 comprises an adhesion layer such as chrome or titanium- tungsten alloy, followed by gold.
  • the gold metal may be thickened by photoresist masking and plating techniques. As is well known in the art, excess metal in the field regions may be etched away by application of photolithography and wet etch techniques, leaving regions of metal electrically isolated from one another. A gold thickness of 5 - 50 microns is preferred in order to minimize electrical resistance to lateral flow of current. Provision is made for gold extended pads or interconnects 18 (see Fig. 3) by appropriate design of photomask.
  • a second wafer 20 is prepared by machining holes 22 through the wafer 20.
  • machining the wafer 20 includes ultrasonic slurry, drilling, sandblasting or wet etching.
  • this second wafer 20 is pyrex with a relatively high concentration of sodium oxide (i.e. greater than about 2.5% by weight) . Both top and bottom surfaces of the second wafer 20 are maintained to be smooth and polished.
  • the first and second wafers 10 and 20 are aligned together such that the through-the-wafer via connections 52 remain exposed by the holes 22 in the second wafer 20.
  • the wafers are bonded together.
  • anodic bonding also known as thermoelectric bonding is used.
  • thermoelectric bonding is used.
  • a wide range of temperature or applied voltage may be used in order to bond the wafers together.
  • anodic bonding may typically be completed at 350 C, with 1200 volts applied between the two wafers .
  • Semiconductor die or- other devices 25 are placed onto the surface 26 of the first wafer 10 in the recesses formed by holes 22 in the second wafer 20. These die devices 25 are permanently attached with any of the techniques of thermocompression bonding, eutectic bonding or epoxy bonding. Next, the die devices 25 are interconnected to the substrate by wirebonding, wedgebonding, tape or ribbon bonding 28 from the top of the devices 25 to the gold interconnect layers 18 prepared on the first wafer 10.
  • a third wafer 30 designated as a capping wafer is prepared.
  • this third wafer will be constructed of glass, but any optically clear but dense material may be used.
  • Advantage is made of the third wafer 30 in order to include various optical elements 32, for example lenses and partially reflecting mirrors. Fabrication of mirrors or lenses 32 in the glass can be accomplished using relatively low-cost wafer-level processing.
  • the optical elements 32 are particularly attractive when either a light emitter or light detector is included in the package, and when the light being emitted or detected is essentially monochromatic. In such a case, diffraction methods may be applied in such a way as to obtain the same effects as reflective or refractive optical elements. It may be important to align the capping wafer 30 over included devices 25 such that a lens region 32 of the wafer 30 is positioned correctly to have_ the desired effect .
  • the capping wafer 30 can be made to include an active optical element 32.
  • the glass can be made to diffract light, and act as a lens or other optical element 32.
  • any optical element 32 can be made by this technique, with the condition that the light source is essentially monochromatic.
  • the light emitted generally fits this criterion.
  • Embossing techniques or pattern and etch techniques may be applied to create the diffractive optical element (see, e.g., U.S. 5,597,613; U.S. 5,812,581; U.S. 5,799,030).
  • the wafer 30 may be molded or otherwise formed to include raised or indented portions, functioning as refractive optical elements 32.
  • Other optical materials may be added to the surfaces of the wafer 30 in order to enhance the refractive optical responses.
  • the degree of reflection can be controlled.
  • a photodiode is included in order to detect reflected light, and the signal produced by the photodiode is applied to an Automatic Gain Control (AGO circuit.
  • AGO circuit Automatic Gain Control
  • the light output from the VCSEL can be stabilized over the life of the product.
  • the third wafer 30 is placed over the wafer assembly and sealed together to form a composite assembly 38. Provision is made for control of ambient in the sealed environment 35 by performing the assembly of second and third wafers in a controlled enclosure.
  • Such controlled enclosure or sealed environment 35 may be evacuated, or may contain inert gases such as nitrogen, argon, helium or other.
  • the third wafer 30 may be sealed to the second wafer 20 by a variety of techniques, including but not limited to ultraviolet-curable adhesive, fritted glass, epoxy, anodic bonding, or eutectic alloy. It is an important -feature of- this invention to minimize temperature excursions during this bonding such as to maintain the integrity of any semiconductor die or other components that may be enclosed. This limitation on temperature will dictate the choice of bonding material and method.
  • the disclosed method results in having electrical connections 41 to the bottom side of the assembly 38.
  • the through-the-wafer via connections 52 are revealed by planar etching of the bottom wafer 10.
  • the bulk of the wafer 10 thickness may be removed by mechanical methods such as lapping and polishing.
  • an isotropic dry silicon etch is used to actually expose the metal 15 in the vias 52.
  • the final thickness of the bottom wafer 10 is preferably reduced to 1 to 2 mils.
  • terminal metal 45 may be desirable to apply terminal metal 45 to the through-the-wafer via connections 52.
  • bump metals are well known in the art, and are convenient for connections to printed circuit boards.
  • the first wafer 10 may be of the type known as wire-in-glass. This provides for through-the-wafer via connections 52 by casting wires in a glass ingot, and then wafering the ingot.
  • the second wafer 20 may be constructed of silicon. Bonding of first and second wafers 10 and 20 by anodic bonding is enabled by choice of one substrate being glass while the second substrate is silicon. Minimization of substrate losses is assured by maintaining the bottom substrate as relatively thick and of a dielectric material.
  • the second wafer 20 may be formed of any arbitrary material, limited only by the condition that an acceptable method may be found to bond the arbitrary material to glass .
  • the first wafer 10 may be constructed of a ceramic material, with for example "plugs" formed of tungsten and copper alloys in order to match thermal expansion coefficients as is well known in the art.
  • the second wafer 20 may be constructed of either silicon or glass or other material, and bonding between the two wafers will be accomplished by above listed methods excepting anodic bonding.
  • the second and -t-hi-rd wafers may be fabricated -as a-single composite wafer.
  • semiconductor die or other devices are placed onto the surface of the first wafer, attached and interconnected by wirebond, wedgebonding, tape or ribbon bonding 28 from the top of the die 25 to the gold interconnect layers 18 prepared on the first wafer 10.
  • the composite capping wafer may be aligned and bonded over the first wafer 10. While there may be advantages in this approach, one clear disadvantage is the potential to damage devices 25 or interconnect betweens devices during assembly. While preferred embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that changes can be made without departing from the principles and spirit of the invention, the scope of which is defined in the accompanying claims.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Lasers (AREA)
  • Led Device Packages (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

L'invention concerne un procédé à l'échelle de la tranche, permettant d'emballer des puces semi-conductrices ou d'autres dispositifs dans un milieu fermé hermétiquement. Selon ce procédé, une pluralité de tranches sont alignées et reliées les unes aux autres pour former un ensemble. Une surface avant d'une première tranche comporte des zones de type trous d'interconnexion, ainsi que des conducteurs à extension latérale qui sont reliés électriquement à du métal se trouvant au niveau desdites zones. Les puces semi-conductrices ou lesdits autres dispositifs sont fixé(e)s sur ladite surface avant et relié(e)s électriquement aux conducteurs. Une deuxième tranche comporte des trous qui forment des évidements destinés à loger les puces semi-conductrices ou lesdits autres dispositifs. Une troisième tranche sert d'élément de recouvrement pour lesdits évidements et permet de ménager un milieu fermé hermétiquement. La surface arrière de la première tranche est amincie pour fournir un accès électrique au métal se trouvant dans lesdites zones. Différents éléments optiques sont disposés dans l'ensemble, certains de ces éléments optiques étant formés par modification structurale de ladite troisième tranche. L'ensemble obtenu à la fin du procédé est divisé pour former des unités d'emballage individuelles.
PCT/US2004/001790 2003-01-24 2004-01-23 Technique d'emballage a l'echelle de la tranche pour emballer hermetiquement des elements optiques et emballages hermetiques correspondants Ceased WO2004068665A2 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007002725A1 (de) 2007-01-18 2008-07-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Gehäuse für in mobilen Anwendungen eingesetzte mikromechanische und mikrooptische Bauelemente
DE102007034888B3 (de) * 2007-07-16 2009-01-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mikrosystem und Verfahren zum Herstellen eines Mikrosystems
DE102008012384A1 (de) 2008-03-04 2009-09-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Deckel für Mikro-Systeme und Verfahren zur Herstellung eines Deckels
WO2011035783A1 (fr) * 2009-09-24 2011-03-31 Msg Lithoglas Ag Procédé de réalisation d'un agencement comprenant un composant appliqué sur un substrat support et agencement ainsi que procédé de réalisation d'un produit semi-fini et produit semi-fini
DE102011119610A1 (de) 2011-11-29 2013-05-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung strukturierter optischer Komponenten
US9620375B2 (en) 2012-09-28 2017-04-11 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Production method
DE102016105440A1 (de) 2016-03-23 2017-09-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung optischer Komponenten unter Verwendung von Funktionselementen

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4144516A (en) * 1976-03-29 1979-03-13 Aine Harry E Solid state transducer and method of making same
JPH0831617B2 (ja) * 1990-04-18 1996-03-27 三菱電機株式会社 太陽電池及びその製造方法
US6059188A (en) * 1993-10-25 2000-05-09 Symbol Technologies Packaged mirror including mirror travel stops
JP3613838B2 (ja) * 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
US6096155A (en) * 1996-09-27 2000-08-01 Digital Optics Corporation Method of dicing wafer level integrated multiple optical elements
US6235141B1 (en) * 1996-09-27 2001-05-22 Digital Optics Corporation Method of mass producing and packaging integrated optical subsystems
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6798931B2 (en) * 2001-03-06 2004-09-28 Digital Optics Corp. Separating of optical integrated modules and structures formed thereby
US6531767B2 (en) * 2001-04-09 2003-03-11 Analog Devices Inc. Critically aligned optical MEMS dies for large packaged substrate arrays and method of manufacture
US6753199B2 (en) * 2001-06-29 2004-06-22 Xanoptix, Inc. Topside active optical device apparatus and method

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US8201452B2 (en) 2007-01-18 2012-06-19 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Housing for micro-mechanical and micro-optical components used in mobile applications
DE102007002725A1 (de) 2007-01-18 2008-07-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Gehäuse für in mobilen Anwendungen eingesetzte mikromechanische und mikrooptische Bauelemente
DE102007034888B3 (de) * 2007-07-16 2009-01-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mikrosystem und Verfahren zum Herstellen eines Mikrosystems
DE102008012384A1 (de) 2008-03-04 2009-09-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Deckel für Mikro-Systeme und Verfahren zur Herstellung eines Deckels
US8517545B2 (en) 2008-03-04 2013-08-27 Fraunhofer-Gesellschaft zur Foerferung der Angewandten Forschung E.V. Cover for microsystems and method for producing a cover
EP3297036A1 (fr) * 2009-09-24 2018-03-21 MSG Lithoglas GmbH Procédé de fabrication d'un dispositif pourvu d'un élément de construction sur un substrat de support et dispositif ainsi que procédé de fabrication d'un produit semi-fini
WO2011035783A1 (fr) * 2009-09-24 2011-03-31 Msg Lithoglas Ag Procédé de réalisation d'un agencement comprenant un composant appliqué sur un substrat support et agencement ainsi que procédé de réalisation d'un produit semi-fini et produit semi-fini
CN102598288A (zh) * 2009-09-24 2012-07-18 Msg里松格莱斯股份公司 用于制造带有承载衬底上的结构元件的布置的方法和布置以及用于制造半成品的方法和半成品
US8966748B2 (en) 2009-09-24 2015-03-03 Msg Lithoglas Ag Method for manufacturing an arrangement with a component on a carrier substrate and a method for manufacturing a semi-finished product
US10580912B2 (en) 2009-09-24 2020-03-03 Msg Lithoglas Ag Arrangement with a component on a carrier substrate, an arrangement and a semi-finished product
DE102011119610A1 (de) 2011-11-29 2013-05-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung strukturierter optischer Komponenten
US9910273B2 (en) 2011-11-29 2018-03-06 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method for producing structured optical components
US9620375B2 (en) 2012-09-28 2017-04-11 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Production method
WO2017162628A1 (fr) 2016-03-23 2017-09-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Procédé de fabrication de composants optiques au moyen d'éléments fonctionnels
DE102016105440A1 (de) 2016-03-23 2017-09-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung optischer Komponenten unter Verwendung von Funktionselementen

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