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WO2004068576A3 - Method of forming a catalyst containing layer over a patterned dielectric - Google Patents

Method of forming a catalyst containing layer over a patterned dielectric Download PDF

Info

Publication number
WO2004068576A3
WO2004068576A3 PCT/US2003/041185 US0341185W WO2004068576A3 WO 2004068576 A3 WO2004068576 A3 WO 2004068576A3 US 0341185 W US0341185 W US 0341185W WO 2004068576 A3 WO2004068576 A3 WO 2004068576A3
Authority
WO
WIPO (PCT)
Prior art keywords
forming
containing layer
layer over
catalyst containing
patterned dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/041185
Other languages
French (fr)
Other versions
WO2004068576A2 (en
Inventor
Markus Nopper
Axel Preusse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10302644A external-priority patent/DE10302644B3/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2003299875A priority Critical patent/AU2003299875A1/en
Priority to GB0513698A priority patent/GB2417132B/en
Priority to JP2004567443A priority patent/JP5214092B2/en
Publication of WO2004068576A2 publication Critical patent/WO2004068576A2/en
Publication of WO2004068576A3 publication Critical patent/WO2004068576A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10P14/46—
    • H10W20/033—
    • H10W20/01—
    • H10W20/035—
    • H10W20/043—
    • H10W20/044—
    • H10W20/051—
    • H10W20/0425—
    • H10W20/425—

Landscapes

  • Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

A metal layer is maybe formed by means of a plating process on a surface region of an underlying material catalytically activated in that a catalyst is deposited or incorporated by CVD, PVD or ALD at least partially during the deposition of the underlying material. In this way, superior metal seed layers may be formed in high aspect ratio vias of metallization structures.
PCT/US2003/041185 2003-01-23 2003-12-22 Method of forming a catalyst containing layer over a patterned dielectric Ceased WO2004068576A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003299875A AU2003299875A1 (en) 2003-01-23 2003-12-22 Method of forming a catalyst containing layer over a patterned dielectric
GB0513698A GB2417132B (en) 2003-01-23 2003-12-22 Method of forming a metal layer over a patterned dielectric by electroless deposition using a catalyst
JP2004567443A JP5214092B2 (en) 2003-01-23 2003-12-22 Method for forming a metal layer on an insulator patterned by electroless plating using a catalyst

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10302644.4 2003-01-23
DE10302644A DE10302644B3 (en) 2003-01-23 2003-01-23 Process for producing a metal layer over a structured dielectric by means of electroless deposition using a catalyst
US10/602,192 2003-06-24
US10/602,192 US6951816B2 (en) 2003-01-23 2003-06-24 Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst

Publications (2)

Publication Number Publication Date
WO2004068576A2 WO2004068576A2 (en) 2004-08-12
WO2004068576A3 true WO2004068576A3 (en) 2004-09-10

Family

ID=32826166

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/041185 Ceased WO2004068576A2 (en) 2003-01-23 2003-12-22 Method of forming a catalyst containing layer over a patterned dielectric

Country Status (5)

Country Link
JP (1) JP5214092B2 (en)
KR (1) KR101098568B1 (en)
AU (1) AU2003299875A1 (en)
GB (1) GB2417132B (en)
WO (1) WO2004068576A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943106B1 (en) * 2004-02-20 2005-09-13 Micron Technology, Inc. Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling
JP2006128288A (en) * 2004-10-27 2006-05-18 Tokyo Electron Ltd Film forming method, semiconductor device manufacturing method, semiconductor device, program, and recording medium
EP2067878B1 (en) * 2007-07-31 2017-03-22 JX Nippon Mining & Metals Corporation Plated material having metal thin film formed by electroless plating, and method for production thereof
KR101277357B1 (en) * 2009-01-30 2013-06-20 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power
US20220344205A1 (en) * 2019-09-25 2022-10-27 Tokyo Electron Limited Substrate liquid processing method and substate liquid processing apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6461675B2 (en) * 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574095A (en) * 1984-11-19 1986-03-04 International Business Machines Corporation Selective deposition of copper
JPH0762545A (en) * 1993-08-30 1995-03-07 Mitsubishi Cable Ind Ltd Wiring board and its production
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
US6380083B1 (en) * 1998-08-28 2002-04-30 Agere Systems Guardian Corp. Process for semiconductor device fabrication having copper interconnects
US6610596B1 (en) * 1999-09-15 2003-08-26 Samsung Electronics Co., Ltd. Method of forming metal interconnection using plating and semiconductor device manufactured by the method
JP2001240960A (en) * 1999-12-21 2001-09-04 Nippon Sheet Glass Co Ltd Article coated with photocatalytic film, method for manufacturing the article, and sputtering target used to coat the film
KR100338112B1 (en) * 1999-12-22 2002-05-24 박종섭 Method of forming a copper wiring in a semiconductor device
WO2001049898A1 (en) * 2000-01-07 2001-07-12 Nikko Materials Co., Ltd. Method for metal plating, pre-treating agent, and semiconductor wafer and semiconductor device using the same
JP2001335952A (en) * 2000-05-31 2001-12-07 Rikogaku Shinkokai Electroless plating method, wiring device and its production method
JP2002004081A (en) * 2000-06-16 2002-01-09 Learonal Japan Inc Electroplating method for silicon wafer
US6479902B1 (en) * 2000-06-29 2002-11-12 Advanced Micro Devices, Inc. Semiconductor catalytic layer and atomic layer deposition thereof
JP2002025943A (en) * 2000-07-12 2002-01-25 Ebara Corp Substrate film forming method
JP2002053971A (en) * 2000-08-03 2002-02-19 Sony Corp Plating method and plating structure, semiconductor device manufacturing method and semiconductor device
EP1180553A1 (en) * 2000-08-15 2002-02-20 Air Products And Chemicals, Inc. CVD process for depositing copper on a barrier layer
JP4083968B2 (en) * 2000-11-02 2008-04-30 株式会社東芝 Manufacturing method of semiconductor device
US20020064592A1 (en) * 2000-11-29 2002-05-30 Madhav Datta Electroless method of seed layer depostion, repair, and fabrication of Cu interconnects
US6596344B2 (en) * 2001-03-27 2003-07-22 Sharp Laboratories Of America, Inc. Method of depositing a high-adhesive copper thin film on a metal nitride substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6461675B2 (en) * 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate

Also Published As

Publication number Publication date
GB2417132B (en) 2007-04-04
JP5214092B2 (en) 2013-06-19
GB2417132A (en) 2006-02-15
KR101098568B1 (en) 2011-12-26
AU2003299875A1 (en) 2004-08-23
GB0513698D0 (en) 2005-08-10
KR20050088363A (en) 2005-09-05
WO2004068576A2 (en) 2004-08-12
JP2006513325A (en) 2006-04-20

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