WO2004063827A1

WO2004063827A1 - Apparatus and method for making a constant current source

Info

Publication number: WO2004063827A1
Application number: PCT/SG2003/000004
Authority: WO
Inventors: Bo Shi
Original assignee: Agency for Science Technology and Research Singapore; National University of Singapore
Current assignee: Agency for Science Technology and Research Singapore; National University of Singapore
Priority date: 2003-01-08
Filing date: 2003-01-08
Publication date: 2004-07-29
Anticipated expiration: 2005-07-08
Also published as: AU2003303685A1

Abstract

An apparatus and a method for making a constant current source by using a constant transconductance source are disclosed. The constant current source comprises a constant voltage providing circuit, an on-chip resistor equivalent circuit, a current mirror circuit and a constant transconductance generating circuit. The on-chip resistor equivalent circuit includes a first MOSFET which is connected to the constant transconductance generating circuit for receiving a biasing voltage to bias the first MOSFET to operate in a deep triode region, thereby acting as a resistor. The constant voltage providing circuit includes a second MOSFET and an operational amplifier that is responsive to a reference voltage applied to the non-inverting terminal of the operational amplifier. The second MOSFET is biased to operate in a saturation region. The gate terminal of the second MOSFET is connected to the output terminal of the operational amplifier while the source terminal of the second MOSFET is connected to the inverting terminal of the operational amplifier and the drain terminal of the first MOSFET of the on-chip resistor equivalent circuit to provide a constant voltage to the first MOSFET for generating a constant current. The current mirror circuit is connected to the constant voltage providing circuit for mirroring the constant current to provide a constant current source for use by circuits requiring a constant current source.

Description

Apparatus and Method for Making a Constant Current Source

Field of the Invention This invention relates to constant current and constant transconductance generating circuits and, more specifically, to a metal-oxide-silicon field effect transistor biasing circuit for generatmg a constant current by using a constant transconductance source.

Background A constant current source is extensively incorporated into analog integrated circuits. The constant current source is used to establish a DC reference current for use in certain applications. For example, in analog-to-digital and digital-to-analog converters, a reference current is needed to establish the input or output full-scale range of the converters. However, for most applications where a current source needs to be. constant, a current generating circuit in the current source needs to use an off- chip resistor. This is so because the resistance of the off-chip resistor is not typically affected by the fluctuations in fabrication process and temperature of the integrated circuits. An example of a conventional constant current generating circuit 100, which makes use of an off-chip resistor Ri, is shown in FIG. 1. The constant current generating circuit 100 includes a voltage providing circuit 102, a current mirror circuit 104 and the off-chip resistor R_. connected as shown in FIG. 1. The voltage providing circuit 102 provides a constant voltage potential, which is substantially equal to a reference voltage, N_ref, at node A. Therefore, a current I_cc flowing through the off- chip resistor Ri is a constant current defined by the ratio N_ref/R_. The current I_cc can be tapped using the current mirror circuit 104 to provide a constant current I₀ for application by circuits requiring a constant current source.

Also extensively incorporated into analog integrated circuits is a constant transconductance source. The constant transconductance source is required as it affects the performance parameters of analog blocks. For example, the bandwidth of an operational amplifier is determined by the ratio g_m/Cι_, where g_m is the transconductance of transistors of the operational amplifier and C is the effective load capacitance. Therefore, to obtain a constant bandwidth, g_m and C_L must be kept constant. While it is not difficult to keep C constant, it is not so for the g_m. The g_m of the transistors is typically easily affected by changes in power supply, fabrication process and temperature of the integrated circuits. For the g_m of the transistors of the operational amplifier to be constant, the transistors can be biased with a current derived from a constant transconductance generating circuit. The constant transconductance generating circuit typically needs to use an off-chip resistor to provide the transistors in the constant transconductance generating circuit with constant g_m characteristic. An example of such a constant transconductance generating circuit is shown in FIG. 2. The circuit 200 was proposed by J. M. Steininger in "Understanding Wide-band MOS Transistors," IEEE Circuits and MOSFETs, Vol. 6, No. 3, pp. 26-31, May 1990. The basic principle of operation is based on the difference between the gate-to-source voltages of two different-sized metal-oxide-silicon field effect transistors (MOSFET) M7 and M8 being equal to the voltage across the off-chip resistor R₂. If the MOSFETs M9 and M10 have the same W/L ratio, where W represents the channel width and L represents the channel length of the MOSFETs M9 and M10, the current flowing through the MOSFET M7 and the off-chip resistor R₂ is the same as the current flowing through the MOSFET M8. The circuit 200 provides the MOSFET M8 with a constant transconductance characteristic that is proportional to the geometric ratios of the MOSFETs M7 and M8 and the inverse value of the off-chip resistor R₂. Thus, the transconductance of the MOSFET M8 is independent of changes in process, temperature, and power supply voltage.

The constant current and constant transconductance generating circuits, such as the foregoing circuits are commonly found coexisting in the same analog integrated circuit chip. When this is the case, it gives rise to a number of disadvantages since each of the constant current and transconductance generating circuits requires the use of an off-chip resistor. The disadvantages of using an off-chip resistor lie in it taking up valuable circuit board space and using an additional input-output pin of the analog integrated circuit chip. Therefore, if both the constant current and constant transconductance sources are required in the same analog integrated circuit chip, two input-output pins are required for two respective off-chip resistors. This is undesirable as the pins can be used for other much-needed functions such as for controlling or sensing. Further, using the off-chip resistors can give rise to noise injection problem.

An on-chip resistor cannot easily replace the off-chip resistor because it is difficult to achieve an accurate on-chip resistance. Further, the on-chip resistor suffers from large resistance variations, in some cases exceeding 50%, due to manufacturing process fluctuations and temperature changes. The variations in the resistance are undesirable as these inconsistencies prevent the generation of constant current and constant transconductance sources.

It is therefore desirable to provide a solution that alleviates the use of an off-chip resistor in a constant current generating circuit.

Summary

In accordance with a first aspect of the invention, there is provided a constant current generating circuit comprising: a constant transconductance generating circuit; a resistor equivalent circuit connected to the constant transconductance generating circuit for receiving a first voltage therefrom for biasing the resistor equivalent circuit for generating a substantially constant resistance; and a voltage providing circuit connected to the resistor equivalent circuit for providing a second voltage thereto, wherein a constant current is driven by the second voltage in opposition to the substantially constant resistance.

In accordance with a second aspect of the invention, there is provided a method for making a constant current source, the method comprising the steps of: providing a constant transconductance generating circuit for providing a first voltage; connecting a resistor equivalent circuit to the constant transconductance generating circuit for receiving the first voltage therefrom for biasing the resistor equivalent circuit for generating a substantially constant resistance; and connecting a voltage providing circuit to the resistor equivalent circuit for providing a second voltage thereto, wherein a constant current is driven by the second voltage in opposition to the substantially constant resistance.

Brief Descriptions of The Drawings

Embodiments of the invention are described hereinafter with reference to the following drawings, in which:

FIG. 1 shows a prior art electrical schematic diagram of a conventional constant current generating circuit;

FIG. 2 shows a prior art electrical schematic diagram of a constant transconductance generating circuit;

FIG. 3 shows an electrical schematic diagram of a constant current generating circuit according to a first embodiment of the invention; and

FIG. 4 shows an electrical schematic diagram of a constant current generating circuit according to a second embodiment of the invention.

Detailed Description

Circuits for generating a constant current by using a constant transconductance source are provided hereinafter. The description is provided with reference to the figures of the drawings, wherein like elements are identified with like reference numerals.

A circuit 300, as shown in FIG.3, for generating a constant current by using a constant transconductance source according to a first embodiment of the invention is described hereinafter. The circuit 300 includes a constant transconductance generating circuit 200, an on-chip resistor equivalent circuit 320, a voltage providing circuit 102, and a current mirror circuit 104. The constant transconductance generating circuit 200 can be of any known topology.

However, for illustrating the embodiments of the invention, the Steininger constant transconductance generating circuit 200, as shown in FIG. 2, is used and described accordingly. Similarly, the voltage providing circuit 102 and the current mirror circuit 104, as shown in FIG. 1, are used for illustrating the embodiments of the invention. It is therefore obvious to one skilled in the art that the embodiments of the invention are not limited to the use of these circuits and variations thereof are also applicable.

The on-chip resistor equivalent circuit 320 includes an n-channel metal-oxide-silicon field effect transistor (MOSFET) M4, which is preferably biased to operate in a linear or deep triode region. The source terminal of the MOSFET M4 is connected to the ground potential of the circuit 300 while the gate terminal is connected to the constant transconductance generating circuit 200 as shown in FIG. 3. The gate terminal of the MOSFET M4 is biased with a biasing voltage N__ιas ι provided by the constant transconductance generating circuit 200 to establish a constant biasing resistance at the MOSFET M4. The drain terminal of the MOSFET M4 is connected to the voltage providing circuit 102 to provide a temperature, power supply and process independent equivalent resistance for the generation of a constant current I_cc.

The voltage providing circuit 102 includes an operational amplifier 302, a reference voltage (N_re_f) 304, and an n-channel MOSFET Ml. N_ref 304, which can be derived from a band-gap source (not shown), is applied to the non-inverting input terminal of the operational amplifier 302 for providing a reference biasing voltage potential. The output terminal of the operational amplifier 302 is connected to the gate terminal of the MOSFET Ml, while the inverting terminal of the operational amplifier 302 is connected to the source terminal of the MOSFET Ml . The source terminal of the MOSFET Ml is also connected to the drain terminal of the MOSFET M4. Such biasing allows the MOSFET Ml to operate in a saturation region and the source terminal voltage of the MOSFET Ml to be maintained at a constant voltage potential substantially equal to N_ref 304. Thus, the current I_cc flowing through the MOSFET Ml and the MOSFET M4 of the on-chip resistor equivalent circuit 320 is given by: ^/« =^■ - ⁽¹⁾

where R_M represents the resistance provided by the MOSFET M4. The drain terminal of the MOSFET Ml is connected to a voltage potential N_dd if the current mirror circuit 104 is not required.

The current mirror circuit 104 includes two p-channel MOSFETs M2 and M3. The source terminals of the MOSFETs M2 and M3 are connected to the voltage potential N_dd while the gate terminals of these MOSFETs are interconnected. The interconnected gate terminals of the MOSFETs M2 and M3 are further connected to the drain terminal of the MOSFET M2. Thus, the MOSFET M2 is biased to operate in a saturation region and forms a current mirror with the MOSFET M3. The drain terminal of the MOSFET M2 is further connected to the drain terminal of the MOSFET Ml for drawing the current I_cc from the MOSFET M2 so as to provide a current I₀ at the drain terminal of the MOSFET M3. The current I₀ is constant if the current I_cc is constant; and the current I_cc is constant if R_M4 is constant.

When the MOSFET M4 operates in the deep triode region, R_M4 can be expressed in terms of the geometries and other properties of the MOSFET M4 as follows:

^RM4 - (2) μ_nC_0X(W/L)₄(V_gs4 - V_Tn)

where, in relation to the MOSFET M4, N_gs4 represents the gate-to-source voltage, (W/L)₄ represents the aspect ratio, Nχ_n represents the threshold voltage, μ_n represents the carrier mobility and C_ox represents the gate oxide capacitance per unit area.

Substituting R_M in equation (2) into equation (1) yields:

I_cc = μ_nC W/L)₄(V_gs4 - V_Tn)V_ref (3) The constant transconductance generating circuit 200 includes four MOSFETs M7, M8, M9 and M10, and an off-chip resistor R₂. The MOSFETs M7 and M8 are of an n-channel transistor type and the MOSFETs M9 and M10 are of a p-channel transistor type. The gate teπninals of the MOSFETs M9 and M10 are interconnected and are further connected to the drain terminal of the MOSFET M9 as shown in FIG. 3. The source terminals of the MOSFETs M9 and M10 are connected to the voltage potential N_dd, thereby forming a current mirror configuration to provide currents ϊ_cg__a and I_cg , to each of the MOSFETs M7 and M8, respectively. The gate terminals of the MOSFETs M7 and M8 are interconnected while the drain terminals are connected to the drain terminals of the MOSFET M9 and M10, respectively, for receiving the respective currents I_cg___a and I_cg__b- The off-chip resistor^' R₂ is connected to the source terminal of the MOSFET M7, which is biased to operate in a saturation region. The MOSFET M8 is also biased to operate in a saturation region with the gate and drain terminals of the MOSFET M8 being interconnected. If the MOSFETs M9 and M10 are of the same size, that is, having the same W/L ratio, where W represents the channel width and L represents the channel length of the MOSFETs M9 and M10, the currents I_cg__a and I_cg_b received by the MOSFETs M7 and M8 at the respective drain terminals are equal. With such a configuration, it is known that the transconductance of the MOSFET M8, g_m8, can be expressed as:

Equation (4) shows that the transconductance of the MOSFET M8 is dependent only on the sizes of the MOSFETs M7 and M8 and the resistor value of R₂. The variables μ_n and C_ox, which are affected by the changes in fabrication process and temperature, are not found in the final expression of g_m8 in equation (4). Thus, any MOSFET operating in a saturation region dependent on an operating current associating with I_cg___a or I_cg_b (which are equal) also inherits a constant transconductance characteristic. The gate-to-source voltages of the MOSFETs M7 and M8 can be expressed as follows, using the square-law model for the MOSFETs M7 and M8:

where N_gs7 and N_gs8 represent the gate-to-source voltage of the MOSFETs M7 and M8, respectively, (W/L) and (W/L)₈ represent the aspect ratios of the MOSFETs M7 and M8, respectively, and in relation to both the MOSFETs M7 and M8, N_Tn represents the threshold voltage, μ_n represents the carrier mobility and C_ox represents the gate oxide capacitance per unit area. Since the biasing voltage N_bi_as is drawn from the interconnected gate terminals of the MOSFETs M7 and M8, it is apparent that the biasing voltage N_bιas_ι is equal to N_gs8. Applying the Kirchhoff s voltage law to the loop consisting of the MOSFETs M7 and M8, and the off-chip resistor R₂, yields:

2E Cg. _ D II <.¥_α

^■ + Vτ,m - V_Tn + I_cg__aR₂ (6) μ_nC₀XW/L μ_nC_0X{WIL)_η

Solving equation (6) for I_cg , where I_cg represents the currents I_cg__a and I_cg__b since these two currents are equal, gives:

I (7)

Substituting I_cg of equation (7) into the N_gs8 expression in equation (5) and solving for N_gs8 provides the expression for Nb s_ι as follows:

Since the gate terminal of the MOSFET M4 is biased with the biasing voltage N_bi_asj, the gate-to-source voltage N_gs of the MOSFET M4 is the same as the biasing voltage

N_Was - Therefore, substituting Nbiasj of equation (8) into equation (3) to replace N_gs yields:

Equation (9) shows that the on-chip resistor equivalent circuit 320 can replace the off- chip resistor R__ as shown in FIG. 1, by biasing the MOSFET M4 to operate in the deep triode region using the biasing voltage Nbia_sj that is derived from the constant transconductance generating circuit 200 as described in the foregoing.

In a second embodiment of the invention, a circuit 400, as shown in FIG. 4, for generating a constant current by using a constant transconductance source is described hereinafter. The circuit 400 includes a constant transconductance generating circuit 200, an on-chip resistor equivalent circuit 320, a voltage providing circuit 102 and a current mirror circuit 104 and a resistance adjusting circuit 420. The constant transconductance generating circuit 200, the on-chip resistor equivalent circuit 320, the voltage providing circuit 102 and the current mirror circuit 104 in the first embodiment, as shown in FIG. 3, are incorporated herein in FIG. 4.

The operation of the circuit 400 is similar to the circuit 300 shown in FIG.3, with the exception of the resistance adjusting circuit 420. In the first embodiment, if the biasing voltage Nbiasj of the MOSFET M4 of the on-chip resistor equivalent circuit 320 requires adjustments to bias the MOSFET M4 to change its resistance, the sizes of the MOSFETs M7 and M8 also require adjustments to change the biasing voltage Nbiasj. However, this is undesirable as changing the sizes of the MOSFETs M7 and M8 can affect the operation of other on-chip circuits that depend on the constant transconductance generating circuit 310. The resistance adjusting circuit 420 alleviates the need to change the sizes of the MOSFETs M7 and M8 and provides an adjusted biasing voltage N_bi_as to bias the MOSFET M4 of the on-chip resistor equivalent circuit 320 as described hereinafter.

The resistance adjusting circuit 420 includes two MOSFETs M5 and M6, where the MOSFET M5 is an n-channel transistor type and the MOSFET M6 is a p-channel transistor type. The gate teπninal of the MOSFET M6 is interconnected with the drain and gate terminals of the MOSFET M9 of the constant transconductance generating circuit 310 so that the MOSFET M6 forms a current mirror configuration with the MOSFET M9. Like the MOSFET M9, the MOSFET M6 is biased to operate in the saturation region with the source terminal of the¹ MOSFET M6 being connected to a voltage potential N _d- Therefore, the current I_cg__a, which flows through the MOSFETs M9 and M7 is mirrored by the MOSFET M6 to produce a current I_d5 that flows through the drain terminal of the MOSFET M6. As shown in the foregoing description for the first embodiment, the current I_cg, which represents the currents I_cg__a and I_cg___b since these two currents are equal, can be expressed as follows:

where (W/L)₇ and (W/L)₈ represent the aspect ratios of the MOSFET M7 and M8, respectively, R₂ represents the resistance of the off-chip resistor R₂, and in relation both the MOSFETS M7 and M8, μ_n represents the carrier mobility and C_ox represents the gate oxide capacitance per unit area.

The MOSFET M5 is biased to operate in a saturation region with the source terminal of the MOSFET M5 being connected to the ground potential of the circuit 400. The gate and drain terminals of the MOSFET M5 are interconnected and are further connected to the drain teπninal of the MOSFET M6 for receiving the current I s therefrom. The current I_d5, which is mirrored from the MOSFET M9 by the MOSFET M6 can be expressed as follows: (WIL ι« = (W/L\ (11)

where the (W/L)₆ and (W/L)₉ represent the aspect ratios of the MOSFETs M6 and M9, respectively. As seen in equation (11), the MOSFET M6 also serves as a scaling factor for increasing or decreasing the magnitude of the current I_ds flowing through the MOSFETs M5 and M6, by varying the geometric size of the MOSFET M6. Accordingly, the changes in the current I_ds leads to changes in the biasing voltage

Nbiasj-

The current I s can also be expressed as follows using the square-law model equation for the MOSFET M5:

where in relation to the MOSFET M5, N_gss represents the gate-to-source voltage, Nχ_n represents the threshold voltage, μ_n represents the carrier mobility and C_ox represents the gate oxide capacitance per unit area.

Substituting equations (11) and (12) into equation (10) and solving for N_gss yields:

21 - mJ(W/L) (W/L)₇ lj(W/L)₆ ** = + ^vτ„ 1 μ_nC_mR₂^WIL)₅{WIL (WIL

The gate terminals of the MOSFET M4 of the on-chip resistor equivalent circuit 320 and the MOSFET M5 of the resistance adjusting circuit 420 are interconnected resulting in the gate-to-source voltages of the MOSFETs M4 and M5 being substantially the same. Thus, the MOSFET M4 is biased with the biasing voltage Nbiasj at its gate teπninal, where the biasing N_bi_as is substantially equal to the N_gss. Like in the first embodiment, the MOSFET M4 is preferably biased to operate in a deep triode region with the source terminal being connected to the ground potential and the drain terminal being connected to the source teπninal of the MOSFET Ml .

With this configuration, the drain current I_cc can be expressed as follows:

i_cc = μ_ncχwiL) (v_gs4 - v_Tn)v, ref (14)

Substituting N_gs5 of equation (13) into equation (14) to replace N_gs4 yields:

Further simplifying equation (15) yields:

Equation (16) shows that the current I_cc, which flows through the MOSFETs Ml, M2 and M4 is not affected by changes in the manufacturing process and the temperature of the circuit 400. The cuπent I_cc can be mirrored by the MOSFET M3 to generate a constant cuπent source I₀, as shown in FIG. 4.

In the foregoing manner, circuits for generating a constant cuπent by making use of a constant transconductance source are described according to the embodiments of the invention for addressing the foregoing disadvantages. Although only a number of embodiments are disclosed it will be apparent to one skilled in the art in view of the foregoing disclosure that numerous changes and modification can be made without departing from the scope and spirit of the invention. For example, the constant transconductance generating circuit 200 as shown in FIGs. 3 and 4 can be replaced by any known constant transconductance generating circuits regardless of whether these circuits use an off-chip resistor or not. Examples of such circuits include those proposed in U.S. Patent 4,484,089 by Nisawanathan and U.S. Patent 5,973,524 by

Martin. Further, the on-chip resistor equivalent circuit 320, the voltage providing circuit 102 and the cuπent minor circuit 104 can be replaced by respective circuits that provide the same respective functions.

Claims

Claims:

1. A constant cuπent generating circuit comprising: a constant transconductance generating circuit; a resistor equivalent circuit connected to the constant . transconductance generating circuit for receiving a first voltage therefrom for biasing the resistor equivalent circuit for generating a substantially constant resistance; and a voltage providing circuit connected to the resistor equivalent circuit for providing a second voltage thereto, wherein a constant cuπent is driven by the second voltage in opposition to the substantially constant resistance.

2. The circuit as in claim 1, wherein the transistor based resistor equivalent circuit comprises a metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals, wherein the MOSFET is biased to operate in a triode region with the gate terminal being connected to the constant transconductance generating circuit for receiving the first voltage therefrom, the source teπninal being connected to a reference potential and the drain terminal being connected to the voltage providing circuit for providing the substantially constant resistance thereto.

3. The circuit as in claim 1, wherein the voltage providing circuit is a constant voltage providing circuit.

4. The circuit as in claim 3, wherein the constant voltage providing circuit comprises: an operational amplifier having inverting input, non-inverting input and output terminals; a reference voltage source, the voltage at the reference voltage source being applied to the non-inverting input terminal of the operational amplifier; and a metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals, wherein the MOSFET is biased to operate in a saturation region with the drain terminal being connected to a third voltage, the gate terminal being connected to the output terminal of the operational amplifier and the source teπninal being connected to the inverting input teπninal of the operational amplifier for providing the source terminal of the MOSFET with the second voltage, the second voltage being substantially equal to the voltage at the reference voltage source, the source terminal of the MOSFET being further connected to the resistor equivalent circuit for providing the second voltage thereto for generating the constant cuπent.

5. The circuit as in claim 1, wherein the constant transconductance generating circuit further comprises a resistance adjusting circuit for adjusting the resistance of the resistor equivalent circuit by adjusting the first voltage for biasing the resistor equivalent circuit for generating the substantially constant resistance.

6. The circuit as in claim 5, wherein the resistance adjusting circuit comprises: first and second metal-oxide-silicon field effect transistors (MOSFETs), each of the MOSFETs having gate, source and drain terminals; the first MOSFET being biased to operate in a saturation region with the source terminal being connected to a third voltage and the gate terminal being connected to the constant transconductance generating circuit, thereby forming a cuπent minor configuration with a third MOSFET in the constant transconductance generating circuit for miπoring a first cuπent therefrom to provide a second cuπent at the drain terminal of the first MOSFET; and the second MOSFET being biased to operate in a saturation region with the source terminal being connected to a reference potential, the gate and drain terminals being interconnected and being further connected to the drain terminal of the first MOSFET for receiving the second cuπent for generating the first voltage at the gate terminal of the second MOSFET for biasing the resistor equivalent circuit for generating the substantially constant resistance.

7. The circuit as in claim 6, wherein the resistor equivalent circuit comprises a fourth metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals, wherein the fourth MOSFET is biased to operate in a triode region with the gate terminal being connected to the gate terminal of the second MOSFET for receiving the first voltage therefrom, the source terminal being connected to the reference potential and the drain terminal of the fourth MOSFET being connected to the voltage providing circuit for providing the substantially constant resistance thereto.

8. The circuit as in claim 1, further comprising an output circuit, wherein the output circuit is connected to the voltage providing circuit for outputting the constant cuπent.

9. The circuit as in claim 8, wherein the output circuit is a cuπent minor circuit, the cunent minor circuit being comiected to the voltage providing circuit for minoring the constant cuπent for outputting the constant cunent.

10. The circuit as in claim 9, wherein the cunent minor circuit comprises first and second metal-oxide-silicon field effect transistors (MOSFETs), each of the MOSFETs having gate, source and drain terminals, wherein the first and second MOSFETs are connected to form a cunent minor configuration with the gate terminals of the first and second MOSFETs being interconnected and being further comiected to the drain terminal of the second MOSFET, the source terminals of the first and second MOSFETs being connected to a third voltage and the drain teπninal of the second MOSFET being further connected to the voltage providing circuit to minor the constant cunent to provide the constant cuπent at the drain terminal of the first MOSFET for outputting the constant cuπent.

11. The circuit as in claim 10, wherein the voltage providing circuit comprises: an operational amplifier having inverting input, non-inverting input and output terminals; a reference voltage source, the voltage at the reference voltage source being applied to the non-inverting input terminal of the operational amplifier; and a third metal-oxide-silicon effect transistor (MOSFET) having gate, source and drain terminals, wherein the third MOSFET is biased to operate in a saturation region with the drain terminal being connected to the drain terminal of the second

MOSFET, the gate terminal being connected to the output teπninal of the operational amplifier and the source terminal being connected to the inverting input terminal of the operational amplifier for providing the source terminal of the third MOSFET with the second voltage, the second voltage being substantially equal to the voltage at the reference voltage source, the source terminal of the third MOSFET being further connected to the resistor equivalent circuit for providing the second voltage thereto for generating the constant cunent.

12. A method for making a constant cunent source, the method comprising the steps of: providing a constant transconductance generating circuit for providing a first voltage; connecting a resistor equivalent circuit to the constant transconductance generating circuit for receiving the first voltage therefrom for biasing the resistor equivalent circuit for generating a substantially constant resistance; and connecting a voltage providing circuit to the resistor equivalent circuit for providing a second voltage thereto, wherein a constant cunent is driven by the second voltage in opposition to the substantially constant resistance.

13. The method as in claim 12, wherein the step of connecting the resistor equivalent circuit comprises the steps of: providing a metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals; and biasing the MOSFET to operate in a triode region with the gate teπninal of the MOSFET being connected to the constant transconductance generating circuit for receiving the first voltage therefrom, the source terminal of the MOSFET being connected to a reference potential and the drain terminal of the MOSFET being connected to the voltage providing circuit for providing the substantially constant resistance thereto.

14. The method as in claim 12, wherein the step of connecting the voltage providing circuit comprises the steps of: providing an operational amplifier having inverting input, non-inverting input and output terminals; providing a reference voltage source and applying the voltage at the reference voltage source to the non-inverting input terminal of the operational amplifier; providing a metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals; and biasing the MOSFET to operate in a saturation region with the drain terminal being connected to a third voltage, the gate terminal being connected to the output teπninal of the operational amplifier and the source terminal being connected to the inverting input terminal of the operational amplifier for providing the source terminal of the MOSFET with the second voltage, the second voltage being substantially equal to the voltage at the reference voltage source, the source terminal of the MOSFET being further connected to the resistor equivalent circuit for providing the second voltage thereto for generating the constant cunent.

15. The method as in claim 12, wherein the step of providing the constant transconductance generating circuit further comprises the step of providing a resistance adjusting circuit for adjusting the first voltage, for biasing the resistor equivalent circuit for generating the substantially constant resistance.

16. The method as in claim 15, wherein the step of providing the resistance adjusting circuit comprises the steps of: providing first and second metal-oxide-silicon field effect transistors (MOSFETs), each of the MOSFETs having drain, source and gate terminals; biasing the first MOSFET to operate in a saturation region with the source terminal being connected to a third voltage and the gate teπninal being connected to the constant transconductance generating circuit, thereby forming a cunent minor configuration with a third MOSFET in the constant transconductance generating circuit for minoring a first cunent therefrom to provide a second cunent at the drain terminal of the first MOSFET; and biasing the second MOSFET to operate in a saturation region with the source terminal being connected to a reference potential, the gate and drain terminals being interconnected and being further connected to the drain terminal of the first MOSFET for receiving the second cunent for generating the first voltage at the gate terminal of the second MOSFET for biasing the resistor equivalent circuit for generating the substantially constant resistance.

17. The method as in claim 16, wherein the step of connecting the resistor equivalent circuit comprises the steps of: providing a fourth metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals; and biasing the fourth MOSFET to operate in a triode region with the gate terminal being connected to the gate teπninal of the second MOSFET for receiving the first voltage therefrom, the source terminal of the MOSFET being connected to the reference potential and the drain terminal of the fourth MOSFET being connected to the voltage providing circuit for providing the substantially constant resistance thereto.

18. The method as in claim 12, further comprising the step of connecting an output circuit to the voltage providing circuit for outputting the constant cunent.

19. The method as in claim 18, wherein the step of connecting the output circuit comprises the step of connecting a cunent minor circuit to the voltage providing circuit for outputting the constant cuπent.

20. The method as in claim 19, wherein the step of connecting the cuπent minor comprises the steps of: providing first and second metal-oxide-silicon field effect transistors (MOSFETs), each of the MOSFETs having gate, source and drain terminals, connecting the first and second MOSFETs to form a cuπent minor configuration with the gate terminals of the first and second MOSFETs being interconnected and being further connected to the drain terminal of the second

MOSFET, the source terminals of the first and second MOSFETs being connected to a third voltage and the drain terminal of the second MOSFET being further connected to the voltage providing circuit to minor the constant current to provide the constant cunent at the drain terminal of the first MOSFET for outputting the constant cunent.

21. The method as in claim 20, wherein the step of connecting the voltage providing circuit comprises the steps of: providing an operational amplifier having inverting input, non-inverting input and output terminals; providing a reference voltage source and applying the voltage at the reference voltage source to the non-inverting input terminal of the operational amplifier; providing a third metal-oxide-silicon field effect transistor (MOSFET) having gate, source and drain terminals; and biasing the third MOSFET to operate in a saturation region with the drain terminal being connected to the drain terminal of the second MOSFET, the gate terminal being connected to the output terminal of the operational amplifier and the source terminal being connected to the inverting input terminal of the operational amplifier for providing the source teπninal of the third MOSFET with the second voltage, the second voltage being substantially equal to the voltage at the reference voltage source, the source terminal of the third MOSFET being further connected to the resistor equivalent circuit for providing the second voltage thereto for generating the constant cunent.