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WO2004061863A3 - Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same - Google Patents

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same Download PDF

Info

Publication number
WO2004061863A3
WO2004061863A3 PCT/US2003/041446 US0341446W WO2004061863A3 WO 2004061863 A3 WO2004061863 A3 WO 2004061863A3 US 0341446 W US0341446 W US 0341446W WO 2004061863 A3 WO2004061863 A3 WO 2004061863A3
Authority
WO
WIPO (PCT)
Prior art keywords
global bit
memory array
block select
nand strings
select devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/041446
Other languages
French (fr)
Other versions
WO2004061863A2 (en
Inventor
Roy E Scheuerlein
Christopher Petti
Andrew J Walker
En-Hsing Chen
Sucheta Nallamothu
Alper Ilkbahar
Luca G Fasoli
Igor Kouznetsov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk 3D LLC
Original Assignee
Matrix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/335,089 external-priority patent/US7005350B2/en
Priority claimed from US10/335,078 external-priority patent/US7505321B2/en
Application filed by Matrix Semiconductor Inc filed Critical Matrix Semiconductor Inc
Priority to JP2004565772A priority Critical patent/JP2006512776A/en
Priority to AU2003300007A priority patent/AU2003300007A1/en
Publication of WO2004061863A2 publication Critical patent/WO2004061863A2/en
Publication of WO2004061863A3 publication Critical patent/WO2004061863A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)

Abstract

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer, preferably connected together by way of vertical stacked vias.
PCT/US2003/041446 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same Ceased WO2004061863A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004565772A JP2006512776A (en) 2002-12-31 2003-12-29 Programmable memory array structure incorporating transistor strings connected in series and method for manufacturing and operating this structure
AU2003300007A AU2003300007A1 (en) 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/335,078 2002-12-31
US10/335,089 US7005350B2 (en) 2002-12-31 2002-12-31 Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US10/335,078 US7505321B2 (en) 2002-12-31 2002-12-31 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US10/335,089 2002-12-31

Publications (2)

Publication Number Publication Date
WO2004061863A2 WO2004061863A2 (en) 2004-07-22
WO2004061863A3 true WO2004061863A3 (en) 2004-12-16

Family

ID=32716876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/041446 Ceased WO2004061863A2 (en) 2002-12-31 2003-12-29 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Country Status (3)

Country Link
JP (1) JP2006512776A (en)
AU (1) AU2003300007A1 (en)
WO (1) WO2004061863A2 (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100657910B1 (en) * 2004-11-10 2006-12-14 삼성전자주식회사 Multi-bit Flash Memory Device, Operation Method thereof, and Manufacturing Method Thereof
DE102005017072A1 (en) * 2004-12-29 2006-07-13 Hynix Semiconductor Inc., Ichon Charge trap insulator memory device, has float channel, where data are read based on different channel resistance induced to channel depending on polarity states of charges stored in insulator
US7709334B2 (en) 2005-12-09 2010-05-04 Macronix International Co., Ltd. Stacked non-volatile memory device and methods for fabricating the same
US7473589B2 (en) * 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US7764549B2 (en) 2005-06-20 2010-07-27 Sandisk 3D Llc Floating body memory cell system and method of manufacture
US7317641B2 (en) 2005-06-20 2008-01-08 Sandisk Corporation Volatile memory cell two-pass writing method
US7489546B2 (en) 2005-12-20 2009-02-10 Micron Technology, Inc. NAND architecture memory devices and operation
EP1997148A1 (en) * 2006-03-20 2008-12-03 STMicroelectronics S.r.l. Semiconductor field-effect transistor, memory cell and memory device
KR100806339B1 (en) * 2006-10-11 2008-02-27 삼성전자주식회사 Nand flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same
US7675783B2 (en) * 2007-02-27 2010-03-09 Samsung Electronics Co., Ltd. Nonvolatile memory device and driving method thereof
JP5175526B2 (en) 2007-11-22 2013-04-03 株式会社東芝 Nonvolatile semiconductor memory device and manufacturing method thereof
JP5288933B2 (en) * 2008-08-08 2013-09-11 株式会社東芝 Semiconductor memory device and manufacturing method thereof
JP5322533B2 (en) * 2008-08-13 2013-10-23 株式会社東芝 Nonvolatile semiconductor memory device and manufacturing method thereof
JP4945609B2 (en) 2009-09-02 2012-06-06 株式会社東芝 Semiconductor integrated circuit device
KR101547328B1 (en) * 2009-09-25 2015-08-25 삼성전자주식회사 Ferroelectric memory device and its operation method
JP5395738B2 (en) * 2010-05-17 2014-01-22 株式会社東芝 Semiconductor device
US8755227B2 (en) 2012-01-30 2014-06-17 Phison Electronics Corp. NAND flash memory unit, NAND flash memory array, and methods for operating them
JP2013161878A (en) * 2012-02-02 2013-08-19 Renesas Electronics Corp Semiconductor device and semiconductor device manufacturing method
US11729989B2 (en) * 2020-01-06 2023-08-15 Iu-Meng Tom Ho Depletion mode ferroelectric transistors
JP2021141283A (en) 2020-03-09 2021-09-16 キオクシア株式会社 Semiconductor storage device
CN112470225B (en) * 2020-10-23 2022-12-09 长江先进存储产业创新中心有限责任公司 Program and read bias and access scheme to increase data throughput of 2-stack 3D PCM memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923587A (en) * 1996-09-21 1999-07-13 Samsung Electronics, Co., Ltd. Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same
US5940321A (en) * 1994-06-29 1999-08-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US6163048A (en) * 1995-10-25 2000-12-19 Cypress Semiconductor Corporation Semiconductor non-volatile memory device having a NAND cell structure
US20010055838A1 (en) * 2000-04-28 2001-12-27 Matrix Semiconductor Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940321A (en) * 1994-06-29 1999-08-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US6163048A (en) * 1995-10-25 2000-12-19 Cypress Semiconductor Corporation Semiconductor non-volatile memory device having a NAND cell structure
US5923587A (en) * 1996-09-21 1999-07-13 Samsung Electronics, Co., Ltd. Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same
US20010055838A1 (en) * 2000-04-28 2001-12-27 Matrix Semiconductor Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

Also Published As

Publication number Publication date
AU2003300007A1 (en) 2004-07-29
WO2004061863A2 (en) 2004-07-22
JP2006512776A (en) 2006-04-13
AU2003300007A8 (en) 2004-07-29

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