WO2004059465A1 - Streamlining cpu utilisation by delaying transactions - Google Patents
Streamlining cpu utilisation by delaying transactions Download PDFInfo
- Publication number
- WO2004059465A1 WO2004059465A1 PCT/US2002/041431 US0241431W WO2004059465A1 WO 2004059465 A1 WO2004059465 A1 WO 2004059465A1 US 0241431 W US0241431 W US 0241431W WO 2004059465 A1 WO2004059465 A1 WO 2004059465A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- accordance
- central processing
- processing unit
- transaction request
- predetermined threshold
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/503—Resource availability
Definitions
- the present invention relates to improvements in central processing unit utilisation in a computing system.
- CPU's central processing units
- time slices vary between different operating systems. For example, the time slice on a multi-processor Microsoft WindowsTM system is approximately 15 milliseconds. However, it will be appreciated that the time slice may vary between 15 to 150 milliseconds, depending on specific circumstances.
- the above examples of a time slice length are provided as examples only, and should be construed as illustrative but not restrictive or definitive .
- the instruction cache may be at least partially, if not fully, overwritten. This process uses a significant amount of time. Additionally, the instructions of the originally executing thread must be re-loaded into the instruction cache once it is rescheduled to execute on the same CPU, thereby incurring a significant time penalty.
- the data cache may be partially, if not fully, overwritten.
- the performance penalty is even more significant than in the previous scenario because the data cache cannot be simply overwritten. Rather, any changes made to the data cache must firstly be written back to main memory before any new data can be loaded into the data cache. Thus, a significant time penalty is incurred on "writing back" (the process of transferring data from the date cache into main memory) and subsequently re- loading the data cache.
- the use of multiple threads and/or multiple processes, and in particular, the use of time slicing creates a number of disadvantages in a transaction processing system. Whilst an operating system developer may desire the use of time slicing to ensure that every thread or process is given an equal share of CPU time and to maintain the appearance (to the end user) that many processes are executing simultaneously, the associated overhead created by loading and unloading the data associated with each process results in a perceptible performance degradation.
- the present invention provides a method of scheduling a transaction request to a central processing unit in a computing system, comprising the steps of,
- the computing system may comprise a number of CPU's, all of which may be polled continuously, such that when one of the plurality of CPU's falls below the predetermined threshold, the transaction request is allocated to the one of the plurality of CPU's.
- the predetermined threshold is achieved when the at least one of a plurality of CPU's becomes idle.
- the first is total throughput (i.e. how many transaction requests are processed in a given time)
- response time i.e. how much time is required for a transaction request to be executed
- the response time is not as critical a statistic as the total throughput. It is only necessary to ensure that the response time remains within limits that are considered to be reasonable by an end user. For example, a user will not be able to determine whether the transaction processing system has a response time of, say, 20 milliseconds, or a response time of 100 milliseconds. Although one response time is five times slower than the other, a user is not capable of discerning between the two values .
- An advantage of the present invention preferably resides in the ability of the method to increase the total number of transactions processed within a given time interval by delaying individual transactions, whilst concurrently managing the delay in a manner such that the response time for an individual transaction is not increased to a point where the delay is perceptible to an end user.
- the method comprises the further step of polling at defined time intervals to determine the system load.
- the predetermined time delay is chosen such that an end user cannot determine any perceptible change in response time.
- the predetermined time delay does not exceed 500 milliseconds. It is generally accepted by a person skilled in the art that a transaction response time should be kept below a value of 1000 milliseconds. Therefore, response times of up to 500 milliseconds are generally acceptable to an end user, in most situations.
- the predetermined time delay is in the order of one to fifteen time slices.
- the transaction is delayed by a time period that corresponds to a range between one and fifteen time slices.
- the time slice may be of the order of 15 milliseconds. However, this value may be varied depending on the type of operating system, the type of computer hardware, or any other appropriate consideration.
- the present invention provides a system for scheduling an incoming transaction to a central processing unit in a computing system, the system comprising :
- - polling means arranged to, for a transaction request, poll at least once central processing unit to obtain a value for the central processing unit load,
- - comparison means arranged to, if the current load is below a predetermined threshold, allocate the transaction request to one of the at least one central processing unit,
- the present invention provides a , computer program arranged, when loaded on a computing system, to implement a method in accordance with a first aspect of the invention, or any dependant aspect thereof.
- the present invention provides a computer readable medium providing a computer program in accordance with a third aspect of the invention.
- Figure 1 is a schematic diagram of a system in accordance with an embodiment of the present invention.
- Figure 2 is a flow chart depicting a method in accordance with an embodiment of the present invention.
- An embodiment of the present invention provides a method of improving the performance of transaction processing systems by delaying the processing of a transaction.
- the performance of a transaction processing system is generally determined by the use of two principal performance characteristics or “statistics" . Firstly, performance of a transaction processing system may be measured by determining the number of transactions executed per unit time. Secondly, performance of a transaction processing system may also be measured by determining the time taken by the transaction processing system to "respond" to a transaction processing request. This measure is generally termed the "response time”.
- the number of transactions executed per unit time is a measure of the overall throughput of the transaction processing system.
- the response time is a measure of how responsive the system appears to an end user.
- a typical transaction processing system can process, on average, 100 transactions per second, and may serve, say, 1000 users. If each user makes a transaction request, on average, once every 10 seconds, then the average number of transactions executed per second would be 100.
- the transaction processing system has an average response time of 500 milliseconds, the time taken from when a user submits a transaction request until he or she receives a response indicating success or failure, would be 500 milliseconds .
- the more important statistic when comparing methods for increasing the efficiency of a transaction processing system, is the number of transactions executed per unit time. It is desirable to maximise this value, as the more important parameter in a transaction processing system is the total system throughput, and not the response time for an individual transaction.
- response time remains within limits which are considered to be reasonable by an end user. For example, a user will not be able to discern whether the transaction processing system has a response time of, say, 20 milliseconds, or a response time of 100 milliseconds. Although one response time is five times longer than the other, a user will not be capable of discerning between the two values. In fact, the applicant has discovered that response times of up to 500 milliseconds are generally acceptable to an end user, in most situations. Therefore, a certain amount of response time may be sacrificed in order to increase the average number of transactions executed per unit time, and thereby increase overall throughput.
- One method for effecting this trade off is as follows.
- the number of transactions executed at any given time will vary depending upon user requests.
- the number of requests made by multiple users within a given unit of time is generally referred to as the "load" of the system.
- the load on a transaction processing machine may be relatively light.
- at least one CPU will generally be idle (ie no processes or threads are being executed on the CPU) . In this situation, an incoming transaction is simply scheduled to a thread or process that executes on the idle CPU.
- the incoming transaction is held for a predetermined period of time, to determine whether a CPU will become free within the predetermined period of time. That is, the incoming transaction is put on hold for a number of time slices (for example, in a multi processor window system, it has generally been found that the transaction may be held for up to say, 15 time slices without unduly increasing response time) . In some operating systems, the time slice is 15 milliseconds. However, different operating systems may use different time slices, so the transaction may be held for more or less than 15 time slices, depending on the operating system, the computer hardware, or any other relevant consideration.
- the delay is small enough to be unnoticeable for practical purposes (that is, the end user will not notice the delay) and, in most situations, the delay will actually increase total throughput per unit of time.
- the present invention may be implemented on an appropriate computing system, and, in one embodiment, is incorporated as a software module into an operating system.
- a computing system comprising a server 1, the server 1 being arranged to receive input from an appropriate input device 2.
- the input device 2 may be a remote terminal, connected through an appropriate network 3 , such as the Internet or a proprietary intranet.
- a user 4 may submit a transaction request 5 to the computing system.
- the operating system 6, which resides on the server 1, has incorporated a software module 7 which determines the CPU load on all available CPU's 8a,..., 8n, and then makes a determination as to whether the transaction request 5 should be delayed for a defined period of time.
- the CPU load may be determined by the use of any appropriate hardware monitor or software application.
- the windowsTM operating system contains an application termed "perfmon" which may be used to monitor a large number of performance characteristics, such as CPU load, disk access times, etc.
- Such an application may be - lo used to determine the CPU load for the available CPU' s 8a,...,8n.
- perfmon an application termed "perfmon” which may be used to monitor a large number of performance characteristics, such as CPU load, disk access times, etc.
- Such an application may be - lo used to determine the CPU load for the available CPU' s 8a,...,8n.
- FIG. 2 An embodiment of the methodology employed to determine whether a transaction should be delayed for a defined period of time is shown in figure 2.
- the software module 7 in the operating system 6 determines the load on each CPU 8a,..., 8n in the computing system (10) .
- a CPU has no load (11) (that is, the CPU is idle) , then the transaction is immediately scheduled to the idle CPU (12) . If all CPU's show a load (13), then the transaction request is delayed (14) . If, during the delay, a CPU becomes available (15) , then the transaction is immediately scheduled to the now idle CPU (12) . If the defined period of time elapses and no CPU has become available, then the transaction request will be assigned to a CPU (i.e. placed in the transaction request queue for the CPU) (15) . It will be understood that the CPU may be polled at any appropriate time interval . Generally, the CPU is polled at every time slice, but this may vary according to particular requirements. Such variations are within the purview of a person skilled in the art. Modifications and variations as would be apparent to a skilled addressee are deemed to be within the scope of the present invention.
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002360776A AU2002360776A1 (en) | 2002-12-27 | 2002-12-27 | Streamlining cpu utilisation by delaying transactions |
US10/540,767 US20060123421A1 (en) | 2002-12-27 | 2002-12-27 | Streamlining cpu utilization by delaying transactions |
PCT/US2002/041431 WO2004059465A1 (en) | 2002-12-27 | 2002-12-27 | Streamlining cpu utilisation by delaying transactions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2002/041431 WO2004059465A1 (en) | 2002-12-27 | 2002-12-27 | Streamlining cpu utilisation by delaying transactions |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004059465A1 true WO2004059465A1 (en) | 2004-07-15 |
Family
ID=32679950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/041431 WO2004059465A1 (en) | 2002-12-27 | 2002-12-27 | Streamlining cpu utilisation by delaying transactions |
Country Status (2)
Country | Link |
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AU (1) | AU2002360776A1 (en) |
WO (1) | WO2004059465A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5826081A (en) * | 1996-05-06 | 1998-10-20 | Sun Microsystems, Inc. | Real time thread dispatcher for multiprocessor applications |
US6105053A (en) * | 1995-06-23 | 2000-08-15 | Emc Corporation | Operating system for a non-uniform memory access multiprocessor system |
US6128657A (en) * | 1996-02-14 | 2000-10-03 | Fujitsu Limited | Load sharing system |
US6658449B1 (en) * | 2000-02-17 | 2003-12-02 | International Business Machines Corporation | Apparatus and method for periodic load balancing in a multiple run queue system |
-
2002
- 2002-12-27 AU AU2002360776A patent/AU2002360776A1/en not_active Abandoned
- 2002-12-27 WO PCT/US2002/041431 patent/WO2004059465A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6105053A (en) * | 1995-06-23 | 2000-08-15 | Emc Corporation | Operating system for a non-uniform memory access multiprocessor system |
US6128657A (en) * | 1996-02-14 | 2000-10-03 | Fujitsu Limited | Load sharing system |
US5826081A (en) * | 1996-05-06 | 1998-10-20 | Sun Microsystems, Inc. | Real time thread dispatcher for multiprocessor applications |
US6658449B1 (en) * | 2000-02-17 | 2003-12-02 | International Business Machines Corporation | Apparatus and method for periodic load balancing in a multiple run queue system |
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AU2002360776A1 (en) | 2004-07-22 |
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