WO2004054109A1 - Injection-locked oscillator circuit and a computational unit - Google Patents

Abstract

The invention relates to an injection-locked oscillator circuit and a computational unit. The injection-locked oscillator circuit contains an oscillator sub-circuit comprising an inductance and a capacitance, in addition to an external signal input for the application of the input signal. Said circuit is also equipped with a transistor sub-circuit comprising two cross-connected transistors, said sub-circuit being coupled to the oscillator sub-circuit.

Description

description

Injection-locked oscillator circuit and arithmetic unit

The invention relates to an injection-locked oscillator circuit and a computing unit.

A frequency divider is used for many applications in modern electronics. A frequency divider is a circuit arrangement in which the frequency of an input signal is an integer multiple of a frequency of an output signal.

A frequency divider is included in many frequency synthesizers. A frequency synthesizer is a device that generates a frequency that is phase coherent with a reference frequency, the reference frequency being provided by an internal or external source.

A frequency divider is also often required in a PLL ("phase-locked loop"). A "phase-locked loop", also called tracking synchronization, is an important application in communications and control technology. In particular, the frequency of an oscillator is set so that it matches the frequency or a multiple of a frequency of a reference oscillator.

A flip-flop is often used to form a frequency divider according to the prior art, it being possible for the frequency divider to be broadband. A frequency divider can be designed in CMOS technology or bipolar technology, dynamic or static, cf. [1], [2].

For a very high frequency or very low power consumption, it is often advantageous to use an oscillator instead of a flip-flop, in which an injected input signal is a multiple of an integer (Double, triple, quadruple, ...) or an integer fraction (half, third, quarter, ...) of the frequency of this input signal is adjusted or locked. The physical-technical properties of the partial oscillator circuit (in particular its natural frequency, which depends on the inductance and the capacitance of the oscillator circuit) clearly result in a specific frequency of the signal being forced. The technology in which an oscillator circuit is used in a frequency divider is known as "in-locked-oscillator" technology.

[3] discloses a frequency synthesizer in CMOS technology with an inction-locked frequency divider.

In the following, an injection-locked oscillator circuit 100 (hereinafter also referred to as ILO circuit) is described with reference to FIG. 1, as is known from [1]. An ILO circuit using a shunt coil (shunt coil) is known from [4].

The injection-locked oscillator circuit 100 shown in FIG. 1 has an oscillator sub-circuit 101 and a transistor sub-circuit 102. An input signal Fj is at an input connection 103. _n provided. The input terminal 103 is coupled to the gate terminal 104a of a first n-MOS field effect transistor 104. A first source / drain terminal 104b of the first n-MOS field effect transistor 104 is brought to the electrical ground potential 105. A second source / drain

Terminal 104c of the first n-MOS field-effect transistor 104 is coupled to respective first source / drain terminals 106b, 107b of a second and a third n-MOS field-effect transistor 106, 107. The second and third n-MOS field-effect transistors 106, 107, which are cross-connected to one another, form the transistor subcircuit 102. The gate connection 107a of the third n-MOS field-effect transistor 107 is included a second source / drain terminal 106c of the second n-MOS field effect transistor 106 is coupled. Furthermore, the gate connection 106a of the second n-MOS field-effect transistor 106 is coupled to a second source / drain connection 107c of the third n-MOS field-effect transistor 107. In addition, the second source / drain connections 106c, 107c are coupled to the oscillator subcircuit 101 formed from a capacitance 108 and an inductance 109. The inductance 109 is brought to the potential of the supply voltage 110.

At a first node 111 and to a second node 112 of the oscillator circuit is in each case _in the signal F / 2 on, that is, a signal with a factor of two compared to the signal Fι _n smaller frequency.

In the injection-locked oscillator circuit 100 according to the prior art, an input signal Fι _n with a high input power is required, since this signal at a less sensitive point or node of the circuit, namely the gate connection 104a of the first n- MOS field-effect transistor 104, is coupled ("common mode" point), which transistor 104 has a large parasitic capacitance. Clearly, the input signal must be input before it is coupled into the oscillator circuit 101

Pass through transistor subcircuit 102 and in this way is subject to damping or undesired influencing. In order to have a sufficiently strong signal at the oscillator circuit 101, it is therefore necessary for the input signal F _n to charge or discharge the large input capacitance with a sufficiently high amplitude. However, this requirement is not met in many electronic applications.

A disadvantage of that known from the prior art

Injection-locked oscillator circuit is thus the low signal sensitivity at the point of coupling an input signal (ie at the gate terminal 104a), which requires a large voltage swing of the input signal. A weak signal can therefore often not be processed with sufficient quality. Furthermore, transistor 104 has a high input capacitance. Referring to FIG. 1, this means that the field effect transistor 104 connected as a current source has to be made large. Furthermore, its parasitic capacitance undesirably influences the properties of the oscillator circuit, in particular its resonant frequency.

A synthesizer device is known from [5], which serves to make careful adjustments and stabilization of the operation against the change in the ambient temperature unnecessary.

A dynamic frequency divider circuit is known from [6], which is implemented by means of injection locking of a widely tunable push-pull oscillator.

A clock processing cell is known from [7], which uses an injection-tuned resonance circuit.

The invention is therefore based on the problem of an injection-locked oscillator circuit and one

To provide arithmetic unit which function even with an input signal of a low intensity and with a low input capacity in an error-free and trouble-free manner.

The problem is solved by an injection-locked oscillator circuit and by an arithmetic unit with the features according to the independent claims.

The injection-locked oscillator circuit according to the invention has an oscillator subcircuit with an inductance and with a capacitance. The oscillator subcircuit also has an external signal input for applying the input signal. In addition, in the injection-locked oscillator circuit, a transistor subcircuit with two transistors interconnected in a crosswise manner is provided, which is coupled to the oscillator subcircuit.

The arithmetic unit according to the invention contains at least one Lastel ^'ement, preferably a plurality of load elements, and a clock, which is set up such that a clock signal can be provided with it the at least one load element. Furthermore, the computing unit contains at least one injection-locked-oscillator circuit connected between the clock generator and at least part of the at least one load element with the above-mentioned features.

In the context of this description, an input signal is understood to mean, in particular, a signal which can be provided to the external (“external”, in particular with regard to the circuit formed from the oscillator subcircuit and the transistor subcircuit) signal input of the oscillator subcircuit. In particular in a case in which in front of the external signal input of the oscillator subcircuit (or between one with respect to the injection-locked

Oscillator circuit global signal input and the external signal input of the oscillator subcircuit) one or more additional components (e.g. a coupling transistor or a coupling capacitor) are connected, the signal applied to these components is considered

Feed signal called. Using such components, a feed signal can be influenced, changed, manipulated, converted, transmitted or modified in such a way that the input signal results therefrom. If such components are missing or such components do not modify the feed signal, the feed signal and input signal are identical. An injection-locked oscillator circuit is clearly provided according to the invention, in which an input signal (or a feed signal) is applied to a more sensitive node of the circuit. In other words, the connection at which the input signal can be applied or coupled in is more sensitive with regard to the coupling in of the input signal than in accordance with the prior art. According to the invention, the input signal is coupled to an external signal input (with respect to the circuit formed from the oscillator subcircuit and the transistor circuit) and thus directly into the oscillator subcircuit. In other words, the injection-locked oscillator circuit of the invention is connected in such a way that the oscillator subcircuit (LC tank) receives an input signal directly and while avoiding the

Interposition of the transistor subcircuit between the oscillator subcircuit and the input signal (or feed signal) can be fed. As a result, according to the invention, a large transistor (for example field effect transistor 104 from FIG. 1 according to the prior art) with a large capacitance is unnecessary, which leads to a low sensitivity when coupling in the signal and requires a large input signal amplitude. Furthermore, it is avoided according to the invention that an input signal must pass through transistors of the transistor subcircuit (for example transistors 106, 107 from FIG. 1) before being coupled into the oscillator subcircuit. As a result, the problem that arises in the inction-locked oscillator circuit known from the prior art is avoided that a feed takes place at a connection that is not very sensitive. By using a node with increased sensitivity as a coupling node, the signal can be processed safely and error-free by the injection-locked oscillator circuit of the invention. The sensitivity of the coupling is increased according to the invention in that the signal is made available directly to an external signal input of the oscillator subcircuit. This will achieved a high input sensitivity in combination with a minimal input capacity. In other words, preferably no additional circuit, in particular not the transistor subcircuit serving as a negative ohmic resistance, which is passed through by the signal before being coupled into the oscillator subcircuit, is preferably interposed between a coupling-in node of the external input signal and input node of the oscillator subcircuit get out.

A basic idea of the invention is to choose a more sensitive point for coupling the input signal in order to inject a signal into an oscillator subcircuit with less input power and less input load and to attract it there.

Preferred developments of the invention result from the dependent claims.

The external signal input can be connected to the inductance of the

Oscillator subcircuit can be connected. By coupling the signal directly into the inductance of the oscillator subcircuit, sensitive coupling is achieved while avoiding the interposition of the transistor subcircuit. The external signal input of the inductance is preferably arranged at a partial tap, more preferably at a central tap, of the inductor. This means that the signal is coupled in a central area of the inductance, so that a symmetrical and sensitive coupling is made possible.

According to another development of the invention, the external signal input is connected to one or more connection nodes between the oscillator subcircuit and the transistor subcircuit. This means that the injected signal can be provided directly to the oscillator subcircuit, and that simultaneously Functionality of the transistor subcircuit can be used advantageously as a descriptive negative ohmic resistor to compensate for losses in the oscillator subcircuit. However, in contrast to the prior art, it is avoided that the input signal is subjected to a lossy passage through the channel regions of transistors of the transistor subcircuit with the cross-connected transistors before they are fed into the oscillator subcircuit.

With this type of coupling the input signal into the oscillator subcircuit, at least one coupling transistor can be provided, which is connected in such a way that a source / drain connection of the coupling transistor is coupled to the external signal input and that at the gate Connection of the coupling transistor, a supply signal for generating the input signal can be provided. According to this embodiment, coupling-in transistors with a considerably smaller capacitance and thus size can be used than is the case with the n-MOS field-effect transistor 104 from FIG. 1. The coupling transistor according to the invention can, for example, have a capacitance which is reduced by a factor of ten compared to the current source transistor 104, so that a more sensitive coupling of signals even of a smaller amplitude is made possible. In contrast to the ILO circuit according to FIG. 1, the signal according to this development is not injected at a common mode point of the circuit, but is coupled in synchronously to two oscillator nodes of the partial oscillator circuit. The feed signal is modified by means of a coupling transistor and fed directly into the oscillator subcircuit in a modified manner as an input signal. The coupling transistor can also be set up or connected in such a way that the supply signal is coupled into the oscillator subcircuit in an unchanged manner as an input signal. Alternatively, the injection-locked-oscillator circuit in the configuration with the external signal coupling at one or more connection nodes between the oscillator sub-circuit and the transistor sub-circuit can have at least one coupling-in capacitance, which is connected in such a way that a first coupling-in capacitance - Connection is coupled to the external signal input and that a supply signal for generating the input signal can be provided at a second coupling-in capacitance connection. This embodiment clearly corresponds to a capacitive coupling of the feed signal directly and directly as an input signal into the oscillator subcircuit. By means of a coupling-in capacitance, the feed signal is fed directly into the oscillator subcircuit in a modified or unchanged manner as an input signal.

According to another embodiment of the invention, the oscillator subcircuit and the transistor subcircuit can be connected in parallel to one another between two connection nodes, the input signal being able to be provided to the oscillator subcircuit by means of the external signal input via the connection nodes. This embodiment clearly corresponds to a parallel connection of the capacitance of the oscillator subcircuit, the inductance of the oscillator subcircuit and the transistor subcircuit, which clearly serves as a negative ohmic resistance. With such a parallel connection, it is again possible to couple an input signal into the oscillator subcircuit without the signal first having to pass through transistors of the transistor subcircuit.

According to a preferred embodiment, in the injection-locked-oscillator circuit according to the invention, a switching element connected to the external signal input (ie to the connection nodes) is provided, which is set up so that the input signal can be provided directly to the partial oscillator circuit by means of the switching element. The switching element can be a switching transistor, preferably a switching field-effect transistor, which switching field-effect transistor is connected in such a way that a supply signal can be applied to the gate connection and that the two source / drain connections are connected to the oscillator. Subcircuit are coupled. The input signal is thus provided at at least one of the source / drain connections of the switching transistor. Clearly, a MOS switch with a small gate capacitance can be used to feed the input signal into the LC circuit based on the supply signal.

The switching element can contain a first and a second switching field-effect transistor, which switching field-effect transistors are connected in such a way that the supply signal can be applied to the gate terminal of the first switching field-effect transistor. A feed signal complementary to the feed signal can be applied to the gate connection of the second switching field effect transistor. A first source / drain connection of the first switching field-effect transistor is coupled to a first source / drain connection of the second switching field-effect transistor and to the oscillator subcircuit. Furthermore, a second source / drain connection of the first switching field-effect transistor is coupled to a second source / drain connection of the second switching field-effect transistor and to the oscillator subcircuit. According to this implementation, differential or complementary signals can be injected.

The switching element can also contain a third and a fourth switching field-effect transistor, the third switching field-effect transistor being connected analogously to the first switching field-effect transistor and the fourth switching field-effect transistor being connected analogously to the second switching field-effect transistor. In other words, a switching element implemented as a MOS switch can be implemented as an n-MOS field-effect transistor, p-MOS field-effect transistor or a parallel connection of both. When using only one n-MOS field-effect transistor or only one p-MOS field-effect transistor as a switching element, a single-phase ("single-ended") input signal can be coupled in. In the case of an implementation with an n-MOS field-effect transistor and a p-MOS field-effect transistor, differential, that is to say two mutually complementary input signals or feed signals can be coupled in. Complementary can in particular mean that at a certain point in time one of the input signals has a first electrical potential, whereas at this point in time the other input signal has a second electrical potential which has a lower value than the first electrical potential, or vice versa. Clearly, the same logical value (for example "1" or "0" or "1" or "- 1") can be encoded in both input signals, but the physical electrical potentials of the input signal and the complementary input signal can be different. When using two pairs of switches, i.e. a total of four switching transistors, a fully symmetrical input load is achieved.

The capacitance of the injection-locked oscillator circuit can be a capacitor, but can also have, or alternatively, have, or be formed by, parasitic and / or variable (in particular adjustable) capacitances. The capacitance can also be formed by means of a varactor or have one.

The inductance of the injection-locked oscillator circuit can be a coil, but can also have, or alternatively, variable inductances (for example of supply lines) or be formed by them. The Inductance can be implemented as an integrated component.

The cross-connected transistors of the injection-locked oscillator circuit can be field-effect transistors.

According to an advantageous implementation of the inction-locked oscillator circuit, a first source / drain connection of a first one of the cross-connected ones

Field effect transistors can be coupled to a first source / drain connection of a second of the cross-connected field effect transistors of the transistor subcircuit, and a second source / drain connection of the first field effect transistor can be coupled to a gate connection of the second field effect transistor. A second source / drain connection of the second field effect transistor can be coupled to a gate connection of the first field effect transistor.

To further increase the symmetry of the circuit, an additional transistor subcircuit with two additional transistors interconnected in a crosswise manner can be provided, which is connected to the oscillator subcircuit symmetrically to the transistor subcircuit. Each of the transistor subcircuits clearly represents a negative ohmic resistance, the functionality of which is based on the fact that losses in the oscillator subcircuit are compensated for due to the crosswise connection.

The transistors of the transistor subcircuit are preferably of the n-type and the additional transistors of the additional transistor subcircuit are preferably of the p-type. Alternatively, the transistors of the p-type transistor subcircuit and the additional transistors of the additional transistor subcircuit of the n-conduction type. It is also possible for the transistors of both transistor subcircuits to be of the n-type or of the p-type.

The injection-locked oscillator circuit can be set up in such a way that when the input signal (or a feed signal) of a first frequency is provided, it generates an output signal of a second frequency, the second frequency being 2 ⁿ times the first frequency. Where n is a positive or negative integer or zero. Preferably n is -2, -1, 1 or 2.

In summary, according to the invention, an injection-locked oscillator circuit is provided, which has an LC element as an oscillator sub-circuit, that is to say a sufficiently narrow-band resonance circuit. In addition, a transistor subcircuit with two cross-connected transistors is provided, which functionally represent a negative resistance, by means of which losses of the ohmic resistances in the LC circuit can be compensated. Based on the resonance frequency of the LC element, the interconnection according to the invention has the effect that an output signal with a stabilized frequency can be provided. Due to the coupling of the input signal (or the feed signal) at a sensitive point of the circuit according to the invention, a small voltage swing of an input signal is sufficient. Furthermore, a transistor with an undesirably high capacitance for coupling the input signal is avoided. The increased

The sensitivity of the injection-locked oscillator circuit according to the invention is therefore also based on the fact that the (parasitic) capacitances are reduced. Therefore, a high input sensitivity is combined with a minimal input capacity. Measurements based on a 0.12 μm CMOS process have shown that an input frequency of 43 GHz and more can be achieved with the circuit architecture according to the invention.

For in-phase injection of an input signal, p-MOS transistors with a coupling of a source / drain connection to a supply voltage can be used. Alternatively, n-MOS transistors can be used with a coupling of a source / drain connection to electrical ground potential. Both n-MOS and p-MOS transistors can also be used in the same circuit. The topology of the oscillator can be replaced by any other LC oscillator topography. The use of the circuit is suitable both as

Frequency divider with a halved, quartered, eighth, ... output frequency compared to an input frequency or as a frequency multiplier with a doubled, quadrupled, eightfold, ... output frequency compared to an input frequency.

The in-locked oscillator subcircuit according to the invention is particularly suitable in a computing unit as a component between a load element (memory element, encoder, decoder, etc.) and a global clock generator, i.e. in a clock distribution tree (clock tree).

The computing unit can be designed as a processor. Furthermore, the computing unit in a computer, a

Communication system or be included in a mobile radio system.

In a conventional implementation of a computing unit, at least one amplifier or driver is provided between a respective load element and the clock generator, in order to supply signals from the clock generator before it is coupled into the load elements amplify and thus compensate for losses on a frequently long transport path of the signal.

According to the invention, an injection-locked oscillator circuit of the invention can be connected between the clock generator and at least one of the load elements, the injection-locked oscillator circuit allowing simple and safe refreshing or regeneration of the signals before being coupled into a load element. It is therefore also possible with clock signals of low amplitude and thus with reduced energy consumption to provide the load elements of a computing unit with a reliable and highly precise clock signal. This enables very low-loss operation, and driver circuits or amplifier circuits required according to the prior art are avoided. This is particularly advantageous because supply lines between the clock generator and the load elements of a computing unit are becoming smaller and smaller in size and thus the ohmic resistances and ohmic losses are increasing. The ILO circuit according to the invention can then advantageously be used to couple clock signals into load elements with little loss.

Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

Show it:

FIG. 1 shows an injection-locked oscillator circuit according to the prior art,

FIG. 2 shows an injection-locked oscillator circuit according to a first exemplary embodiment of the invention,

FIG. 3 shows an injection-locked oscillator circuit according to a second exemplary embodiment of the invention, FIG. 4 shows an injection-locked oscillator circuit according to a third exemplary embodiment of the invention,

FIG. 5 shows an injection-locked oscillator circuit according to a fourth exemplary embodiment of the invention,

Figure 6 is an injection-locked oscillator circuit according to ^■ a fifth embodiment of the invention,

FIG. 7 shows an injection-locked oscillator circuit according to a sixth exemplary embodiment of the invention,

FIG. 8 shows an injection-locked oscillator circuit according to a seventh exemplary embodiment of the invention,

FIG. 9 shows an injection-locked oscillator circuit according to an eighth exemplary embodiment of the invention,

Figure 10 is a circuit arrangement in which a plurality of injection-locked oscillator circuits according to the

Invention are interconnected in a clock distribution tree.

The same or similar components in different figures are provided with the same reference numbers.

An injection-locked oscillator circuit 200, hereinafter also referred to as ILO circuit 200, according to a first exemplary embodiment of the invention is described below with reference to FIG.

The ILO circuit 200 contains an oscillator subcircuit 201 as well as a first transistor subcircuit 202 and a second transistor subcircuit 203. The first transistor subcircuit 202 includes a first n-MOS field-effect transistor 204 and a second n-MOS field-effect transistor 205. A first source / drain terminal 204b of the first n-MOS field-effect transistor 204 and a first source / drain Terminal 205b of the second n-MOS field-effect transistor 500 is brought to electrical ground potential 206. The gate terminal 204a of the first n-MOS field-effect transistor 204 is coupled to a second source / drain terminal 205c of the second n-MOS field-effect transistor 205. The gate terminal 205a of the second n-MOS field-effect transistor is coupled to a second source / drain terminal 204c of the first n-MOS field-effect transistor 204. In other words, the n-MOS field-effect transistors 204, 205 of the first transistor subcircuit 202 are cross-connected to one another.

The second transistor subcircuit 203 is composed of the first and second p-MOS field effect transistors 207, 208 which are cross-connected to one another. First source / drain connections 207b, 208b of the p-MOS field effect transistors 207, 208 are at the electrical potential of the supply - Voltage 209. The gate terminal 207a of the first p-MOS field effect transistor 207 is coupled to a second source / drain terminal 208c of the second p-MOS field effect transistor 208. The gate connection 208a of the second p-MOS field effect transistor 208 is coupled to a second source / drain connection 207c of the first p-MOS field effect transistor 207.

It should be noted that in each of the exemplary embodiments described, a current source can optionally be connected to at least one of the reference potentials 206, 209. Furthermore, the oscillator subcircuit 201 is formed from a capacitor 210 (capacitance C) and a coil 211 (inductance L).

A first node 212 is coupled to the second source / drain terminal 204c of the first n-MOS field effect transistor 204. A second node 213 is coupled to the second source / drain terminal 205c of the second n-MOS field effect transistor 205. The first node 212 is coupled to a third node 214, which is coupled to a first connection of the coil 211. The second node 213 is coupled to a fourth node 215, which is coupled to a second connection of the coil 211. Further, ^'a fifth node 216 coupled to a first terminal of the capacitor 210, while a sixth node 217 to a second terminal of the capacitor 210 is coupled. The fifth node 216 is coupled to a seventh node 218, which is coupled to the second source / drain terminal 207c of the first p-MOS field-effect transistor 207. Furthermore, the sixth node 217 is coupled to an eighth node 219, which is coupled to the second source / drain terminal 208c of the second p-MOS field-effect transistor 208.

An input signal or feed signal Fj. _n is directly on the

Coil 211 applied (input signal and feed signal are identical according to the exemplary embodiment of FIG. 2). More precisely, the input signal Fi _{n is} attached to a center tap of the coil 211, that is to say in such a way that there are essentially the same number of coil turns between the third node 214 and the center tap 220 as between the center tap 220 and the fourth node 215. The input signal is clear Fi _n coupled at a very sensitive and symmetrical point of the injection-locked oscillator circuit 200, namely directly at the center of the coil 211 of the oscillator sub-circuit 201. The sensitivity at this point is considerably greater than that Sensitivity when coupling in the manner shown in Fig.l. In particular, in the ILO circuit 200 it is avoided that the input signal Fι _n has to pass through a transistor subcircuit 202 or 203 before being coupled into the oscillator subcircuit 201, so that the input signal Fι _{n is} protected from attenuation or interference by saving this signal path is. Thus, the required input power of the signal _{Fj .n is} significantly reduced in the ILO circuit 200 compared to the ILO circuit 100 according to the prior art, so that the ILO circuit 200 is also suitable for applications in which input signals of low amplitude are provided ,

It should be noted that, due to the functionality of the ILO circuit 200, an output signal Fi _n / 2 is provided at the nodes 214 to 217, that is to say an output signal with a frequency reduced by a factor of two compared to the frequency of the input signal. ^'

An injection-locked oscillator circuit 300 according to a second exemplary embodiment of the invention is described below with reference to FIG.

The ILO circuit 300 includes an oscillator circuit portion 201, which is similar to that in Figure 2 interconnected with the difference that the signal Fι _n of the coil 211 is not provided at the center tap. Instead, the center tap of the coil 211 is brought to the electrical potential of the supply voltage 209.

Furthermore, as in FIG. 2, a transistor subcircuit 202 with cross-connected first and second n-MOS field-effect transistors 204, 205 is provided. A supply signal Fi _{n is} provided to an input terminal 301 for the ILO circuit 300. The connection 301 is connected to the gate connection 302a of a third n-MOS field-effect transistor 302 and to the gate connection 303a a fourth n-MOS field effect transistor 303 coupled. First source / drain connections 302b, 303b of the third and fourth n-MOS field-effect transistors 302, 303 and a first source / drain connection 304b of a fifth n-MOS field-effect transistor 304 are at ground potential 206. A second source / Drain terminal 304c of the fifth n-MOS field-effect transistor 304 is coupled to the first source / drain terminals 204b, 205b of the first and second n-MOS field-effect transistors 204, 205. A second source / drain connection 302c of the third n-MOS field effect transistor 302 is coupled to a first node 305 of the oscillator subcircuit 201. A second source / drain connection 303c of the fourth n-MOS field effect transistor 303 is coupled to a second node 306 of the oscillator subcircuit 201.

In the ILO circuit 300, an input signal of the ILO circuit 300 based on the supply signal Fι _{n is} directly injected onto the oscillator nodes 305, 306 as external signal inputs of the oscillator subcircuit 201. For this purpose, the transistors 302, 303 are used, at whose gate connections 302a, 303a the supply signal is provided. The ILO circuit 300 in turn prevents the input signal at the source / drain connections 302c, 303c from passing through the cross-coupled transistors of the transistor subcircuit before being coupled into the oscillator subcircuit. A particularly sensitive coupling point for the input signal is thus selected in FIG. 3, so that the functionality of the ILO circuit 300 is reliably made possible even with feed signals F _n with a very low amplitude. It should also be noted that the signal Fι _n / 2 is provided at the oscillator nodes 305, 306, that is to say the input signal which is reduced in frequency by a factor of two. According to the 3 are not immediately identical to the feed signal and input signal.

An injection-locked oscillator circuit 400 according to a third exemplary embodiment of the invention is described below with reference to FIG.

The ILO circuit 400 differs from the ILO circuit 300 essentially in that, in addition to the first transistor subcircuit 202, a second one

Transistor subcircuit 203, connected in a manner similar to that shown in FIG. 2, is provided. The transistor circuits 202 and 203 are clearly connected symmetrically with respect to the oscillator subcircuit 201. The supply signal Fi _n is coupled into the ILO circuit 400 in a manner similar to that in FIG. 3 using the third and fourth n-MOS field effect transistors 302, 303, at whose gate connections 302a, 303a the supply signal Fι _{n is} provided. Via the second source / drain connections 302c, 303c of the third and fourth n-MOS field effect transistors 302, 303, the input signal generated from the supply signal is directly, that is, in particular without going through one of the transistor subcircuits 202, 203, into the Components 210, 211 of the oscillator subcircuit 201 are coupled. This in turn enables a more sensitive and less error-prone coupling of the input signal into the oscillator subcircuit 201, so that 400 output signals Fi _n / 2 are generated at halved frequency due to the functionality of the ILO circuit.

It should be noted that in the exemplary embodiments described, the conduction type (n-type or p-type) can be selected as desired from each of the transistors. For example, in FIG. 3, FIG. 4, the n-MOS transistors 302, 303 can alternatively be implemented as p-MOS transistors. An injection-locked oscillator circuit 500 according to a fourth exemplary embodiment of the invention is described below with reference to FIG.

The ILO circuit 500 contains an oscillator subcircuit 201 and a transistor subcircuit 202, which are connected to one another in a manner similar to that shown in FIG. Furthermore, an n-MOS field effect transistor 304 is provided, which is likewise connected to the transistor subcircuit 202 in the manner shown in FIG.

As an alternative to the coupling-in of the feed signal Fi _n shown in FIG. 3 using coupling-in transistors 302, 303, the coupling-in of the feed signal F _{n is} realized in a capacitive manner in the ILO circuit 500. For this purpose, a first coupling capacitor 501 and a second coupling capacitor 502 are provided. The supply signal F _{in is} applied to one connection of the coupling capacitors 501, 502. The other connection of the first coupling capacitor 501 is coupled to the second node 306 of the oscillator subcircuit 201, into which the input signal based on the feed signal F _{n is} thus coupled. Furthermore, the other connection of the second coupling-in capacitor 502 is coupled to the first node 305, so that in this way the input signal based on the supply signal Fi _n is coupled to the first node 305 of the oscillator subcircuit 201. This results in an advantageous coupling, since the input signal can be coupled directly into the oscillator subcircuit 201 so that it is reliable, so that

Output signals Fi _n / 2 are provided with halved frequency.

An injection-locked oscillator circuit 600 according to a fifth exemplary embodiment of the invention is described below with reference to FIG. 6. In the ILO circuit 600, an oscillator subcircuit 201 is again provided, which is formed from a coil 211 and a capacitance 210, which are connected in parallel to one another. 6 also shows a first ohmic resistor 601, which represents the ohmic resistance of the leads to the capacitor 210 and the capacitor 210 itself. In addition, a parasitic second ohmic resistor 602 is shown, which is intended to represent the ohmic resistance of the coil 211 and the associated leads. Signal losses due to these ohmic resistors 601, 602 are clearly supplied by the transistor subcircuit 202 connected in parallel with the oscillator subcircuit 201 with a negative resistor 603. The negative resistor 603 can in turn be realized by means of two cross-connected transistors. An input signal is coupled into the ILO circuit 600 via a switching element 604, which can be configured as a p-MOS transistor or an n-MOS transistor. When using a sufficiently small p-MOS or n-MOS field-effect transistor as the switching element 604, a high input sensitivity is combined with a minimal input capacitance. The switching element 604 is closed or opened by means of the feed signal Fι _n , as a result of which an input signal based on the feed signal is coupled into the oscillator subcircuit 201.

The ILO circuit 600 is further characterized in that the mutually complementary output signals F _out and F _out are provided at first and second output nodes 605, 606. Thus, the ILO circuit 600 is a fully differential circuit arrangement.

An injection-locked oscillator circuit 700 according to a sixth exemplary embodiment of the invention is described below with reference to FIG. The ILO circuit 700 has an oscillator subcircuit 201 and a transistor subcircuit 202, which are connected to one another in a similar manner to the ILO circuit 300 from FIG. 3. However, in the ILO circuit 700, the supply signal F _in and the complementary supply signal F ^ are coupled in using a p-MOS switching transistor 701 and an n-MOS switching transistor 702. To the gate connection 702a of the The n-MOS switching transistor 702 can be supplied with the supply signal F ^, whereas the complementary supply signal F _{ώ can be applied} to the gate terminal 701a of the p-MOS switching transistor 701. Based on the feed signal and the feed signal inverse thereto, an input signal and an input signal complementary thereto are fed into the oscillator subcircuit 201. A first source / drain connection 701b of the p-

MOS switching transistor 701 is connected to a first source

/ Drain terminal 702b of the n-MOS switching transistor 702 is coupled, and the output signal F _{out is} provided at these terminals. In addition, a second source / drain connection 701c of the p-MOS switching transistor 701 and a second source / drain connection 702c of the n-MOS switching transistor 702 are coupled to one another. The inverse output signal F _{out is present} at these connections. The signals F _out and

F _out are complementary to each other. This means that F _{out has} a logic value "1" if and only if F _{out has} the logic value "0" and vice versa.

The transistors 701, 702 form a switching element for coupling the differential input signals, which are generated from the supply signals F ^, F ^, into the oscillator

Subcircuit 201. In other words, the transistors 701, 702 connected according to FIG. 7 form an n-MOS / p-MOS switch.

An injection-locked oscillator circuit 800 according to a seventh exemplary embodiment of the invention is described below with reference to FIG. The ILO circuit 800 clearly represents a circuit combination of the ILO circuits 400 and 700. An oscillator subcircuit 201 and a first and a second transistor subcircuit 202; 203 are interconnected in the manner shown in FIG. 4, with the coupling of a feed signal F _in and a feed signal F ^ complementary thereto being implemented in accordance with the principle shown in FIG. For this purpose, a p-MOS switching transistor 701 and an n-MOS switching transistor 702 are again provided, with the supply signal and the complementary supply signal in each case at one of the gate connections 701a and

702a can be provided. An output signal F _out and an output signal F _out complementary thereto can be generated at two output nodes. An input signal defined by means of the supply signal is thus coupled in again using a MOS switch with a low gate capacitance, so that even an input signal of low amplitude can be safely coupled into the oscillator subcircuit 201. Again, the transistor subcircuits 202, 203 form a negative ohmic resistance to compensate for ohmic losses in particular in the oscillator subcircuit 201.

An injection-locked oscillator circuit 900 according to an eighth exemplary embodiment of the invention is described below with reference to FIG.

The ILO circuit 900 differs from the ILO circuit 700 shown in FIG. 7 in that instead of the switching element formed from two transistors 701, 702 in the ILO circuit 900, a first p-MOS switching transistor 901, a first n-MOS switching transistor 902, a second p-MOS switching transistor 903 and a second n-MOS switching transistor 904 is provided. At the gate terminal 902a of the first n-MOS switching transistor 902 and at the gate terminal 903a of the The second p-MOS switching transistor 903, the supply signal F ^ is provided. At the gate terminal 901a of the first p-MOS switching transistor 901 and at the gate terminal 904a of the second n-MOS switching transistor 904, a complementary supply signal F ^ is provided. First source

/ Drain connections 901b, 902b of the first p-MOS switching transistor 901 and the first n-MOS switching transistor 902 are coupled to one another. Furthermore, second source / drain connections 901c, 902c of the first p-MOS switching transistor 901 and the first n-MOS switching transistor 902 are coupled. First source / drain connections 903b, 904b of the second p-MOS switching transistor 903 and the second n-MOS switching transistor 904 are coupled to one another. In addition, second source / drain connections 903c, 904c of the second p-MOS switching transistor 903 and the second n-MOS switching transistor 904 are coupled to one another.

The interconnection of the oscillator subcircuit 201 and the transistor subcircuit 202 is implemented in the same way as in FIG. 7. The ILO circuit 900 uses a fully balanced switch with two pairs of switches, which achieves a fully balanced input load. With the same dimensioning of the LC circuit, the ILO circuit 900 synchronizes an input signal such that the frequency of the output signal F _{out is} equal to the frequency of the input signal and not, as in the exemplary embodiments described above, equal to half the frequency of the input signal.

Of course, in particular the exemplary embodiments shown in FIGS. 2 to 9 can be modified in such a way that n-MOS transistors are replaced by p-MOS transistors and the circuitry is adapted accordingly. In particular, in-phase injection can be carried out using p-MOS transistors which are connected to a supply voltage instead of n-MOS transistors which are connected to a ground potential are realized. N-MOS transistors or p-MOS transistors can also be used simultaneously in each of the circuits.

It should be noted that, as an alternative to the exemplary embodiment shown in FIG. 9, the switching transistors 901 to 904 can all be designed as p-MOS transistors or all as n-MOS transistors.

Furthermore, the realization of the oscillator subcircuit can be replaced by any other oscillator topology, in deviation from the exemplary embodiments shown in FIG. 2 to FIG. For example, several coils and / or several capacitors can be used, and these can be connected in parallel and / or in series in any way.

A circuit arrangement 1000 is described below with reference to FIG. 10, in which a plurality of injection-locked oscillator circuits 1003 according to the invention are advantageously connected in a clock distribution tree.

The circuit arrangement 1000 has a clock generator 1001 for providing a clock signal from a common one

Clock frequency to a plurality of load elements 1002. The load elements 1002 are coupled to the clock generator 1001 by means of electrically conductive feed lines 1004. Between each of the load elements 1002 and the clock generator 1001, an injection-locked

Oscillator circuit 1003 (e.g. one of the ILO circuits shown in Fig. 2 to Fig. 9).

Deviating from the configuration shown in FIG. 10, it is also possible for part of the loads 1002 and the clock

1001 no injection-locked-oscillator circuit. Alternatively, multiple injection-locked Oscillator circuits can be connected between a load element 1002 and the clock generator 1001. Further alternatively, additional drivers (amplifiers) can optionally be connected between individual load elements and the clock generator 1001. It is also possible, in addition to the injection-locked

Switch oscillator circuits 1003 between clock generator 1001 and load elements 1002 central or decentralized drivers (e.g. amplifiers).

In circuit arrangement 1000, most of them are

Load elements 1002 are set up in such a way that they require a clock signal of frequency f of clock generator 1001 to fulfill their functionality. However, a first load element 1002a is provided, which requires a frequency which is double in relation to the frequency of the signal of the clock generator 1001. In order to provide such a frequency, a first injection-locked oscillator circuit 1003a is implemented between the first load element 1002a and the clock generator 1001 in such a way that the latter doubles the frequency of the clock generator 1001 and provides a signal with this doubled frequency to the first load element 1002a. Furthermore, a second load element 1002b is provided, which is operated at a quarter of the frequency of the signal of the clock generator 1001. A second injection-locked oscillator circuit 1003b is therefore set up between the clock generator 1001 and the second load element 1002b in such a way that it converts the frequency of the signal from the clock generator 1001 into a frequency of a signal which is reduced by a factor of four and which the second load element 1003b provided. The following publications are cited in this document:

[1] Pfaff, D, Huang, Q (1999) "A quarter-micron CMOS, 1 GHz VCO / prescaler-set for very low power applications", Custom Integrated Circuits, p.649-652

[2] Yuan, J, Svensson, C (1989) "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, pp.62-70

[3] Rategh, HR et al. (2000) "A CMOS frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver", IEEE Journal of solid-state Circuits, Vol. 35, No. 5, pp.780-787

[4] Wu, H, Haji iri, A (2001) "A 19 GHz 0.5mW 0.35μm CMOS frequency divider with shunt-peaking locking-range enhancement", Digist of Technical Papers, ISSCC 2001, p.412f, 471

[5] JP 62 047 212

[6] Madden, CJ et al. (1996) "A novel 75 GHz InP HEMT Dynamic Divider", In: ^ Gallium Arsenide Integrated Circuit Symposium, Orlando / Fl / USA, Nov. 3-6, 1996, Technical

Digest 1996, pp. 137-140

[7] US 6,317,008 LIST OF REFERENCE NUMBERS

100 injection-locked oscillator circuit

101 Oscillator subcircuit

102 transistor subcircuit

103 Input connection

104 first n-MOS field effect transistor 104a gate connection

104b first source / drain connection 104c second source / drain connection

105 ground potential

106 second n-MOS field-effect transistor 106a gate connection

106b first source / drain connection 106c second source / drain connection

107 third n-MOS field effect transistor 107a gate connection

107b first source / drain connection 107c second source / drain connection

108 capacity

109 inductance

110 supply voltage

111 first knot

112 second knot

200 injection-locked oscillator circuit

201 oscillator subcircuit

202 first transistor subcircuit

203 second transistor subcircuit

204 first n-MOS field-effect transistor 204a gate connection

204b first source / drain connection 204c second source / drain connection

205 second n-MOS field-effect transistor 205a gate connection

205b first source / drain connection 205c second source / drain connection

206 ground potential

207 first p-MOS field effect transistor 207a gate connection

207b first source / drain connection 207c second source / drain connection

208 second p-MOS field effect transistor 208a gate connection

208b first source / drain connection 208c second source / drain connection

209 supply voltage

210 capacitor

211 coil

212 first knot

213 second knot

214 third knot

215 fourth knot

216 fifth knot

217 sixth knot

218 seventh knot

219 eighth knot

220 center tap

300 injection-locked oscillator circuit 301 input connector

302 third n-MOS field effect transistor 302a gate connection

302b first source / drain connection 302c second source / drain connection

303 fourth n-MOS field-effect transistor 303a gate connection

303b first source / drain connection 303c second source / drain connection 304 fourth n-MOS field-effect transistor 304a gate connection 304b first source / drain connection 304c second source / drain connection

305 first knot

306 second knot

400 injection-locked oscillator circuit

500 injection-locked oscillator circuit

501 first coupling capacitor

502 second coupling capacitor

600 injection-locked oscillator circuit

601 first ohmic resistance

602 second ohmic resistance

603 negative resistance

604 switching element

605 first output node

606 second output node

700 injection-locked oscillator circuit

701 p-MOS switching transistor 701a gate connection

701b first source / drain connection 701c second source / drain connection

702 n-MOS switching transistor 702a gate connection

702b first source / drain connection

702c second source / drain connection

800 injection-locked oscillator circuit

900 injection locked oscillator circuit

901 first p-MOS switching transistor 901a gate connection

901b first source / drain connection 901c second source / drain connection

902 first n-MOS switching transistor 902a gate connection

902b first source / drain connection 902c second source / drain connection

903 second p-MOS switching transistor 903a gate connection 903b first source / drain connection 903c second source / drain connection 904 second n-MOS switching transistor 904a gate connection 904b first source / drain connection 904c second source / drain connection

1000 circuit arrangement

1001 clock

1002 load elements 1002a first load element 1002b second load element

1003 Injection-Locked-Oscillator-Circuit 1003a first Injection-Locked-Oscillator-Circuit 1003b second Injection-Locked-Oscillator-Circuit

1004 supply lines

Claims

claims: 1. Injection-locked oscillator circuit • with an oscillator subcircuit with o an inductance and with a capacitance; o an external signal input for applying the input signal; With a transistor subcircuit with two cross-connected transistors, which is coupled to the oscillator subcircuit, • in which the input signal can be provided by means of a switching element connected in parallel with the oscillator subcircuit. 2. Injection-locked oscillator circuit according to claim 1, wherein the switching element is connected to the external signal input switching element, and is set up in such a way that by means of the switching element the oscillator sub-circuit a supply signal for generating the input signal is available. 3. Injection-locked oscillator circuit according to claim 2, wherein the switching element is a switching field effect transistor, which switching field effect transistor is connected such that • the feed signal can be applied to the gate connection; • The two source / drain connections are coupled to the oscillator subcircuit. 4. Injection-locked oscillator circuit according to claim 2, wherein the switching element contains a first and a second switching field-effect transistor, which switching field-effect transistors are connected in such a way that • The feed signal can be applied to the gate connection of the first switching field-effect transistor; At the gate terminal of the second switching field-effect transistor to the supply signal complementary feed signal can be applied; a first source / drain connection of the first switching field effect transistor is coupled to a first source / drain connection of the second switching field effect transistor and to the oscillator subcircuit; a second source / drain connection of the first switching field effect transistor is coupled to a second source / drain connection of the second switching field effect transistor and to the oscillator subcircuit. 5. Injection-locked oscillator circuit according to claim 4, wherein the switching element further includes a third and a fourth switching field effect transistor, the third switching field effect transistor analogous to the first switching field effect transistor and wherein the fourth switching field effect transistor analogous to how the second switching field-effect transistor is connected. 6. In ection-locked oscillator circuit according to one of claims 1 to 5, wherein the capacitance is a capacitor. 7. Injection-locked oscillator circuit according to one of claims 1 to 6, wherein the inductance is a coil. 8. Injection-locked oscillator circuit according to one of claims 1 to 7, in which the cross-connected transistors are field effect transistors. 9. injection-locked-oscillator circuit according to claim 8, wherein a first source / drain connection of a first of the cross-connected field effect transistors is coupled to a first source / drain connection of a second of the cross-connected field effect transistors of the transistor subcircuit , a second source / drain Connection of the first field effect transistor is coupled to a gate connection of the second field effect transistor and a second source / drain connection of the second field effect transistor is coupled to a gate connection of the first field effect transistor. 10. Injection-locked oscillator circuit according to one of claims 1 to 9, with an additional transistor sub-circuit with two additional interconnected crosswise Transistors, which is connected to the oscillator subcircuit symmetrically to the transistor subcircuit. 11. Injection-locked oscillator circuit according to claim 10, wherein the transistors of the transistor subcircuit of the n-type and the additional transistors of the additional transistor subcircuit of the p-type are or in which the transistors of the transistor subcircuit of the p -Conduction type and the additional transistors of the additional transistor subcircuit of the n-conductivity type. 12. Injection-locked oscillator circuit according to one of claims 1 to 11, which is set up in such a way that it generates an output signal of a second frequency when the input signal of a first frequency is provided, the second frequency being 2 ⁿ times the first frequency and where n is a positive or negative integer or zero. 13. Injection-locked oscillator circuit according to claim 12, wherein n is -2, -1, 1 or 2. 14. Computing unit • with at least one load element; • with a clock that is set up in such a way that with it a clock signal can be provided to the at least one load element; with at least one injection-locked oscillator circuit connected between the clock generator and at least part of the at least one load element according to one of claims 1 to 13.