WO2004049557A2

WO2004049557A2 - High-speed class-ab transconductance stage

Info

Publication number: WO2004049557A2
Application number: PCT/IB2003/005299
Authority: WO
Inventors: Mike H. Splithof; Paulus P. F. M. Bruin
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2002-11-28
Filing date: 2003-11-20
Publication date: 2004-06-10
Anticipated expiration: 2005-05-28
Also published as: WO2004049557A3; AU2003280113A1

Abstract

A transconductance stage comprises a first transistor wherein a base terminal of the first transistor is a first input terminal; a collector terminal of the first transistor is a first output terminal; a first operational amplifier is connected by its output to an emitter terminal of the first transistor and to its own inverting input terminal; an input voltage source is connected by one terminal to the base terminal of the first transistor and by another terminal to ground; and a reference voltage source is connected by one terminal to a non-inverting input terminal of the first operational amplifier and by another terminal to ground.

Description

High-speed class- AB transconductance stage

The present invention relates to a high-speed class-AB transconductance stage. In a transconductance stage of class AB the maximum signal output current is larger than the quiescent current. Fig. 1 shows a differential voltage source 2 providing a voltage Nid connected by its plus terminal to a base terminal of a transistor 4. An emitter terminal of the transistor 4 is connected to ground. A collector terminal of the transistor 4 is an output terminal of the current II. A minus terminal of the differential voltage source 2 is connected to a base terminal of a transistor 6. An emitter terminal of the transistor 6 is connected to ground. A collector terminal of the transistor 6 is an output terminal of a current 12. The differential output current Iod is equal to 11-12. The two transistors 4 and 6 are in common emitter configuration. This is almost similar to the well-known differential amplifier, which comprises two common emitter transistors in anti-series connection. A differential voltage Vid at the base terminals of the transistors 4 and 6 will result in a differential collector current Iod at the output terminals. A low quiescent current does not limit the maximum output current. The common mode rejection is roughly zero. Fig. 2 shows a known implementation of a class-AB transconductance stage, see also C. Toumazou et al., "Analog IC design, the current mode approach", ISBN 0 86341 215 7, pp. 215-221,1990. It shows a circuit comprising a differential voltage source 22 connected by its minus terminal to a base terminal of a transistor 16 and connected by its plus terminal to a base terminal of a transistor 24. A collector of the transistor 24 is connected to a supply voltage Ncc. An emitter of the transistor 24 is connected to an emitter of transistor 25. A collector of the transistor 25 is connected to a current source 26 and to a base terminal of the transistor 25. The current source 26 is connected by its other terminal to ground. The current source 26 provides a current of 10/2. The base terminal of transistor 25 is connected to a base terminal of a transistor 8. A collector of the transistor 8 is an output terminal for a current 12'. An emitter terminal of the transistor 8 is connected to an emitter terminal of transistor 12. A base terminal of a transistor 10 is connected to the base terminal of the transistor 24. A collector terminal of the transistor 10 is an output terminal of a current II. An emitter terminal of the transistor 10 is connected to an emitter terminal of a transistor 14. A collector terminal of the transistor 14 is an output terminal of a current II'. A base terminal of the transistor 14 is connected to a base terminal of a transistor 18. The base terminal of the transistor 18 is connected to a collector terminal of the transistor 18 and to a current source 20. The other terminal of the current source 20 is connected to ground. The current source 20 provides a current of 10/2. An emitter terminal of the transistor 18 is connected to an emitter terminal of a transistor 16. A collector terminal of the transistor 12 is an output terminal of the current 12. A base terminal of the transistor 12 is connected to a base terminal of the transistor 16. A collector terminal of the transistor 16 is connected to a supply voltage Vcc. The differential output current Iod is equal to 11-12. The inverted output current Iod' is equal to Il'-I2'. A disadvantage of this circuit is the use of p-type transistors as amplifying devices. This will limit the achievable bandwidth, because p-type transistors are typically slower than n-type transistors in a given IC-process. Moreover, the transconductance of this stage will be limited because the n-type transistors are degenerated by the emitter resistance of the p-type transistors. A further known implementation of a class-AB transconductance stage is known from R. Harjani et al., "An Integrated Low- Voltage Class AB CMOS OTA", IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 134-141, February 1999. Further known implementations of class-A transconductance stages, where the maximum output current is limited by the quiescent current, are known from R. J. van de Plassche, "A Wide-Band Operational Amplifier...", IEEE J. Solid-State Circuits, vol. SC-6, pp. 347-352, December 1971; R.J. van de Plassche, "A Wide-Band Monolithic Instrumentation Amplifier", IEEE J. Solid-State Circuits, vol. SC-10, pp. 424-431, December 1975."

US 6,414,552 Bl discloses a non-linear current mirror. The non-linear current mirror is particularly useful in the output stage of an operational transconductance amplifier for improving slew rate and stability while maintaining low bias current. The non-linear current mirror circuit comprises a first MOS transistor whose gate and drain are coupled together and are further coupled to a first current input. A second MOS transistor has its gate coupled to the first MOS transistor gate, and its drain is coupled to a second current input. A third MOS transistor has its drain coupled to the second MOS transistor source, and its gate is coupled to the second MOS transistor drain. A fourth MOS transistor has its gate coupled to the third MOS transistor gate. The source Ls is coupled to the first MOS transistor source and the third MOS transistor source. Finally, the drain forms a current output. US 5,103,188 discloses an electrical circuit for amplifying complex, wideband signals, preferably audio and servo/robotic signals, comprising a first input buffer in an emitter-follower configuration or in a source-follower configuration. A bias current rail traverses the first buffer. The low-impedance output of the first buffer is connected to a load resistor, preferably in the order of 50-500 ohms. The circuit further comprises positive and negative opposing current mirrors connected to the bias current rail that reflect the currents created in the bias current rail by an input voltage signal imposed across the load resistor. The combined outputs of the current mirrors are connected to the input of a second buffer. The output of the second buffer is connected via a feedback means to the output of the first buffer and to a load. The first buffer is driven by dual voltage supply rails, preferably a lower voltage, of the order of 15 Volts. Higher dual voltage supply rails for the second buffer and the opposing current mirrors, typically at least 50 to 70 Volts, are used for power amplifiers. The present invention provides an amplifier which can amplify complex, high-speed, wideband signals without slew rate, overshoot, or ringing arid still maintain a large degree of linearity with increasing input overdrive. It is capable of unprecedented high-frequency response and phase stability without any need for typical compensation techniques.

The aim of US 5103188 is to provide a voltage-to-current stage with a linear transconductance for a wide range of input signal amplitudes. The idea works if the output impedance of the buffer is small compared with a resistor of the circuit. This implies that, for a given bias current, a lot of energy is lost in just making a low output impedance, and linearization is achieved by degeneration with the same resistor. Second, the input buffer has two in-phase current outputs with opposite directions. This has been implemented by using complementary transistors.

US 6,188,281 discloses a class-AB transconductance amplifier with bandwidth not limited by slew rate. This patent, like US2001/0038312, relates to the linearization of class AB-transconductance stages. It teaches connecting one or more stages with a concave behavior in parallel, to compensate for the convex behavior of the class-AB stage. This can be seen in Fig. 6 of US 6,188,281. In Fig. 7 of US 6,188,281 it is shown how the combined transconductance functions lead to a more linear overall behavior (Fig. 7c). The class-AB circuit shown in Fig. 2 of US 6,188,281 uses voltage followers, and it uses p-type transistors as active amplifiers. The compensation circuit is a simple class-A differential pair or a combination of more than one of these. In class AB circuits, the maximum signal output current is larger than the quiescent current. It is an object of the present invention to provide a high-speed class-AB transconductance stage which has a high common mode rejection, and yet the maximum output current is not fixed by the circuit itself or by its quiescent current. To achieve the object of the present invention, a high-speed class-AB transconductance stage is disclosed comprising a first transistor wherein a base terminal of the first transistor is a first input terminal; a collector terminal of the first transistor is a first output terminal; a first operational amplifier is connected by its output to an emitter terminal of the first transistor and to its own inverting input terminal; an input voltage source is connected by one terminal to the base terminal of the first transistor and by another terminal to ground; and a reference voltage source is connected by one terminal to a non-inverting input terminal of the first operational amplifier and by another terminal to ground. It is an advantage of the present invention that the proposed transconductance stage has a high common mode rejection and the maximum of 11-12 is not fixed by the circuit itself or by its quiescent current.

According to a preferred embodiment of the invention, the first operational amplifier comprises an input transistor wherein a base terminal of the input transistor is a non-inverting input terminal; an emitter terminal of the input transistor is an inverting input terminal; a folded cascode transistor is connected by its emitter terminal to the collector terminal of the input transistor; the base terminal of the folded cascode transistor is connected to the inverting input terminal; a first current source is connected to the collector terminal of the input transistor and the emitter terminal of the folded cascode transistor; a second current source is connected to the collector terminal of the folded cascode transistor; an output transistor is connected by its base terminal to the collector terminal of the folded cascode transistor and to the second current source; the emitter terminal of the output transistor is connected to ground; and the collector terminal of the output transistor is the output terminal of the operational amplifier. It is an advantage of this embodiment that a high speed class-AB transconductance stage with improved high-speed performance is provided.

According to a preferred embodiment of the invention, the first transistor of the transconductance stage, the input transistor of the operational amplifier, and the output transistor of the operational amplifier are of the fastest type in a given IC process, and the folded cascode transistor of the operational amplifier is of the complementary type. An advantageous feature is that only three transistors are used to form the required operational amplifier. The input transistor of the operational amplifier combines a differential input and an offset voltage of one base-emitter voltage. One folded cascode transistor is needed to convey the current of the input transistor to another voltage level, and finally only one output transistor is needed because the operational amplifier only needs to perform a current-sinking action. According to a preferred embodiment of the invention, the first operational amplifier operates at least as fast as the first transistor.

According to a preferred embodiment of the invention, the output of the first operational amplifier can sink a large current.

According to a preferred embodiment of the invention, any transistor can be a bipolar transistor or a field effect transistor.

According to a preferred embodiment of the invention, the input signal is a voltage.

According to a preferred embodiment of the invention, the output signal is a current. According to a preferred embodiment of the invention, the current sources of the operational amplifier define the quiescent current of the transconductance stage.

To achieve the object of the present invention, a transconductance stage is disclosed comprising a first transistor and a second transistor wherein a base terminal of the first transistor is a first input terminal; a base terminal of the second transistor is a second input terminal; a collector terminal of the first transistor is a first output terminal; a collector terminal of the second transistor is a second output terminal; a first operational amplifier is connected by its output terminal to an emitter terminal of the first transistor and to its own inverting terminal; a second operational amplifier is connected by its output to an emitter terminal of the second transistor and to its own inverting terminal; a differential voltage source is connected by one terminal to the base terminal of the first transistor and by another terminal to the base terminal of the second transistor; a common mode voltage source is connected by one terminal to one base terminal of the first or second transistor and by another terminal to ground; a first base emitter voltage source is connected by one side to the base terminal of the first transistor and by another side to a non-inverting terminal of the second operational amplifier; and a second base emitter voltage source is connected by one side to the base terminal of the second transistor and by another side to a non-inverting terminal of the first operational amplifier. The advantageous feature of the present invention is that the circuit thus provided has a high common mode rejection and yet the maximum of the absolute value of 11-12 is not fixed by the circuit itself or by its quiescent current. Furthermore, the provided circuit has a differential input and a differential output signal.

According to a preferred embodiment of the invention, the first and second operational amplifiers including the first and second base emitter voltage source comprise an input transistor wherein a base terminal of the input transistor is a non-inverting input terminal; an emitter terminal of the input transistor is an inverting input terminal; a folded cascode transistor is connected by its emitter terminal to the collector terminal of the input transistor; the base terminal of the folded cascode transistor is connected to the inverting input terminal; a first current source is connected to the collector terminal of the input transistor and the emitter terminal of the folded cascode transistor; a second current source is connected to the collector terminal of the folded cascode transistor; an output transistor is connected by its base terminal to the collector terminal of the folded cascode transistor and to the second current source; the emitter terminal of the output transistor is connected to ground; and the collector terminal of the output transistor is the output terminal of the operational amplifier. It is an advantage of this embodiment that a high-speed class-AB transconductance stage with improved high-speed performance is provided.

According to a preferred embodiment of the invention, the first and second transistors of the transconductance stage, the input transistors of the first and second operational amplifier and the output transistors of the first and second operational amplifier are of the fastest type in a given IC process, and the folded cascode transistor of the first and second operational amplifier is of the complementary type. An advantageous feature is that only three transistors are used to form the required operational amplifier including one base emitter voltage source. The input transistor of the operational amplifier combines a differential input and an offset voltage of one base emitter voltage. One folded cascode transistor is needed to convey the current of the input transistor to another voltage level and finally only one output transistor is needed because the operational amplifier only needs to perform a current-sinking action.

According to a preferred embodiment of the invention, a transistor used in folded cascode configuration is a current conveyor, conveying a current in a branch to the same current in another branch at a different voltage.

According to a preferred embodiment of the invention, an input signal is applied between the first and the second input terminal as a differential signal. It is an advantageous feature of the present invention that a differential signal is used. Differential signals can be robust to common mode disturbances.

According to a preferred embodiment of the invention, an output signal is provided as a differential signal between the first and the second output terminal as a differential signal. It is an advantageous feature of the present invention that the output signal is a differential signal. Differential signals can be robust to common mode disturbances.

According to a preferred embodiment of the invention, the input signal is a differential voltage.

According to a preferred embodiment of the invention, the output signal is a differential current.

According to a preferred embodiment of the invention, the first and second current sources in the operational amplifiers define the quiescent current of the transconductance stage.

According to a preferred embodiment of the invention, active devices of low speed are used in unity gain configuration only.

According to a preferred embodiment of the invention, the first and second operational amplifiers operate at least as fast as the first and second transistors. It is an advantageous feature of the present invention that this circuit can be used at high frequencies because the operational amplifiers work as fast as the transistors which perform a voltage-to- current transfer.

According to a preferred embodiment of the invention, the output of the first and second operational amplifiers sinks large currents.

These and various other advantages and features of novelty which characterize the present invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better imderstanding of the invention, its advantages, and the object obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter in which preferred embodiments of the present invention are illustrated and described.

Fig. 1 shows two common emitter stages;

Fig. 2 shows a known implementation of a class-AB transconductance stage; Fig. 3 shows a cross-coupled common emitter stage according to the present invention; Fig. 4 shows a proposed realization of the operational amplifier according to the present invention; and

Fig. 5 shows a single-ended version of Fig. 4.

Fig. 3 shows a cross-coupled common emitter stage. The stage comprises a differential voltage source 28. A plus terminal of the differential voltage source 28 is connected to a base terminal of a transistor 30. A collector terminal of the transistor 30 is an output terminal of a current II. An emitter terminal of the transistor 30 is connected to an output terminal of the operational amplifier 36. The base terminal of the transistor 30 is connected to a plus terminal of a base emitter voltage source 32. A minus terminal of the base emitter voltage source 32 is connected to a plus terminal of an operational amplifier 34. A minus terminal of the operational amplifier 34 is connected to an output terminal of the operational amplifier 34. The output terminal of the operational amplifier 34 is connected to an emitter terminal of a transistor 40. The output terminal of the operational amplifier 36 is connected to a minus terminal of the operational amplifier 36. A plus terminal of the operational amplifier 36 is connected to a minus terminal of a base emitter voltage source 38. A plus terminal of the base emitter voltage source 38 is connected to a base terminal of the transistor 40 and to a minus terminal of the differential voltage source 28. A collector terminal of the transistor 40 is an output terminal of a current 12.

An input variable is a differential voltage Vid serving as a differential input voltage and applied between the base terminals of the transistors 30 and 40. An output variable is Iod, a differential output current which is equal to 11-12. A common mode voltage source Vic is connected between the base of transistor 40 and ground (not shown). Both operational amplifiers 34 and 36 have unity feedback, the output is connected to the inverting input. This gives the operational amplifiers 34 and 36 voltage follower behavior and a high bandwidth.

To understand the circuit in Fig. 3, suppose that Vic increases by a certain amount. Through the operational amplifier 36, the emitter of transistor 30 will follow the increase in Vic. Since the base of transistor 30 is also connected to Vic (through Vid 28), the base voltage increases by the same amount, so no difference occurs in II due to the change in Vic. In a similar way, the emitter of the transistor 40 also follows the increase in Vic, and 12 is not changed by Vic either. This means that this cross-coupling trick renders the circuit insensitive to common mode voltage variations. As the transistors 30 and 40 are still connected in common emitter configuration, the maximum of the absolute value of 11-12 is still not limited by the quiescent current. The quiescent current is defined by the voltage sources 32 and 38.

The implementation of the operational amplifiers 34 and 36 will be discussed in the following text. First, it is necessary that the operational amplifiers 34 and 36 can sink large currents because both II and 12 are flowing into the outputs of the operational amplifiers 34 and 36. Second, in order not to harm the Vid to Iod transfer (transconductance) at high frequencies, the operational amplifiers 34 and 36 must be able to operate as fast as the transistors 30 and 40. The transistors 30 and 40 are referred to as transconductance transistors because these transistors actually perform the voltage-to-current conversion. The above- mentioned conditions are again fulfilled because the output stage of the operational amplifier 34 and 36 is made with a common emitter stage.

Fig. 4 shows the transductance stage of Fig. 3 with a practical implementation of the operational amplifiers. Fig. 4 comprises a differential voltage source 42 connected by its plus terminal to a base terminal of a transistor 44. The base terminal of the transistor 44 is connected to a base terminal of a transistor 60. A collector terminal of the transistor 44 is an output terminal of a current II. An emitter terminal of the transistor 44 is connected to a base terminal of a transistor 50, to an emitter terminal of a transistor 54, and to a collector terminal of a transistor 46. An emitter terminal of transistor 46 is connected to ground. A base terminal of transistor 46 is connected to a current source 48. The other side of the current source 48 is connected to ground. The current source 48 provides a current of 10/2. The base terminal of transistor 46 is also connected to a collector terminal of transistor 50. An emitter terminal of transistor 50 is connected to a current source 52 and to a collector terminal of transistor 54. The current source 52 is connected by its other side to a supply voltage terminal Vcc 56 and to a current source 58. The current sources 52 and 58 each provide a current of 10. A base terminal of transistor 54 is connected to a base terminal of a transistor 68. A collector terminal of the transistor 60 is connected to the current source 58. The current source 58 is connected to an emitter terminal of a transistor 62. A base terminal of transistor 62 is connected to an emitter terminal of transistor 60 and to an emitter terminal of transistor 68. A collector terminal of transistor 62 is connected to a current source 64. The other side of the current source 64 is connected to ground. The current source 64 provides a current of 10/2. The emitter of the transistor 68 is connected to a collector terminal of a transistor 66. A base terminal of transistor 66 is connected to a collector terminal of transistor 62. An emitter terminal of transistor 66 is connected to ground. A collector terminal of transistor 68 is an output terminal of a current 12. A base terminal of transistor 68 is connected to a minus terminal of the differential voltage source 42 providing a voltage Vid. Vid is the input variable as a differential input voltage, applied between the base terminals of the transistors 44 and 68. Iod is the output variable as a differential output current equal to 11-12. In the following the operation of the operational amplifiers will be explained.

Assume no base currents and that Vid is equal to zero. The collector of transistor 46 is the output of the operational amplifier 36. The base of transistor 54 is the non-inverting input of the operational amplifier 36 and the emitter of the transistor 54 is the inverting input terminal of the operational amplifier 36. Since the collector of the transistor 46 is connected to the emitter of the transistor 54, unity feedback is achieved.

Transistor 50 is a pnp transistor in common base configuration (folded cascode). Since the common base configuration has inherent unity feedback, the emitter current of the pnp transistor 50 will be conveyed to the collector up to the transit frequency of the pnp transistor. The transit frequency is the frequency at which the current amplification has been reduced to exactly one. This is an important indicator of the transistor's performance with respect to speed and is mostly noted as fT.

Transistor 50 is biased at a current 10/2, which is defined by a current source between the collector of transistor 50 and ground. Transistor 54 is biased at a current of 10/2 which is 10 minus the emitter current of transistor 50, which results in a base emitter voltage between the non-inverting terminal and the inverting input terminal of the operational amplifier 36. The transistor 44 will have the same base emitter voltage as transistor 54, since Vid is zero and will also carry a current 10/2 if transistor 44 and transistor 54 are matched devices. Transistor 46 will carry 10, which is the sum of the emitter currents of transistor 44 and transistor 54. Of course, the current distribution in the individual branches may alternatively be chosen differently.

Fig. 5 shows a single-ended version of Fig. 4. Fig. 5 comprises an input voltage source 70 providing a voltage Vin connected by its minus terminal to ground and by its plus terminal to a base terminal of a transistor 72. A collector terminal of transistor 72 is an output terminal of a current II. An emitter terminal of the transistor 72 is connected to a collector terminal of a transistor 74 and to a base terminal of a transistor 80. An emitter terminal of the transistor 74 is connected to ground. A base terminal of transistor 74 is connected to a current source 76 and to a collector terminal of the transistor 80. The other side of the current source 76 is connected to ground. The current source 76 provides a current of 10/2. An emitter terminal of transistor 80 is connected to a current source 82 and to a collector terminal of a transistor 84. The other side of the current source 82 is connected to a source 83 of supply voltage Vcc. The current source 82 provides a current of 10. An emitter terminal of transistor 84 is connected to the base terminal of transistor 80. A base terminal of transistor 84 is connected to a plus terminal of a voltage source 86 providing a voltage Vref. The minus terminal of the voltage source 86 is connected to ground. Vin is an input variable as a voltage between ground and the base of transistor 72. II is an output variable as the collector current of transistor 72.

The circuit of Fig. 5 shows a single-ended version of Fig. 4. It behaves like the normal common emitter stage. The difference with a normal common emitter stage is that transistor 72 carries a current 10/2 when Vin is equal to Vref, independent of device characteristics if transistors 72 and transistor 84 are matched.

Equation (1) shows the formula for II.

The present invention discloses a transconductance stage of class AB. The stage operates at a low quiescent current, which is well controlled by a local negative feedback loop. The feedback loop assures that currents are automatically boosted when a large differential voltage appears at the input terminals. The local feedback loop is tight and designed for optimum speed. This is achieved in that the only p-type transistor in this loop operates in common-base configuration. Hence, the circuit operates very well up to the transit frequency of the p-type transistor. The proposed transconductance stage has a high common mode rejection and can be used to replace the differential pair in many amplifier topologies. The present invention is especially useful for wide bandwidth (operational) amplifiers, which require high slew rates. For this reason, it offers good perspectives for application in a video output amplifier, which drives the cathodes of a cathode ray tube (CRT) directly. The application is characterized by high voltages. The supply voltage can range up to 250V and the output voltage swings can be up to 150V. Quiescent currents are preferably low to minimize static dissipation at these high supply voltages. The application requires a speed in terms of small-signal bandwidth and a slew rate which is at the edge of what the technology offers. As static dissipation must be minimized, yet high slew rates are also necessary, and class-AB operation is mandatory. The idea may also be useful for application in Scan Velocity Modulation (ScaVeM) amplifiers. This is a trick used in TV sets for improving the resolution of the picture by modulating the horizontal scan velocity of the electron beam at black-to-white and white-to-black transitions. The most important issue is that again the supply voltage is high (50V-150V) and the static current should be kept low, to limit static dissipation. For picture improvement reasons, ScaVeM amplifiers modulate the horizontal scan in TVs with CRTs. This application is also characterized by high voltages, and high speed is required. Furthermore, the invention can generally be used in amplifying applications where static dissipation is an issue. New characteristics and advantages of the invention covered by this document have been set forth in the foregoing description. It will be understood, however, that this disclosure is, in many respects, only illustrative. Changes may be made in details, particularly in matters of shape, size, and arrangement of parts, without departing from the scope of the invention. The scope of the invention is, of course, defined in the language in which the appended claims are expressed.

For example, although the above description focuses on bipolar transistors, it will be clear to those skilled in the art that field effect transistors, such as MOSFETs may be used instead of bipolar transistors. In that case the words gate, drain, and source should be substituted where in the description the transistor terminals are referred to as base, collector, and emitter.

Claims

CLAIMS:

1. A high-speed class-AB transconductance stage comprising: a first transistor with a control electrode and a main current-conducting path terminated by a first main electrode and a second main electrode, wherein the control electrode of the first transistor is a first input terminal; the first main electrode of the first transistor is a first output terminal; a first operational amplifier is coupled by its output to the second main electrode of the first transistor and to its own inverting input terminal; an input voltage source has a first terminal coupled to the control electrode of the first transistor, further having a second terminal coupled to ground; and a reference voltage source has a first terminal coupled to a non- inverting input terminal of the first operational amplifier and a further terminal coupled to ground.

2. A high-speed class-AB transconductance stage as claimed in claim 1, wherein said first transistor is a bipolar transistor with a base as the control electrode, a collector as the first main electrode, and an emitter as the second main electrode.

3. The stage of claim 2, wherein the first operational amplifier comprises an input transistor wherein a base terminal of the input transistor is a non-inverting input terminal; an emitter terminal of the input transistor is an inverting input terminal; a folded cascode transistor is connected by its emitter terminal to the collector terminal of the input transistor; the base terminal of the folded cascode transistor is connected to the inverting input terminal; a first current source is connected to the collector terminal of the input transistor and the emitter terminal of the folded cascode transistor; a second current source is connected to the collector terminal of the folded cascode transistor; an output transistor is connected by its base terminal to the collector terminal of the folded cascode transistor and to the second current source; the emitter terminal of the output transistor is connected to ground; and the collector terminal of the output transistor is the output terminal of the operational amplifier.

4. The stage of claim 3, wherein the folded cascode transistor is used to convey the current of the input transistor to another voltage level.

5. The stage of claim 3, wherein the first transistor of the transconductance stage, the input transistor of the operational amplifier, and the output transistor of the operational amplifier are of the fastest type in a given IC process.

6. A transconductance stage comprising: a first transistor and a second transistor both having a first control electrode, a main current conducting path terminated by a first main electrode, and a second main electrode, wherein the first control electrode of the first transistor is a first input terminal; the first control electrode of the second transistor is a second input terminal; the first main electrode of the first transistor is a first output terminal; the first main electrode of the second transistor is a second output terminal; a first operational amplifier is coupled by its output terminal to the second main electrode of the first transistor and to its own inverting terminal; a second operational amplifier is coupled by its output to the second main electrode of the second fransistor and to its own inverting terminal; a differential voltage source is coupled by one terminal to the confrol electrode of the first transistor and by another terminal to the confrol electrode of the second fransistor; a common mode voltage source is coupled by one terminal to the control electrode of the first or second fransistor and by another terminal to ground; a first bias voltage source is coupled by a terminal coupled to the control electrode of the first transistor and by a further terminal to a non-inverting terminal of the second operational amplifier; and a second bias voltage source is coupled by a terminal to the control electrode of the second transistor and by a further terminal to a non-inverting terminal of the first operational amplifier.

7. The transconductance stage as claimed in claim 6, wherein said first and second transistors are bipolar transistors with a base as the control electrode, a collector as the first main electrode, and an emitter as the second main electrode.

8. The stage of claim 7, wherein the first and second operational amplifiers including the first and second base emitter voltage sources comprise an input transistor, wherein a base terminal of the input transistor is a non-inverting input terminal; an emitter terminal of the input transistor is an inverting input terminal; a folded cascode transistor is connected by its emitter terminal to the collector terminal of the input transistor; the base terminal of the folded cascode transistor is connected to the inverting input terminal; a first current source is connected to the collector terminal of the input transistor and the emitter terminal of the folded cascode transistor; a second current source is connected to the collector terminal of the folded cascode transistor; an output transistor is connected by its base terminal to the collector terminal of the folded cascode transistor; the emitter terminal of the output transistor is connected to ground; and the collector terminal of the output transistor is the output terminal of the operational amplifier.

9. The stage of claim 8, wherein the first and second transistors, the input transistor of the first and second operational amplifier, and the output transistor of the first and second operational amplifiers are of the fastest type in a given IC process.

10. The stage of claim 8, wherein the folded cascode transistor of the first and second operational amplifiers is a current conveyor, conveying a current in a branch to the same current in another branch at a different voltage.