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WO2003102963A1 - An integrated circuit having a memory device, and a method of testing such an integrated circuit - Google Patents

An integrated circuit having a memory device, and a method of testing such an integrated circuit Download PDF

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Publication number
WO2003102963A1
WO2003102963A1 PCT/SG2002/000093 SG0200093W WO03102963A1 WO 2003102963 A1 WO2003102963 A1 WO 2003102963A1 SG 0200093 W SG0200093 W SG 0200093W WO 03102963 A1 WO03102963 A1 WO 03102963A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
memory device
address
data
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SG2002/000093
Other languages
French (fr)
Inventor
Prashant Balakrishnan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to PCT/SG2002/000093 priority Critical patent/WO2003102963A1/en
Priority to CN02828961.7A priority patent/CN1625782A/en
Priority to TW092107295A priority patent/TW200307296A/en
Publication of WO2003102963A1 publication Critical patent/WO2003102963A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories

Definitions

  • An integrated circuit having a memory device, and a method of testing such an integrated circuit
  • the present invention relates to a method of testing a memory device located on an integrated circuit, and method of testing such a device.
  • FIFO memory devices typically include such a device at each of the input ports.
  • FIFO memory devices are implemented as dual port memories, which are more compact than register-based implementations of memory.
  • register-based implementations of memory Like all integrated circuitry, such memory devices are occasionally faulty, and it is desirable to test them, both to ensure that the resultant integrated circuit is operational, and also to identify the fault during the production process of the integrated circuit.
  • the favoured method for testing a memory is BIST (built-in self-test), illustrated in Fig. 1.
  • the memory device 1 has an address input Addr for receiving an address defining a location in the memory, a data input D for specifying the data which is to be written to that address, and a control input C which receives a "write” or "read” command if the specified data is to be written into the specified address.
  • the integrated circuit includes a BIST module 3 and switches 5, 7-, 9.
  • the switches 5, 7, 9 transmit outputs of the BIST module 3 to the respective inputs of the memory device 1.
  • the BIST thereby transmits a predetermined sequence of inputs to the memory device 1 and the outputs of the memory device 1 are monitored to determine whether the memory device 1 outputs a corresponding desired output through its output 11.
  • the BIST module 3 ensures that exactly known signals are sent to all the inputs of the memory device, so that the memory device can be tested reliably in isolation, even if there are faults in other locations of the integrated circuit.
  • the switches 5, 7, 9 ensure that respective signals 13, 15, 17 (which may be generated by other modules on the integrated circuit, or alternatively be received by the integrated circuit from outside) are transmitted to the inputs Addr, D and C of the memory device.
  • the BIST module 3 is not used at all, and it and the switches 13, 15, 17 amount to an overhead on the overall efficiency and area of the integrated circuit.
  • the integrated circuit comprises a number of memory devices 1 (e.g. in the case of an integrated circuit which is a switching device having multiple input ports), providing a BIST module 3 for each memory device 1 is a large overhead.
  • the alternative that is providing only a single BIST module 3 and using it to test a plurality of memory devices in turn, significantly complicates the logic of the integrated circuit and makes it hard to provide a symmetrical circuit design.
  • the present invention seeks to address the above problems, and in particular to provide a new integrated circuit and a new method of testing an integrated circuit.
  • the invention proposes that an integrated circuit having one or more memory devices is tested by transmitting into the integrated circuit (i) an address signal indicating an memory address, (ii) a data signal indicating data for that address, and (iii) for each respective memory device a command signal which indicates whether the data is to be written to the respective memory device.
  • the data output by each memory device, and at least some of the signals it has received, are both monitored.
  • the integrated circuit does not require a BIST module for generating exactly known signals to all inputs of the memory devices. It is true that, in contrast to the BIST method, this may mean that the data which reaches the memory module is corrupted from the desired input on its way to the memory device due to other faults in the integrated circuit. However, the data which is input to the memory device is monitored with sufficient accuracy that if it is corrupted, due to a fault on the integrated circuit other than in the memory device, that fact will be noted and the memory device will not be incorrectly blamed for having generated the fault.
  • the invention makes possible a functional testing of the memory devices, as opposed to one based on an additional test logic which is only employed during the test procedure.
  • the present invention may thus lead to significant cost savings, by removing the need to provide the additional logic on-chip.
  • the monitoring of the data input to each memory device comprises only the monitoring of a monitoring signal formed from the address signal and the command signal. It is particularly efficient if the monitoring signal is performed by an operation including (or logically equivalent to) an XOR operation and given to a scan register, because in that case the monitoring signal will toggle whenever either of the address signal and the command signals toggles: in other words the monitoring signal efficiently compresses the full address signal and command signal.
  • a first expression of the invention is an integrated circuit including one or more memory devices, each memory device having an address input for receiving an address signal specifying an address in the memory, a data input for receiving data, a command input for receiving a command signal indicating whether the data is to be written into the address, and an output, the integrated circuit further including a monitoring unit for deriving a monitoring signal from at least some of the signals input to each memory device.
  • a second expression of the invention is a method of testing an integrated circuit including one or more memory devices, each memory device having an address input for receiving an address signal specifying an address in the memory, a data input for receiving data, a command input for receiving a command signal indicating whether the data is to be written into the address, and an output, the method comprising: transmitting signals into the integrated circuit to cause the one or more memory devices to each receive an address signal, a data signal and for each memory device a corresponding command signal, monitoring at least some of the signals input to each memory device and the data output from the memory devices.
  • Fig. 1 shows schematically a known BIST memory testing scheme
  • Fig. 2 shows the configuration of a memory device provided on an integrated circuit according to the present invention.
  • a memory device 21 which has an address input Addr for receiving an address signal specifying an address within the memory, a data input D for receiving a data signal specifying the data which is to be written to that address, and a control input C which receives a "write" command if the specified data is to be written into the specified address.
  • the embodiment has an additional XOR gate (monitoring unit) 23, which receives as inputs the address signal 25 and the control signal 27 and generates a combined signal 29.
  • the memory device 21 is typically one of a plurality of equivalently constructed memory devices provided on an integrated circuit.
  • the integrated circuit receives and transmits to all the memory devices data generated off the integrated circuit comprising an address signal (serial address), a data signal and a respective command signal for each memory device.
  • the data signals may for example be successively AA/55/FF/00. Note that although the various signals originate off-chip they may be modified on-chip on their way to the memory device 1 by the circuitry which, during the normal operation of the integrated circuit, processes signals input to the integrated circuit and transmits them to the memory device(s).
  • all the memory devices receive the address signal, the data signal, and their own control signal.
  • the integrated circuit may be faulty, it is not certain that this data will be correctly transmitted to each of the memory devices. However, this can be observed by monitoring the outputs 29 of the respective memory devices.
  • the output 29 is passed to a scan register 31 , from where it can be monitored.
  • the output from multiple memory devices 21 may be passed to the same scan register.
  • the other outputs 11 of the memory device 21 are monitored in the normal functional mode.
  • the invention will be employed in a switching device with 24 Fast Ethernet ports and 2 Gigabit ports. Typically, in such a device the same block is implemented as many times as the number of ports.
  • the device may be implemented as a single port memory instead of as a dual port memory.

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  • Tests Of Electronic Circuits (AREA)

Abstract

An integrated circuit carrying memory devices is tested by transmitting into it (i) an address signal indicating an memory address, (ii) a data signal indicating data for that address, and (iii) for each memory device a respective command signal which indicates whether the data is to be written to the respective memory device. The data output by each memory device, and at least some of the signals it has received, are both monitored. Since the data is generated off-chip, the integrated circuit does not require a BIST module for generating exactly known signals to all inputs of the memory devices during the test mode. The signals input to the memory device are monitored with sufficient accuracy that if they are corrupted, due to a fault on the integrated circuit other than at the memory device, that fact will be noted and the memory device will not be incorrectly blamed for having generated the fault.

Description

An integrated circuit having a memory device, and a method of testing such an integrated circuit
Field of the invention
The present invention relates to a method of testing a memory device located on an integrated circuit, and method of testing such a device.
Background of the invention
Many modern integrated circuits employ first-in-first-out (FIFO) memory devices. A switching device, for example, typically includes such a device at each of the input ports. Typically FIFO memory devices are implemented as dual port memories, which are more compact than register-based implementations of memory. Like all integrated circuitry, such memory devices are occasionally faulty, and it is desirable to test them, both to ensure that the resultant integrated circuit is operational, and also to identify the fault during the production process of the integrated circuit.
Presently, the favoured method for testing a memory is BIST (built-in self-test), illustrated in Fig. 1. The memory device 1 has an address input Addr for receiving an address defining a location in the memory, a data input D for specifying the data which is to be written to that address, and a control input C which receives a "write" or "read" command if the specified data is to be written into the specified address. The integrated circuit includes a BIST module 3 and switches 5, 7-, 9.
During a testing mode of the integrated circuit, the switches 5, 7, 9 transmit outputs of the BIST module 3 to the respective inputs of the memory device 1. The BIST thereby transmits a predetermined sequence of inputs to the memory device 1 and the outputs of the memory device 1 are monitored to determine whether the memory device 1 outputs a corresponding desired output through its output 11. The BIST module 3 ensures that exactly known signals are sent to all the inputs of the memory device, so that the memory device can be tested reliably in isolation, even if there are faults in other locations of the integrated circuit.
Once the testing operation is finished however, the normal operation of the integrated circuit begins. In this mode, the switches 5, 7, 9 ensure that respective signals 13, 15, 17 (which may be generated by other modules on the integrated circuit, or alternatively be received by the integrated circuit from outside) are transmitted to the inputs Addr, D and C of the memory device. In this normal operation of the integrated circuit, the BIST module 3 is not used at all, and it and the switches 13, 15, 17 amount to an overhead on the overall efficiency and area of the integrated circuit.
When the integrated circuit comprises a number of memory devices 1 (e.g. in the case of an integrated circuit which is a switching device having multiple input ports), providing a BIST module 3 for each memory device 1 is a large overhead. However, the alternative, that is providing only a single BIST module 3 and using it to test a plurality of memory devices in turn, significantly complicates the logic of the integrated circuit and makes it hard to provide a symmetrical circuit design.
Summary of the invention
The present invention seeks to address the above problems, and in particular to provide a new integrated circuit and a new method of testing an integrated circuit.
In general terms, the invention proposes that an integrated circuit having one or more memory devices is tested by transmitting into the integrated circuit (i) an address signal indicating an memory address, (ii) a data signal indicating data for that address, and (iii) for each respective memory device a command signal which indicates whether the data is to be written to the respective memory device. The data output by each memory device, and at least some of the signals it has received, are both monitored.
Since the data is generated off-chip, the integrated circuit does not require a BIST module for generating exactly known signals to all inputs of the memory devices. It is true that, in contrast to the BIST method, this may mean that the data which reaches the memory module is corrupted from the desired input on its way to the memory device due to other faults in the integrated circuit. However, the data which is input to the memory device is monitored with sufficient accuracy that if it is corrupted, due to a fault on the integrated circuit other than in the memory device, that fact will be noted and the memory device will not be incorrectly blamed for having generated the fault.
In other words, the invention makes possible a functional testing of the memory devices, as opposed to one based on an additional test logic which is only employed during the test procedure. The present invention may thus lead to significant cost savings, by removing the need to provide the additional logic on-chip.
The present inventors further propose that the monitoring of the data input to each memory device comprises only the monitoring of a monitoring signal formed from the address signal and the command signal. It is particularly efficient if the monitoring signal is performed by an operation including (or logically equivalent to) an XOR operation and given to a scan register, because in that case the monitoring signal will toggle whenever either of the address signal and the command signals toggles: in other words the monitoring signal efficiently compresses the full address signal and command signal.
Specifically, in a first expression of the invention is an integrated circuit including one or more memory devices, each memory device having an address input for receiving an address signal specifying an address in the memory, a data input for receiving data, a command input for receiving a command signal indicating whether the data is to be written into the address, and an output, the integrated circuit further including a monitoring unit for deriving a monitoring signal from at least some of the signals input to each memory device.
A second expression of the invention is a method of testing an integrated circuit including one or more memory devices, each memory device having an address input for receiving an address signal specifying an address in the memory, a data input for receiving data, a command input for receiving a command signal indicating whether the data is to be written into the address, and an output, the method comprising: transmitting signals into the integrated circuit to cause the one or more memory devices to each receive an address signal, a data signal and for each memory device a corresponding command signal, monitoring at least some of the signals input to each memory device and the data output from the memory devices.
Brief description of the figures
An embodiment of the invention will now be described in detail for the sake of example only, with reference to the following figures in which:
Fig. 1 shows schematically a known BIST memory testing scheme; and Fig. 2 shows the configuration of a memory device provided on an integrated circuit according to the present invention.
Detailed Description of the Embodiment
Referring to figure 2, a memory device 21 is shown which has an address input Addr for receiving an address signal specifying an address within the memory, a data input D for receiving a data signal specifying the data which is to be written to that address, and a control input C which receives a "write" command if the specified data is to be written into the specified address. In comparison to the configuration shown in Fig. 1 , the embodiment has an additional XOR gate (monitoring unit) 23, which receives as inputs the address signal 25 and the control signal 27 and generates a combined signal 29.
The memory device 21 is typically one of a plurality of equivalently constructed memory devices provided on an integrated circuit. The integrated circuit receives and transmits to all the memory devices data generated off the integrated circuit comprising an address signal (serial address), a data signal and a respective command signal for each memory device. The data signals may for example be successively AA/55/FF/00. Note that although the various signals originate off-chip they may be modified on-chip on their way to the memory device 1 by the circuitry which, during the normal operation of the integrated circuit, processes signals input to the integrated circuit and transmits them to the memory device(s).
Ideally, all the memory devices (such as device 21) receive the address signal, the data signal, and their own control signal. However, since the integrated circuit may be faulty, it is not certain that this data will be correctly transmitted to each of the memory devices. However, this can be observed by monitoring the outputs 29 of the respective memory devices. The output 29 is passed to a scan register 31 , from where it can be monitored. The output from multiple memory devices 21 may be passed to the same scan register. The other outputs 11 of the memory device 21 are monitored in the normal functional mode.
It is presently envisaged that the invention will be employed in a switching device with 24 Fast Ethernet ports and 2 Gigabit ports. Typically, in such a device the same block is implemented as many times as the number of ports. Although only a single embodiment of the invention has been described above, the invention is not limited in which respect, and many variations are possible within the scope of the invention as will be clear to a skilled reader. For example, the device may be implemented as a single port memory instead of as a dual port memory.

Claims

Claims
1. An integrated circuit including one or more memory devices, each memory device having an address input for receiving an address signal specifying an address in the memory, a data input for receiving data, a command input for receiving a command signal indicating whether the data is to be written into the address, and an output, the integrated circuit further including a monitoring unit for deriving a monitoring signal from at least some of the signals input to each memory device.
2. An integrated circuit according to claim 1 in which the monitoring unit derives the monitoring signal from the address signal and the command signal.
3. An integrated circuit according to claim 1 or claim 2 in which the monitoring unit is an XOR gate.
4. An integrated circuit according to any preceding claim in which the memory device is a FIFO memory device.
5. An integrated circuit according to any preceding claim which operates as a switching device.
6. A method of testing an integrated circuit including one or more memory devices, each memory device having an address input for receiving an address signal specifying an address in the memory, a data input for receiving data, a command input for receiving a command signal indicating whether the data is to be written into or read from the specified address, and an output, the method comprising: transmitting signals into the integrated circuit to cause the one or more memory devices to each receive an address signal, a data signal and for each memory device a corresponding command signal, monitoring at least some of the signals input to each memory device and the data output from the memory devices.
7. A method according to claim 6 in which the monitoring of the signals input to each memory device comprises monitoring a signal derived from the address signal and the command signal.
8. A method according -to claim 6 in which the signal is derived from the address signal and the command signal as an XOR operation, and passed to a scan register.
PCT/SG2002/000093 2002-05-15 2002-05-15 An integrated circuit having a memory device, and a method of testing such an integrated circuit Ceased WO2003102963A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/SG2002/000093 WO2003102963A1 (en) 2002-05-15 2002-05-15 An integrated circuit having a memory device, and a method of testing such an integrated circuit
CN02828961.7A CN1625782A (en) 2002-05-15 2002-05-15 Integrated circuit with storage device and method for testing the integrated circuit
TW092107295A TW200307296A (en) 2002-05-15 2003-03-31 An integrated circuit having a memory device, and a method of testing such an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2002/000093 WO2003102963A1 (en) 2002-05-15 2002-05-15 An integrated circuit having a memory device, and a method of testing such an integrated circuit

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WO2003102963A1 true WO2003102963A1 (en) 2003-12-11

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
DE102005018790A1 (en) * 2005-03-14 2006-09-21 Infineon Technologies Flash Gmbh & Co. Kg Integrated circuit and method for operating and parallel testing integrated circuits
US9196381B2 (en) 2012-11-01 2015-11-24 Futurewei Technologies, Inc. Technique to operate memory in functional mode under LBIST test

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9482718B2 (en) * 2014-01-13 2016-11-01 Texas Instruments Incorporated Integrated circuit

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US4672609A (en) * 1982-01-19 1987-06-09 Tandem Computers Incorporated Memory system with operation error detection
EP0449052A2 (en) * 1990-03-29 1991-10-02 National Semiconductor Corporation Parity test method and apparatus for a memory chip
US5404332A (en) * 1993-10-07 1995-04-04 Fujitsu Limited Apparatus for and a method of detecting a malfunction of a FIFO memory
US5444722A (en) * 1993-02-17 1995-08-22 Unisys Corporation Memory module with address error detection
US5546385A (en) * 1995-01-19 1996-08-13 Intel Corporation Flexible switching hub for a communication network
US5579322A (en) * 1993-09-02 1996-11-26 Sony Corporation Dual port memory having testing circuit

Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
US4672609A (en) * 1982-01-19 1987-06-09 Tandem Computers Incorporated Memory system with operation error detection
EP0449052A2 (en) * 1990-03-29 1991-10-02 National Semiconductor Corporation Parity test method and apparatus for a memory chip
US5444722A (en) * 1993-02-17 1995-08-22 Unisys Corporation Memory module with address error detection
US5579322A (en) * 1993-09-02 1996-11-26 Sony Corporation Dual port memory having testing circuit
US5404332A (en) * 1993-10-07 1995-04-04 Fujitsu Limited Apparatus for and a method of detecting a malfunction of a FIFO memory
US5546385A (en) * 1995-01-19 1996-08-13 Intel Corporation Flexible switching hub for a communication network

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005018790A1 (en) * 2005-03-14 2006-09-21 Infineon Technologies Flash Gmbh & Co. Kg Integrated circuit and method for operating and parallel testing integrated circuits
US7409609B2 (en) 2005-03-14 2008-08-05 Infineon Technologies Flash Gmbh & Co. Kg Integrated circuit with a control input that can be disabled
US9196381B2 (en) 2012-11-01 2015-11-24 Futurewei Technologies, Inc. Technique to operate memory in functional mode under LBIST test

Also Published As

Publication number Publication date
CN1625782A (en) 2005-06-08
TW200307296A (en) 2003-12-01

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