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WO2003039055A1 - Procede et dispositif pour representer la base de depart d'un codeur dans l'espace signal d'une modulation qam ou psk - Google Patents

Procede et dispositif pour representer la base de depart d'un codeur dans l'espace signal d'une modulation qam ou psk Download PDF

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Publication number
WO2003039055A1
WO2003039055A1 PCT/DE2001/004105 DE0104105W WO03039055A1 WO 2003039055 A1 WO2003039055 A1 WO 2003039055A1 DE 0104105 W DE0104105 W DE 0104105W WO 03039055 A1 WO03039055 A1 WO 03039055A1
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Prior art keywords
bits
bit
interleaver
reliability
bit stream
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PCT/DE2001/004105
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German (de)
English (en)
Inventor
Bernhard Raaf
Martin DÖTTLING
Jürgen MICHEL
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Siemens AG
Siemens Corp
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Siemens AG
Siemens Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H04L1/0069—Puncturing patterns
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
    • H04L27/3416—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes

Definitions

  • the present invention relates to a method for adapting the bit rate of a bit stream to be transmitted in a communication system, in particular a mobile radio system, and a corresponding communication device.
  • a rate adaptation (“rate matching") is provided on the transmitter side in order to adapt the bit rate of the bit stream to be transmitted to the respectively possible transmission rate, wherein bits are either removed from the bit stream or multiplied, in particular doubled, in the bit stream ,
  • the removal of bits is referred to as "puncturing” and the multiplication as repetition ("repetition").
  • FIG. 1 A possible structure of the transmission path of a mobile radio transmitter, in which such a bit rate adaptation is provided, is shown by way of example in FIG. 1.
  • a data stream consisting of several data or transport blocks is first expanded by a device 1 by so-called “tail bits”.
  • the bit stream thus output by the device 1 is fed to a channel encoder 2, where redundant bits are added to the information bits depending on the type of channel coding used in each case, so that in most coding schemes so-called systematic bits on the one hand and parity bits ("parity Depending on the code rate of the channel encoder 2, more or less systematic bits or parity bits arise.
  • the parity bits have a lower priority or importance for the decoding of the corresponding message than the systematic bits
  • Channel encoder 2 can be a so-called turbo encoder, for example, in UMTS mobile radio systems, which is usually constructed from interleaved convolutional encoders.
  • the channel encoder 2 is followed by a bit rate adaptation device 3 which punctures and / or repeats the bits supplied to it in accordance with a specific bit rate adaptation algorithm. Due to the lower importance or priority of the parity bits, the parity bits are conventionally preferably punctured for bit rate adaptation, since these are less important than the systematic bits for successful decoding of the respective message on the receiver side.
  • the bit stream output by the bit rate adaptation device 3 is scrambled with the aid of an interleaver 4, so that the individual bits are rearranged in time according to a specific interleaving law a.
  • the result of the interleaver 4 is that the priorities of the individual bits are no longer known in the bit stream output by it.
  • the bits output by the interleaver 4 are fed to a modulator 5 which, depending on the type of modulation used in each case, determines several of these bits
  • QPSK modulation Quadrature Phase Shift Keying
  • two bits are each divided into four symbols evenly distributed in a two-dimensional symbol space, while in one
  • 8PSK modulation three bits, with 16QAM modulation ("quadrature amplitude modulation") four bits and with a 64QAM Modulation six bits can be assigned to a symbol in a two-dimensional symbol space.
  • the symbols generated by the modulator 5 are transmitted in the form of a real and imaginary part, which clearly describe the position of the respective symbol in the two-dimensional symbol space.
  • a demultiplexer 7 connected downstream of the modulator 5 distributes the symbols over possibly several channels, where the symbol sequence is coded with different channeling or spreading codes Wi ... W M , which is shown in FIG. 1 in the form of corresponding multipliers 8.
  • the sum signal of these differently spread symbol sequences is generated and output via a summer 9.
  • a control unit 6 is provided with the abbreviation AMCS ("Adaptive Modulation and Coding Scheines"), which controls the modulation alphabet of the modulator 5 to be used as well as the coding schemes and code rates of the channel encoder 2 and the division into the individual channelization codes sets the demultiplexer 7.
  • AMCS Adaptive Modulation and Coding Scheines
  • the transmission path structure shown in FIG. 1 corresponds, for example, to the structure of the physical layer provided for a so-called HSDPA connection ("High Speed Downlink Packet Access") in UMTS mobile radio systems.
  • HSDPA connection High Speed Downlink Packet Access
  • This is a packet-switched connection type, and what is known as an ARQ process ("Automatic Repeat Request") can also be used, the receiver (for example a mobile station) of a data packet, if this data packet is incorrectly received, from retransmitting it Sender (for example a base station) requests, whereupon the transmitter sends a repetition of the originally sent data packet to the receiver.
  • Sender for example a base station
  • the signal constellation or the two-dimensional symbol space 12 for 16QAM modulation being shown by way of example in FIG. 3A.
  • four bits ii, qi, i 2 and q 2 are each assigned to a symbol 13 of the two-dimensional symbol space 12 shown in FIG. 3A, the type of mapping of the individual bits onto the symbols 13 being referred to as "gray mapping" ,
  • those columns or rows of symbols are marked with a dash which correspond to a bit ii or i 2 or qi or q 2 with the value "1".
  • the signal constellation or the two-dimensional symbol space 12 for 64QAM modulation is shown by way of example.
  • There are six bits each ii, qi i- 2 ⁇ 32, i 3 and q 4 are assigned in the order given to a symbol 13 of the two-dimensional symbol space 12 shown in FIG. 3A.
  • FIG. 2 A further proposal is shown in FIG. 2, whereby after the channel encoder or turbo encoder 2, which outputs the bits separately according to systematic bits S and parity bits P, separate processing of the systematic bits and parity bits is performed. Therefore, in particular, two separate interleavers 4a and 4b are provided, with a device 10 having a parallel / serial conversion to only one bit stream in such a way that the most intelligent possible assignment of the bits with different priorities or importance to the bit positions with different reliability can be done within the individual symbols.
  • the bits with the highest priority, ie the systematic bits S are preferably distributed to the bit positions with the highest reliability and the bits with the lowest priority, ie the parity bits, to the bit positions with the lowest reliability.
  • the present invention is therefore based on the object of providing a method for adapting the bit rate of a bit stream to be transmitted in a communication system and a communication device, the data transmission quality and data transmission security being able to be improved with as little effort as possible regardless of the code rate selected in each case.
  • This object is achieved according to the invention by a method with the features of claim 1 or a communication device with the features of claim 20.
  • the subclaims each define preferred and advantageous embodiments of the present invention.
  • the systematic bits are mapped to bit positions of the modulation symbols with a high degree of reliability and, if the number of bit positions with the high degree of reliability is not sufficient, to bit positions with a lower degree of reliability.
  • the parity bits are mapped to the remaining bit positions with the lower reliability after a corresponding bit rate adjustment has been carried out.
  • Systematic bits to be mapped preferably selected as uniformly as possible from all systematic bits to be transmitted.
  • the principle described above can also be applied to more than two different reliabilities, such as occur with 64QAM modulation, for example.
  • the systematic bits can be mapped, for example, to the bit positions with a high reliability and, if the number of bit positions with the high reliability is not sufficient, to the bit positions with a medium reliability, while the parity bits to the bit positions with a low reliability and the remaining bit positions are mapped with the average reliability.
  • the reliabilities can be divided into a first group of reliabilities and a second group of reliabilities, the reliabilities contained in the first group being higher than the reliabilities contained in the second group, so that the method described above applies accordingly to the two groups assigned bit positions can be applied.
  • corresponding exemplary embodiments of the rate adaptation device according to the invention which processes systematic bits and parity bits of the channel encoder in accordance with the previously described method, are proposed for different effective code rates.
  • the bits to be mapped to the bit positions with the high reliability and the bit positions with the low or lower reliability are fed to separate interleavers, which are preferably designed differently in order to achieve the best possible distribution of the bits to be transmitted.
  • interleavers which are preferably designed differently in order to achieve the best possible distribution of the bits to be transmitted.
  • Corresponding exemplary embodiments are also described in detail in this regard. It is expressly pointed out that the various configurations of the interleaver are in principle independent of the previously described inventive concept and can of course also be used in communication devices in which the above inventive concept has not been implemented.
  • the present invention is preferably suitable for use in mobile radio systems, in particular for use in UMTS mobile radio systems.
  • the present invention is not limited to this preferred area of application, but can generally be used in any communication system where systematic bits and parity bits are to be transmitted.
  • the transmitter side not only the transmitter side, but also the receiver side is affected by the present invention, since on the receiver side a received signal processed according to the invention must be evaluated.
  • FIG. 1 shows a simplified block diagram of a conventional transmission path structure of a mobile radio transmitter
  • FIG. 2 shows a simplified block diagram of a further conventional transmission path structure of a mobile radio transmitter
  • FIG. 3A and FIG. 3B show the signal constellation for a 16QAM modulation and a 64QAM modulation
  • FIG. 4 shows a simplified block diagram of the transmission path structure of a mobile radio transmitter according to a first exemplary embodiment of the present invention
  • FIG. 5 shows a simplified block diagram of the transmission path structure of a mobile radio transmitter according to a second exemplary embodiment of the present invention
  • FIG. 6 shows a simplified block diagram of the transmission path structure of a mobile radio transmitter according to a third exemplary embodiment of the present invention
  • FIG. 7 shows an illustration to clarify the writing of bits into the interleaver shown in FIGS. 4 through 6 according to an embodiment of the present invention
  • FIG. 8 shows an illustration to illustrate a shift in the writing of bits into the interleaver shown in FIGS. 4 through 6 and a shift in the reading out of the bits therefrom according to a further exemplary embodiment of the present invention
  • FIG. 9 shows a representation to explain a procedure for determining optimized column swapping algorithms for the interleaver shown in FIGS. 4 through 6.
  • FIG. 10 shows a block diagram for a rate adjustment algorithm.
  • FIGS. 11 to 13 show diagrams to illustrate different variants of a rate adjustment algorithm
  • Figure 14 shows a block diagram for a rate adjustment algorithm.
  • the parity bits are mapped to symbols with low or lower reliability, the number of parity bits to be mapped being adapted to the symbols available according to steps (a) and (b) by rate adaptation.
  • 16QAM modulation as already explained with reference to FIG. 3A, only bit positions or symbols with two different transmission reliabilities, namely with high reliability (H) and low reliability (L), are distinguished.
  • H high reliability
  • L low reliability
  • 64QAM modulation is of particular interest for the UMTS-HSDPA transmission standard.
  • the 64QAM modulation has symbols or bit positions with three different reliabilities, namely with high, medium and low reliability.
  • the systematic bits can first be mapped to bit positions of the modulation symbols with high reliability and the parity bits to bit positions with low reliability. The remaining systematic bits and parity bits are then mapped evenly to the bit positions with medium reliability (preference being given to the systematic bits if in doubt).
  • Another possibility is to group the different reliabilities in such a way that there are only two classes of bits to which steps (a) - (c) above can be applied. It makes sense to combine the bit positions with high and medium reliability in one class, while the other class corresponds to the bit positions with low reliability.
  • the first class then contains twice as many symbols and bits as the second class.
  • half of the bits with medium reliability can be added to the bit class with high and low reliability.
  • two classes with the same number of bits are created and the implementation of the method can be carried out completely analogously to the 16QAM.
  • the 8PSK modulation as with the 16QAM modulation, there are only two different reliabilities, so that the above steps (a) - (c) can, in principle, also be transferred to the 8PSK modulation.
  • the number of bit positions with high reliability is twice as high as the number of bit positions with low reliability, which must be taken into account accordingly in the rate adjustment.
  • the method described above should preferably be designed in such a way that "related" bits are also output together. This means that systematic bits whose positions differ only slightly in the output bit stream of the channel encoder also follow similar positions in the bit stream
  • This principle can be applied both to adjacent systematic bits and to adjacent parity bits and also to adjacent systematic bits and parity bits. In these cases, too, this measure can be used to achieve a wide separation of adjacent bits after interleaving. This is relevant, since every second half iteration of the channel decoding systematic bits are used together with the associated parity bits of the corresponding bit stream with a similar position in the output bit stream of the channel encoder. The more of these bits were poorly transmitted in the local environment, the more likely it is to be incorrectly detected, which which is more likely if these bits were sent over the respective transmission channel at similar times, since the channel properties are typically correlated over relatively short periods of time.
  • TTI interval Transmission Time Interval
  • the values for ZH and ZL can - as already described - differ from one another.
  • FIG. 4 shows an exemplary embodiment for the transmission path of a mobile radio transmitter according to the present invention for an effective code rate Ce> 0.5.
  • the bit stream output by the channel encoder 2 becomes with
  • bit rate adaptation device 3 Using a demultiplexer 11 divided into a bit stream with systematic bits ⁇ , a bit stream with first parity bits P1 and a bit stream with second parity bits P2.
  • the function of the bit rate adaptation device 3 shown in FIG. 1 is performed by a mapping device 14, rate adaptation devices 15 and 16, and a multiplexer 17 and a device 18 which describe the previously described Prepare the above steps (a) - (c) in order to be able to map the systematic bits S and the parity bits P1, P2 in the best possible way according to the rules described above to the bit positions with high or low reliability of the symbols of the modulator 5.
  • the mapping device 14 executes the following mapping algorithm:
  • the ABS function creates an absolute value.
  • This mapping algorithm is based on calculating an error value e, which is a measure for the deviation between the instantaneous puncturing rate and the desired puncture, two update parameter e m inus and e p ⁇ us are used to with the aid of the error value either e m i nus is reduced or increased by e p ⁇ us .
  • step 100 the error value e is initially set to an initial value ei n i, which represents the error between the instantaneous and the desired puncturing rate at the beginning of the method.
  • the index of the currently viewed bit is then set to 1 in a step 101.
  • the sequence embedded in a WHILE loop 102 is then carried out for all Xi bits of the respective data packet no. I. In this case is updated in a step 103 for bit x m of the error value e, for which purpose the difference is calculated between the instantaneous error value and the updated parameter e m i nus.
  • step 104 If the result is e ⁇ O (step 104), the corresponding output bit yl m of the upper output bit stream of the device 14 is punctured (step 105), while the corresponding output bit y2 m of the lower output bit stream of the device 14 is set to the value of the input bit x m (Step 106).
  • the corresponding error value e is then increased by the update parameter e P ⁇ us (step 107).
  • step 108 the output bit yl m is set to the value of the input bit x m and the output bit y2 m to a fill value ⁇ (steps 109, 110).
  • the fill value ⁇ identifies bits to be punctured in the second output bit stream y2 and is used to determine the bit order initially unchanged.
  • the second (lower) output bit stream y2 output by the mapping device is combined with the bit streams output by the rate adaptation devices 15 and 16 by a multiplexer 17 to form a common bit stream. All bits which have the fill value ⁇ in this bit stream are then removed from the bit stream by a device 18 connected downstream of the multiplexer 17 and thus punctured.
  • the index m of the bit to be processed is incremented (step 111).
  • mapping algorithm described above is based on a conventional puncturing algorithm in which a certain number of input bits are mapped to a smaller number of output bits by removing corresponding bits from the input bit stream as evenly as possible. Due to the expansion of this algorithm to two output bit streams explained above, this algorithm is not only suitable for rate adaptation, but also for demultiplexing bits onto the second output bit stream, with which the bits removed from the primary bit stream are transmitted. It is crucial for the performance of the transmission system that the selected bits are correlated as little as possible with regard to their information content, which is achieved by choosing the distance between two punctured bits or between two bit streams y1 and bitstream y2 as evenly as possible Bits is reached.
  • the first parity bits P1 and the second parity bits P2 are each subjected to a rate adjustment algorithm by the rate adjustment devices 15 and 16, which is similar to the mapping algorithm described above, but with the exception that that in each case the corresponding input bit stream is mapped onto only one output bit stream by removing or puncturing bits as uniformly as possible. That is, the rate adjustment algorithm corresponds to the above mapping algorithm without steps 106 and 110, wherein in addition in step 105 the corresponding bit is preferably not punctured immediately, but is first set to the fill value ⁇ .
  • the puncturing device 15 executes the rate adjustment algorithm with respect to the first parity bits P1 with the following parameters:
  • the FLOOR function rounds off the argument in parentheses to the next smaller integer value.
  • the CEIL function rounds the argument in brackets up to the next larger integer value.
  • the multiplexer 17 combines the second output bit stream y2 of the mapping device 14 and the output bit streams of the puncturing devices 15, 16 into a common bit stream, in which the device 18 then removes all the bits to which the fill value ⁇ has previously been assigned.
  • the first (upper) output bit stream y1 output by the mapping device 14 is fed to a first interleaver 4a which, according to a certain scheme, maps the corresponding bits to high-reliability bit positions (hereinafter also referred to as H-bit positions) of the 16QAM modulator 5 reorders.
  • the bits output by the device 18, on the other hand, are to be mapped to bit positions with low reliability of the modulator 5 (hereinafter also referred to as L-bit positions), so that a separate interleaver 4b is provided for these bits, which carries out a desired rearrangement.
  • FIG. 5 shows a further exemplary embodiment of the present invention for an effective code rate Ce in the range 1/3 ⁇ Ce ⁇ 0.5.
  • mapping device 19 In contrast to FIG. 4, two mapping devices 19, 20 are provided.
  • mapping device 20 to which the second parity bits P2 are supplied, executes the mapping algorithm explained above with the following parameters:
  • mapping devices 19, 20 each deliver two output bit streams yl, y2, as described above, the first output bit stream yl being supplied to the mapping device 19 of a rate adjustment device 21 which supplies the corresponding bits to the rate adjustment algorithm described above with the following parameters subjects:
  • the first output bit stream y1 of the mapping device 20, on the other hand, is fed to a rate adjustment device 22, which subjects the corresponding bits to the rate adjustment algorithm with the following parameters:
  • the output bits of the two rate adjustment devices 21, 22 are combined by a multiplexer 25 to form a common data stream and fed to the interleaver 4b for reordering and mapping to the bit positions of the modulator 5 with low reliability.
  • the second output bit streams y2 of the mapping devices 19, 20, on the other hand, are fed together with the systematic bits S to a multiplexer 23, which generates a common data stream therefrom, a device 24 subsequently removing all bits with the fill value ⁇ before the remaining bits the interleaver 4a for temporal rearrangement and mapping to the bit positions with high reliability of the modulator 5 are supplied.
  • FIG. 6 shows a further exemplary embodiment of the present invention for an effective code rate Ce ⁇ l / 3.
  • This exemplary embodiment largely corresponds to the exemplary embodiment shown in FIG. 5, but an additional rate adjustment device 26 is provided for the systematic bits S, which performs the rate adjustment algorithm with the following parameters:
  • the bits selected by the rate adaptation algorithm are not punctured, but repeated.
  • the two rate adjustment devices 21, 22 also perform bit repetition, the rate adjustment device 21 using the following parameters:
  • the rate adjustment device 22 uses the following parameters according to FIG. 6:
  • the mapping algorithm of the mapping device 19 is carried out with the following parameters:
  • the mapping device 20 executes the mapping algorithm with the following parameters:
  • bits output by the interleaver 4a are mapped to symbols or bit positions of the 16QAM modulator 5 with high reliability, while the bits output by the interleaver 4b to the less well protected bit positions are mapped with low reliability.
  • FIGS. 5 and 6 can also be modified in such a way that the function blocks 19 and 21 or the function blocks 20 and 22 are interchanged. Integration of the function blocks 21 and 22 into the function blocks 19 and 20 is also possible.
  • turbo encoder outputs the bits to be output in the sequence S (1), PICL), P2 (1), S (2), Pl (2), P2 (2), ...
  • S (i) or Pl (i) or P2 (i) denotes the systematic bit no. i or the parity bit no. i of the first or second parity bit stream.
  • S (i) or Pl (i) or P2 (i) denotes the systematic bit no. i or the parity bit no. i of the first or second parity bit stream.
  • the rate adjustment algorithm in step 202 can be the same algorithm as described above or in the currently valid specification of UMTS. However, different sets of parameters for the variables e, ei n i, e m i nus and e p ⁇ us are used for each class of bits. This can be easily achieved if these parameters are provided with an index that designates the class of the bits currently being processed. This corresponds to the parameter b already introduced.
  • the mapping algorithm in step 203 can also be the same algorithm as already described above.
  • different sets of parameters for the variables e, eini, e m i nU s and e p ⁇ us are used for each class of bits. This can be easily achieved in an analogous manner if these parameters are provided with an index which denotes the class of the bits just processed, which in turn corresponds to the parameter b already introduced.
  • Output bit streams are defined for each class of input bits. If only one output bit stream is assigned to a class, all bits of this class are output to this output bit stream. If two output bit streams are assigned to a class, the bits are divided between the two output bit streams according to the mapping algorithm presented above.
  • the value ⁇ is not necessary to use the value ⁇ as the “fill value”. Since the bits are processed sequentially, not in blocks, it is ensured a priori that the bits get into the output bit streams in the correct order.
  • the algorithm can also be expanded to more than two output bit streams, for example by using several selection processes. be carried out consecutively. However, this will rarely be necessary (unless there are so many bits in a class that more than two output bit streams must be used).
  • the rate adjustment process and the mapping process are carried out independently of one another. However, this does not have to be optimal in all cases. Rather, it can be advantageous to carry out the two algorithms as a function of one another. For example, consider the case where a class of bits must both be punctured and split across two different output bit streams. With uncoordinated execution it can happen that in the vicinity of a punctured bit another bit is output on an output bit stream of low reliability. Both bits are thus less well protected than those bits which are output (unpunctured) on the output bitstream with high reliability. It would be more beneficial to ensure that such an unfavorable encounter is avoided.
  • the mapping algorithm additionally processes information relating to the puncturing that has already been carried out, whereby in the vicinity of a puncturing an assignment to the less reliable output bit current should be avoided if possible.
  • the rate adjustment algorithm additionally processes information relating to the mapping carried out in the environment, puncturing being avoided as far as possible in the vicinity of an assignment to the less reliable output bit stream.
  • the influence of the puncturing is often more serious than the influence of the assignment. In these cases, this variant will tend to work less well than variant 1).
  • the rate adjustment algorithm and the mapping algorithm are preferably combined in a single algorithm or several algorithms.
  • This algorithm first selects bits that are "weakened”, either by puncturing or by assignment to the less reliable output bit stream.
  • a decision is then made as to which of these two alternatives should be carried out.
  • After (or before) puncturing, but especially between two successive puncturing a larger distance is left than after (o- before) an assignment, in particular between two assignments, to the less reliable output bit stream.
  • the importance of the bits in the vicinity of punctured bits is increased in order to avoid that many bits are mapped or badly mapped to bad positions in this area It is thus achieved that bits are assigned to the reliable output or output bitstream are mapped.
  • variant 1 Another exemplary embodiment of variant 1 is described below. It is particularly relevant for code rates between 0.5 and 1.
  • the parity bits are punctured relatively heavily (more than half of the parity bits are punctured) and some of the systematic bits are mapped to the less reliable output bit stream, although most systematic bits are assigned to the more reliable output bit stream.
  • the puncturing pattern of the parity bits Pl and the mapping pattern of the systematic bits S Both are used in the first, third, fifth ... half-iteration of the turbo decoder, again with no weakening due to punctured parity bits Pl and associated systematic Bits S should accumulate in certain places. Extensive simulations have shown that the following procedure gives good results: the standard puncturing algorithm is used for the puncturing.
  • the mapping algorithm but performed as follows:
  • the error parameter e is not reduced at every systematic bit to the value e m i nus, but only if a parity bit Pl, that is, a parity bit of the first parity tuschbitstroms Pl, is not punctured. If e is less than 0 in the subsequent systematic bit, this bit is assigned to the less reliable output bit stream and e increased by e p i us , otherwise this bit is assigned to the more reliable output bit stream.
  • the (first) output bit stream provided by default or by default for bit mapping is denoted by stream (b), while the alternative (second) output bit stream is denoted by
  • Stromalt (b) is designated.
  • Mapping parameters emap and emapminus are used in the course of the mapping algorithm, emapminus being used in step 308 to reduce emap.
  • either parts of the systematic bits are output on the less reliable output bit stream or parts of the parity bits are mapped on the more reliable output bit stream. This is achieved by suitable selection of all "e” parameters and by selection of the appropriate bit stream for the respective mapping step.
  • All of the exemplary embodiments described above have in common that either parts of the systematic bits correspond to the bit stream which is fed to the interleaver 4b and is mapped to bit positions with lower reliability, and / or parts of the parity bits to the bit stream which is fed to the interleaver 4a and with bit positions higher reliability is mapped.
  • the assignment or reordering patterns used for this purpose are not chosen to be constant, but are changed in a data-packet or even bit-specific manner. This can be done by appropriately adapting the parameters in the above algorithms, in particular, for example, the parameters can be ei n i data frame or changed bitspezifisch or selected.
  • rate adjustment algorithms can also be used and combined with the mapping algorithm as already described.
  • these rate adjustment algorithms can also be operated without a combination with the mapping algorithm and can therefore be used advantageously by and with a person skilled in the art with and without the use of a mapping algorithm.
  • two types of rate adjustment algorithms can be distinguished: in the first case, at least all systematic bits are transmitted, and as much parity bits as there is still space in the transmission packet afterwards. This results in a so-called self-decodable redundancy version, i.e. the data sent can be reconstructed (at least if there are not too many transmission errors) from a single such redundancy version.
  • Another type of rate adjustment algorithm works as follows (although in the following description no longer differentiates between parity and systematic bits it is applicable for both cases): First, a set of candidates is selected from all bits. In a second step, the bits to be transmitted are then selected from these candidates. This is particularly advantageous if the receiver does not have so much memory that it can store all possible bits (or their received values), but only a smaller number. The number of candidates is then selected according to this number, thus ensuring that even in the sum of several transmissions, no more than this number of different bits can be transmitted. This ensures that the receiver can actually store all of the transmitted bits and thus take them into account.
  • Such a selection process is shown by way of example in FIG. 10.
  • the easiest way to select the candidates is to use an algorithm that is structured like one of the rate adjustment algorithms mentioned above, as is to select the redundancy version. However, this selection is not optimal, as can be seen in the following example, see also FIG. 11. Assume that the total number of bits to be transmitted is 24 (top line of FIG. 11), the number of candidates or the memories of the receiver is 6 and in a redundancy version 4 bits should be selected. The 6 candidates can be selected with the same spacing (X in the middle line), but the 4 bits to be transmitted cannot, the rate adjustment algorithm then selects 4 bits that are as equally spaced as possible, resulting in those marked with x in the third line of FIG. 11 bits.
  • a less than optimal coding or selection of the data for the second or a further redundancy version will therefore not be particularly disadvantageous in practice.
  • the selection algorithm for the first redundancy version must be optimized. It must also be taken into account that the first redundancy version can often only send a small number of parity bits, since all systematic bits must be sent. Since a large proportion of the parity bits must be punctured (typically up to 5/6), it is particularly important to distribute the few remaining parity bits as evenly as possible. In the following redundancy versions, significantly more parity bits can typically be sent, since no systematic bits have to be sent. With these many bits, minor irregularities in the distribution pattern are not as serious.
  • Variant b can also be generalized to the effect that both the first selection algorithm for the selection of the candidates and therefore also the second selection algorithm are modified.
  • the first selection algorithm expediently selects bits optimized for the first redundancy version and likewise fills the spaces as evenly as possible.
  • the second selection algorithm selects the bits for a (in particular the first) redundancy version from the candidates.
  • an algorithm based on the calculation of an error value e can be used, as has already been described above in several variants:
  • the error value e is starting at eini in each case by a predetermined value e m _. nus ER- low, if e becomes less than 0, a bit is either punctured or selected and the error value increased by e p ⁇ us .
  • This algorithm can be adapted so that e is not reduced by the same value e m i nu s for each candidate, but by a value that is proportional to the number of bits in the original bit stream between two candidates. If the selection of the candidates and the selection of a redundancy version are carried out at the same time, e can be reduced by a value e'minus for each bit of the original total current. This allows an inexpensive implementation without the need to store the number of original bits between two candidates in the transmitter or receiver.
  • a particularly simple to implement embodiment provides that the number of candidates is not necessarily chosen to be the maximum (that is, corresponding to the storage capacity of the recipient). Instead, the number of candidates is chosen so that it is in a simple ratio to the number of bits selected for the first redundancy version.
  • a simple ratio (and thus a preferred exemplary embodiment) is, for example, the case where the number of candidates is a multiple of the number of bits selected for the first redundancy version.
  • the rate adjustment algorithm which selects the bits for the first redundancy version from the candidates, can then make a strictly regular selection (e.g. every 4th bit), which makes the resulting pattern as regular as possible again (there are only one or two possible intervals between adjacent selected bits, and the distribution of any two distances is even).
  • the number of candidates should be divisible by 10. If the recipient actually has space for 45 reception values, only 40 candidates should still be used. Although the reduced number of If candidates have a deterioration in the transmission characteristics for a later redundancy version, this is more than compensated for by the improvement of the transmission characteristics for the first redundancy version, since the first redundancy version has a greater influence on the overall performance of the system.
  • a further simple ratio is the case in this context that the number of candidates is in a simple division ratio to the number of bits selected for the first redundancy version. This allows the use of more candidates, but at the expense of the performance of the first redundancy version.
  • One possible compromise is to use the simplest possible division ratio, in which the difference between the number of
  • the receiver knows the number of bits selected for the first transmission. This is usually a reasonable assumption. Although it may be that the receiver does not receive the first transmission and therefore these parameters due to transmission errors, the sender (since he learns of this fact from the HARQ protocol) should again send a "first" transmission (ie a self-decodable packet) , since it makes no sense to send a packet that is not self-decodable.
  • This second “first” transmission packet means that the receiver now knows the number of bits selected for the first transmission.
  • the currently valid number of for the first transmission selected bits are also explicitly communicated to the receiver.
  • a typical number can be used instead of the currently valid number of bits selected for the first transmission. This typical number can be differentiated depending on the type of modulation and, if necessary, the type of coding. Since the type of modulation and possibly coding must be communicated to the receiver anyway, this does not result in any increased signaling requirements; in the event of a connection being established, these typical numbers must also be transmitted once.
  • FIG. 14 Another quite different rate adjustment algorithm is shown in FIG. 14.
  • the bits of a class (systematic, party 1 and / or parity 2) are written into an interleaver (scrambler), which outputs the bits in a different order.
  • a block of bits with the desired number is then selected from this stream. This selection is represented by the horizontal arrows, which each select a block of bits from the interleavers (after scrambling).
  • Different block sizes can also be selected from different interleavers.
  • Parity 1 and 2 bits can either be written in separate interleavers or in a common interleaver.
  • the interleaver is intended to ensure that by selecting a block after the interleaver, bits that are as evenly distributed as possible are selected in front of the interleaver. In this concept, however, since the interleaver is the same for every possible number of selected bits, it cannot be optimal for every possible number. According to a preferred embodiment, the interleaver is optimized especially for a particularly relevant case of the number of bits to be selected. For example, for an HSDPA connection ("High Speed Downlink Packet Access") in UMTS mobile radio systems, in particular coding questions of% or% are proposed (depending on the channel properties). The As a result, the party bits are transmitted 50% of the time the first packet is transmitted, or only a sixth of the parity bits.
  • HSDPA connection High Speed Downlink Packet Access
  • the interleaver for the parity bits would therefore be selected such that the bits in the first sixth of the interleaver are distributed as evenly as possible.
  • this block there could be bits with the index in the original order of k * 6 + kO, where k passes through the values 1, 2, 3 ... and kO is a constant from the set 0,1,2,3,4 , 5 is. In the particularly relevant case, this ensures that an optimal bit selection is carried out.
  • the bits in the first half can be chosen as j * 2 + jO, where j passes through the values 1, 2, 3 ...
  • An embodiment variant of such an interleaver consists in writing the bits in columns, then exchanging the lines of the interleaver according to a predetermined exchange rule, and then reading out the bits line by line (if necessary, additional exchanges can be made, for example within a line) Interleavers can then be determined by the exchange rule.
  • bits with the result Index 0 + i * 30, 20 + i * 30, 10 + i * 30, 5 + i * 30, 15 + i * 30, ordered this gives the bits with the index 0, 5, 10, 15, 20, 30 , 35, 40, 45, 50, 60, ...
  • the column swapping operation is divided into 5 groups, each with 6 elements.
  • a better choice would be a division into 6 groups, each with 5 elements, because then if 1/6 of the bits were selected, which corresponds to the first 5 lines, a group would be completely selected.
  • This first group should contain the elements 0, 6, 12, 18, 24 in any order, the subsequent groups would then also contain 5 elements, within a group all elements have the same remainder when divided by 6
  • the elements within a group can still be permuted as desired, so that a better distribution can be achieved if the selection rate differs from 1/6.
  • the first 3 groups should also contain even and the following 3 groups odd elements.
  • the first group is 0, 12, 24, 6, 18, the following groups emerge from this group by adding the values 4, 2, 1, 5 and 3 to the corresponding elements of the first group.
  • the properties of interleavers which are used according to the rate adjustment algorithm and the mapping algorithm, are described below. These interleavers are therefore different from the interleaver just described, which can be used as parts of a rate adjustment algorithm. If both interleavers are to be used, the rearrangement operation of the interleaver just described can also be undone, so that only the effect of the rate adjustment remains.
  • the two interleavers 4a, 4b are preferably designed such that they distribute adjacent or closely spaced input bits as well as possible within the frame to be sent (“frame” or TTI).
  • frames or TTI
  • those bits that are within the so-called influence length of the constituent convolutional code used for the channel or turbo encoder 2 should be distributed as evenly as possible in order to utilize the maximum time diversity ("time diversity").
  • bits that are close to each other, which get into the different interleavers 4a, 4b, should be distributed as well as possible.
  • the interleavers 4a, 4b should be designed differently, since otherwise, for example, two adjacent bits, one of which is fed to the interleaver 4a and one to the interleaver 4b, would be distributed again to successive positions.
  • this is undesirable for reasons of transmission security and transmission quality, since both bits are affected, for example, when poor channel properties or high noise levels occur, particularly during the transmission of the two corresponding symbols.
  • Such decoding errors can, however, be corrected by decoders more poorly than errors which occur in a distributed manner. Therefore, there is basically also the need for interleaver structures, which can be used to achieve good transmission quality and transmission security when applying the previously explained invention.
  • the bits are to be mapped to the corresponding modulation symbols in a suitable manner.
  • the bits of the interleaver 4a, 4b are output after a parallel / serial conversion in the order HHLL, since each modulation symbol has two bits with high reliability and two bits with lower Reliability.
  • the bits are output in the order HLHL, i.e.
  • bits of the interleaver 4a which are to be mapped on bit positions of the modulation symbols with high reliability
  • bits of the interleaver 4b which are to be mapped on bit positions of the modulation symbols with low reliability, are alternately output. Sorting according to the HLHL scheme is easier to process, since only even positions and odd positions need to be distinguished. With the conventional HHLL scheme, on the other hand, four different positions in blocks of four bits each have to be distinguished.
  • Interleavers that are easy to implement are block interleavers, into which data is written line by line and read out column by column.
  • interleavers are problematic in the implementation of the invention, since consecutive bits would then also be output consecutively.
  • this problem can be avoided if the data or bits are read out offset from the second interleaver.
  • the first bit of the second interleaver output does not correspond to the first bit written into this interleaver, but rather to a bit shifted by a certain number of sets. With a suitable choice of the offset, very good nesting can thus be achieved.
  • the position of the first output bit of the second interleaver is selected such that it lies as precisely as possible in the middle between the bits of the first interleaver closest in the order of writing.
  • FIG. 7 A corresponding example is shown in FIG. 7.
  • the diagram shows the bits horizontally when writing into the corresponding interleaver and vertically the order when reading them out, with bits 27 of the first interleaver having a Check and the bits 28 of the second interleaver are shown with a square.
  • the first bit of the second interleaver output and the two closest bits of the first interleaver are optimally shifted from one another, ie the (read) position of the first bit of the second
  • the interleaver lies exactly in the middle of the (read) positions of the two bits of the first interleaver closest in the order of writing.
  • the optimization criterion for a suitable combination of two identical interleavers is different in the case of interleavers with interchanged columns than when using block interleavers.
  • the column swapping operation distributes successive bits much better. However, since the bits are distributed over the entire area, there are no "unoccupied" areas into which the output of the second interleaver could be shifted, as is possible with a block interleaver. Rather, in the optimal output of the second interleaver, the special selected column swapping operation are taken into account. The best displacement can then be determined by examining all possible displacements, the following displacement parameters being available:
  • the first bit written in the second interleaver does not necessarily have to be written in the first column of the second interleaver, but can alternatively also be written in any other column, in which case the remaining columns are described cyclically starting with this column.
  • the first bit of the second interleaver to be read out does not necessarily have to be read out from the first line, but can alternatively also be read out from every other line of the second interleaver, the other lines then being read out cyclically starting with this line. In this case, such a shift in writing and reading out is equivalent, since in the interleavers under consideration there are generally no line swaps.
  • FIG 8 shows an exemplary embodiment for a "horizontal" shift by three columns when writing into the second interleaver (variant (i)) and a "vertical” shift by 15 rows (variant (iii)).
  • the diagram shows the position horizontally (ie along the x-axis) of the bits when writing into the interleaver and vertically (ie along the y-axis) their position when reading out. For each bit, the corresponding position is also indicated next to the corresponding bit when writing to the interleaver, with only the first 120 bits which are written to the interleaver being shown for better illustration.
  • the above-described shift operation is indicated by an arrow in FIG. 8.
  • Another variant of the generation of two optimally coordinated interleavers 4a, 4b is to use different, but coordinated, column swapping operations for both interleavers 4a, 4b.
  • bit interleavers with column swapping as has already been explained - the bits are written line by line and the columns are then exchanged according to a predetermined scheme, whereby according to one embodiment of the invention, even columns are exchanged only with even columns and odd columns only with odd columns.
  • the bits are then read out in the following order: the first bit of the first column, the first bit of the second column, the second bit of the first column, the second bit of the second column, then alternately one bit each of the first and second columns to these have been completely read out, then analogous reading of the third and fourth columns etc.
  • This process is equivalent to the use of two interleavers with different column swapping, but each time a column swapping is sought which, provided that only even columns and odd columns can be swapped, achieves the best possible scrambling or distribution of the bits.
  • a column swapping scheme that meets these conditions can be obtained, for example, by starting with a conventional column swapping scheme without the restriction regarding the prescribed swapping of the even and odd columns.
  • Such a conventional column swapping scheme is shown in the first row of Figure 9, with the columns numbered 0. If, in this conventional column swapping scheme, an odd column were exchanged for an even column or vice versa, an adjacent column or a column close to it could simply be used instead. The result of this operation is shown on the second line of FIG. 9, with the changes made compared to the first line of FIG. 9 being highlighted in bold. If this results in unfavorable conditions, you can try to improve this by swapping the columns. A corresponding one
  • the exemplary embodiment is shown in the third line of FIG. 9, with changes in relation to the second line of FIG. 9 again being highlighted in bold.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

Selon l'invention, les bits à transmettre dans un système de communication sont soumis à un codage de canal et transformés en bits systématiques (S) et en bits de parité (P1, P2), puis ils sont représentés pour la transmission sur des symboles de modulation, par exemple d'un modulateur 16QAM (5). Les bits systématiques (S) sont représentés sur des positions binaires des symboles de modulation (13) avec une fiabilité élevée, et, si le nombre des positions binaires présentant une fiabilité élevée n'est pas suffisant, ils sont représentés sur des positions binaires d'une plus faible fiabilité, tandis que les bits de parité (P1, P2) sont représentés sur les positions binaires restantes, de fiabilité plus faible, après exécution correspondante d'une adaptation de débit binaire (15, 16; 21, 22) par rapport aux bits de parité (P1, P2).
PCT/DE2001/004105 2001-10-15 2001-10-30 Procede et dispositif pour representer la base de depart d'un codeur dans l'espace signal d'une modulation qam ou psk Ceased WO2003039055A1 (fr)

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WO2018119883A1 (fr) 2016-12-29 2018-07-05 Qualcomm Incorporated Structure imbriquée pour construction de code polaire utilisant une évolution de densité

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Cited By (10)

* Cited by examiner, † Cited by third party
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EP1564954A3 (fr) * 2004-02-12 2007-09-05 Fujitsu Limited Dispositif de transmission avec procédé d'arrangement de bits
CN100514900C (zh) * 2004-02-12 2009-07-15 富士通株式会社 使用比特排列方法的传输装置
US7860186B2 (en) 2004-02-12 2010-12-28 Fujitsu Limited Transmitting apparatus with bit arrangement method
EP2293509A1 (fr) * 2004-02-12 2011-03-09 Fujitsu Limited Dispositif de transmission avec procédé d'arrangement de bits
US7965791B2 (en) 2004-02-12 2011-06-21 Fujitsu Limited Transmitting apparatus with bit arrangement method
EP2375667A1 (fr) * 2004-02-12 2011-10-12 Fujitsu Limited Dispositif de transmission avec procédé d'arrangement de bits
EP2381636A1 (fr) * 2004-02-12 2011-10-26 Fujitsu Limited Dispositif de transmission avec procédé d'arrangement de bits
US8077800B2 (en) 2004-02-12 2011-12-13 Fujitsu Limited Transmitting apparatus with bit arrangement method
US8085872B2 (en) 2004-02-12 2011-12-27 Fujitsu Limited Transmitting apparatus with bit arrangement method
US8213535B2 (en) 2004-02-12 2012-07-03 Fujitsu Limited Transmitting apparatus with bit arrangement method

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