WO2003038832A1 - Semiconductor storage device - Google Patents

Semiconductor storage device Download PDF

Info

Publication number: WO2003038832A1
Authority: WO; WIPO (PCT)
Prior art keywords: standby mode; output; switched; circuit; deep
Prior art date: 2001-10-16
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Ceased

Application number

PCT/JP2002/010764

Other languages

English (en)

French (fr)

Inventor

Hiroyuki Takahashi

Atsushi Nakagawa

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Electronics Corp

Original Assignee

NEC Electronics Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2001-10-16

Filing date

2002-10-16

Publication date

2003-05-08

2002-10-16 Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp

2002-10-16 Priority to US10/492,765 priority Critical patent/US6879537B2/en

2003-05-08 Publication of WO2003038832A1 publication Critical patent/WO2003038832A1/ja

2004-04-16 Anticipated expiration legal-status Critical

Status Ceased legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4068—Voltage or leakage in refresh operations

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Dram (AREA)

PCT/JP2002/010764 2001-10-16 2002-10-16 Semiconductor storage device Ceased WO2003038832A1 (en)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
US10/492,765 US6879537B2 (en)	2001-10-16	2002-10-16	Semiconductor storage device having a plurality of operation modes

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP2001318658A JP4262912B2 (ja)	2001-10-16	2001-10-16	半導体記憶装置
JP2001-318658		2001-10-16

Publications (1)

Publication Number	Publication Date
WO2003038832A1 true WO2003038832A1 (en)	2003-05-08

Family

ID=19136321

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
PCT/JP2002/010764 Ceased WO2003038832A1 (en)	2001-10-16	2002-10-16	Semiconductor storage device

Country Status (5)

Country	Link
US (1)	US6879537B2 (ja)
JP (1)	JP4262912B2 (ja)
CN (1)	CN100446123C (ja)
TW (1)	TWI270074B (ja)
WO (1)	WO2003038832A1 (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP4147087B2 (ja) *	2002-10-29	2008-09-10	株式会社ルネサステクノロジ	情報処理通信装置
JP2005222581A (ja) *	2004-02-03	2005-08-18	Renesas Technology Corp	半導体記憶装置
KR100600331B1 (ko) *	2005-05-30	2006-07-18	주식회사 하이닉스반도체	연속적인 버스트 모드로 동작 가능한 슈도 ｓｒａｍ
JP4745782B2 (ja) *	2005-10-05	2011-08-10	エルピーダメモリ株式会社	半導体記憶装置
US7453758B2 (en) *	2006-02-21	2008-11-18	Infineon Technologies Ag	Control system for a dynamic random access memory and method of operation thereof
US8102700B2 (en) *	2008-09-30	2012-01-24	Micron Technology, Inc.	Unidirectional spin torque transfer magnetic memory cell structure
US8612809B2 (en)	2009-12-31	2013-12-17	Intel Corporation	Systems, methods, and apparatuses for stacked memory
KR20130015941A (ko) *	2011-08-05	2013-02-14	에스케이하이닉스 주식회사	내부전압생성회로
US8605489B2 (en) *	2011-11-30	2013-12-10	International Business Machines Corporation	Enhanced data retention mode for dynamic memories
JP6020076B2 (ja) *	2012-11-16	2016-11-02	株式会社ソシオネクスト	インタフェース回路及び半導体装置
US9361972B1 (en) *	2015-03-20	2016-06-07	Intel Corporation	Charge level maintenance in a memory
CN106710622A (zh) *	2015-07-22	2017-05-24	上海华虹集成电路有限责任公司	自主调节的电荷泵系统
KR20190029307A (ko) *	2017-09-12	2019-03-20	에스케이하이닉스 주식회사	메모리 시스템 및 이의 동작방법
US11894041B2 (en) *	2020-12-01	2024-02-06	SK Hynix Inc.	Electronic devices executing refresh operation based on adjusted internal voltage

Citations (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH0519914A (ja) *	1991-07-17	1993-01-29	Sharp Corp	半導体装置の内部降圧回路
JPH0620471A (ja) *	1992-06-30	1994-01-28	Hitachi Ltd	ダイナミック型ｒａｍ
JPH08279285A (ja) *	1995-02-08	1996-10-22	Matsushita Electric Ind Co Ltd	半導体記憶回路のデータ保持時間の延長装置及び延長方法
JPH08306185A (ja) *	1995-04-26	1996-11-22	Samsung Electron Co Ltd	半導体メモリ装置の電源電圧発生回路
JPH10201222A (ja) *	1996-12-27	1998-07-31	Fujitsu Ltd	昇圧回路及びこれを用いた半導体装置
JP2001184865A (ja) *	1999-12-21	2001-07-06	Fujitsu Ltd	半導体記憶装置
JP2001344971A (ja) *	2000-05-30	2001-12-14	Mitsubishi Electric Corp	Ｄｒａｍ搭載半導体集積回路装置
JP2002170383A (ja) *	2000-11-30	2002-06-14	Fujitsu Ltd	半導体記憶装置及び半導体装置
JP2002373490A (ja) *	2001-06-15	2002-12-26	Mitsubishi Electric Corp	半導体記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS615495A (ja)	1984-05-31	1986-01-11	Toshiba Corp	半導体記憶装置
JPS62188096A (ja)	1986-02-13	1987-08-17	Toshiba Corp	半導体記憶装置のリフレツシユ動作タイミング制御回路
JP2529680B2 (ja)	1987-02-23	1996-08-28	沖電気工業株式会社	半導体メモリ装置
JPH04243087A (ja)	1991-01-18	1992-08-31	Matsushita Electric Ind Co Ltd	ランダムアクセスメモリーのリフレッシュ装置及びそれを用いたコンピューター装置
JP2863042B2 (ja)	1992-07-17	1999-03-03	シャープ株式会社	ダイナミック型半導体記憶装置
TW306001B (ja) *	1995-02-08	1997-05-21	Matsushita Electric Industrial Co Ltd
JP3367519B2 (ja)	1999-12-03	2003-01-14	日本電気株式会社	半導体記憶装置及びそのテスト方法
JP4707244B2 (ja) *	2000-03-30	2011-06-22	ルネサスエレクトロニクス株式会社	半導体記憶装置および半導体装置
JP4707803B2 (ja) *	2000-07-10	2011-06-22	エルピーダメモリ株式会社	エラーレート判定方法と半導体集積回路装置

2001
- 2001-10-16 JP JP2001318658A patent/JP4262912B2/ja not_active Expired - Fee Related
2002
- 2002-10-16 CN CNB028222938A patent/CN100446123C/zh not_active Expired - Fee Related
- 2002-10-16 US US10/492,765 patent/US6879537B2/en not_active Expired - Fee Related
- 2002-10-16 WO PCT/JP2002/010764 patent/WO2003038832A1/ja not_active Ceased
- 2002-10-16 TW TW091123881A patent/TWI270074B/zh not_active IP Right Cessation

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH0519914A (ja) *	1991-07-17	1993-01-29	Sharp Corp	半導体装置の内部降圧回路
JPH0620471A (ja) *	1992-06-30	1994-01-28	Hitachi Ltd	ダイナミック型ｒａｍ
JPH08279285A (ja) *	1995-02-08	1996-10-22	Matsushita Electric Ind Co Ltd	半導体記憶回路のデータ保持時間の延長装置及び延長方法
JPH08306185A (ja) *	1995-04-26	1996-11-22	Samsung Electron Co Ltd	半導体メモリ装置の電源電圧発生回路
JPH10201222A (ja) *	1996-12-27	1998-07-31	Fujitsu Ltd	昇圧回路及びこれを用いた半導体装置
JP2001184865A (ja) *	1999-12-21	2001-07-06	Fujitsu Ltd	半導体記憶装置
JP2001344971A (ja) *	2000-05-30	2001-12-14	Mitsubishi Electric Corp	Ｄｒａｍ搭載半導体集積回路装置
JP2002170383A (ja) *	2000-11-30	2002-06-14	Fujitsu Ltd	半導体記憶装置及び半導体装置
JP2002373490A (ja) *	2001-06-15	2002-12-26	Mitsubishi Electric Corp	半導体記憶装置

Also Published As

Publication number	Publication date
US20050007851A1 (en)	2005-01-13
CN1585985A (zh)	2005-02-23
JP4262912B2 (ja)	2009-05-13
JP2003123468A (ja)	2003-04-25
TWI270074B (en)	2007-01-01
US6879537B2 (en)	2005-04-12
CN100446123C (zh)	2008-12-24

Publication	Publication Date	Title
WO2003038832A1 (en)	2003-05-08	Semiconductor storage device
US5844435A (en)	1998-12-01	Low power, high accuracy clock circuit and method for integrated circuits
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CN102570973B (zh)	2014-11-19	时钟系统以及用于时钟系统的方法
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WO2002069344A3 (en)	2003-05-15	Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
KR940022853A (ko)	1994-10-21	다이나믹형 ram
TW200629700A (en)	2006-08-16	Switching regulator
KR960702640A (ko)	1996-04-27	장치에서 전력 제어를 위한 방법 및 기구(method and apparatus for power control in devices)
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JP3577347B2 (ja)	2004-10-13	集積回路及びその動作を制御する方法
JPS62219839A (ja)	1987-09-28	起動制御方式
GB961846A (en)	1964-06-24	Timing circuit for defining long intervals of time
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JP2002099332A (ja)	2002-04-05	多電圧直流電源装置
KR970071813A (ko)	1997-11-07	딥 파워 다운 제어회로
US8248119B2 (en)	2012-08-21	Low power frequency divider and low power phase locked loop including the same

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2003-07-24	DFPE	Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
2004-04-16	WWE	Wipo information: entry into national phase	Ref document number: 10492765 Country of ref document: US
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