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WO2003034224A3 - Debug exception registers - Google Patents

Debug exception registers Download PDF

Info

Publication number
WO2003034224A3
WO2003034224A3 PCT/GB2002/004124 GB0204124W WO03034224A3 WO 2003034224 A3 WO2003034224 A3 WO 2003034224A3 GB 0204124 W GB0204124 W GB 0204124W WO 03034224 A3 WO03034224 A3 WO 03034224A3
Authority
WO
WIPO (PCT)
Prior art keywords
debug
debug exception
exception registers
processor
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2002/004124
Other languages
French (fr)
Other versions
WO2003034224A2 (en
Inventor
Nigel Peter Topham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PTS Corp
Original Assignee
PTS Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0124563.8A external-priority patent/GB0124563D0/en
Application filed by PTS Corp filed Critical PTS Corp
Publication of WO2003034224A2 publication Critical patent/WO2003034224A2/en
Publication of WO2003034224A3 publication Critical patent/WO2003034224A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3698—Environments for analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A processor is disclosed which comprises a debug handler (3) for handling a plurality of debug related events occurring within the processor (1). A debug flag (B) is provided for enabling and disabling the plurality of debug related events. The debug flag (B) is cleared if an exception is raised as a consequence of a debug event.
PCT/GB2002/004124 2001-10-12 2002-09-11 Debug exception registers Ceased WO2003034224A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB0124563.8A GB0124563D0 (en) 2001-10-12 2001-10-12 Debug exception registers
GB0124563.8 2001-10-12
GB0204499A GB2380831A (en) 2001-10-12 2002-02-26 Debug exception handler and registers
GB0204499.8 2002-02-26

Publications (2)

Publication Number Publication Date
WO2003034224A2 WO2003034224A2 (en) 2003-04-24
WO2003034224A3 true WO2003034224A3 (en) 2003-12-18

Family

ID=26246654

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/004124 Ceased WO2003034224A2 (en) 2001-10-12 2002-09-11 Debug exception registers

Country Status (1)

Country Link
WO (1) WO2003034224A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106250260B (en) * 2016-08-03 2019-07-23 北京小米移动软件有限公司 Processor overflows monitoring and adjustment method and device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530804A (en) * 1994-05-16 1996-06-25 Motorola, Inc. Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes
JPH09288595A (en) * 1996-04-19 1997-11-04 Matsushita Electric Ind Co Ltd Arithmetic processing unit
EP1089184A2 (en) * 1999-10-01 2001-04-04 STMicroelectronics, Inc. Microcomputer debug architecture and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530804A (en) * 1994-05-16 1996-06-25 Motorola, Inc. Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes
JPH09288595A (en) * 1996-04-19 1997-11-04 Matsushita Electric Ind Co Ltd Arithmetic processing unit
EP1089184A2 (en) * 1999-10-01 2001-04-04 STMicroelectronics, Inc. Microcomputer debug architecture and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 03 27 February 1998 (1998-02-27) *

Also Published As

Publication number Publication date
WO2003034224A2 (en) 2003-04-24

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