WO2003025683A1

WO2003025683A1 - High accuracy timing and jitter measurement system and methods

Info

Publication number: WO2003025683A1
Application number: PCT/CA2002/001438
Authority: WO
Inventors: Sassan Tabatabaei; Yong Luo; Purang Abolmaesumi; Mohammad Reza Sirouspour
Original assignee: Vector 12 Corp
Current assignee: Vector 12 Corp
Priority date: 2001-09-20
Filing date: 2002-09-20
Publication date: 2003-03-27
Anticipated expiration: 2004-03-20

Abstract

Methods and apparatus for measuring timing characteristics, such as jitter, in a signal use a vernier technique to take repeated measurements of time intervals in the signal. Multiple setsof measurements may be taken. In each set a time to digital converter is configured to completemeasurements in a different amount of time. Jitter in the time to digital converter and jitter in thesignal of interest can be independently computed.

Description

HIGH ACCURACY TIMING AND JITTER MEASUREMENT SYSTEM AND

METHODS

Cross-Reference to Related Application

[0001] This application claims the benefit of the filing date of U.S. patent application No. 60/324,101 filed on 20 September, 2001, which is hereby incorporated herein by reference.

Technical Field

[0002] The invention relates to methods and apparatus for timing signals. The invention may be applied to built-in self testing of high speed timing circuits and interfaces. The invention has application to jitter measurement.

Background

[0003] A time-to-digital converter (TDC) can be used to study the timing of a signal of interest. In a typical test, a series of time intervals defined between edges in a signal of interest are measured. The resulting data is processed to obtain results which characterize the signal. For example, the resulting data may be processed to obtain a value for the root mean square (RMS) jitter in the signal. To perform highly accurate jitter measurements, it is necessary to separate the effect of internal jitter in the TDC from the jitter in the signal being characterized.

[0004] Tabatabaei et al., PCT publication No. WO169328 discloses a time-to-digital converter (TDC). The TDC uses differences between the periods of two oscillators to make precise measurements of time intervals. At the start of a measurement, during a coarse measurement phase, the periods of the oscillators differ by a first, larger amount. During the measurement, a switching circuit causes the oscillators to switch to a fine state in which their periods differ by a second, smaller amount. The measurement is completed after a fine measurement phase. The result of the measurement is a number, N_c, of cycles of one of the oscillators during the coarse measurement phase and a number, N_F, of cycles of the oscillator during the fine measurement phase. [0005] If jitter in the TDC occurs randomly, the variance of jitter due to the TDC is proportional to the number of cycles of the oscillators needed to complete a time measurement. The jitter accumulates on the edges of the oscillator signals.

[0006] Tabatabaei et al. disclose that the number of cycles needed to complete a measurement of an interval can be varied by controlling the switching circuit. The internal jitter of the TDC may be estimated by taking two sets of measurements. Each set of measurements includes measurements made of a number of intervals. The first set of measurements is characterized by a ratio of the length of the coarse measurement phase to the length of the fine measurement phase. The second set of measurements is characterized by a different ratio of these quantities.

[0007] In each set of measurements, the numbers N_c and N_F are related to the length T_D of the interval by: T_D = N_cT_C + N_FT_F - T_c - T_R - T_Q (1) where:

T_ΔC is the difference in period of the oscillators during the coarse measurement phase; Tip is the difference in period of the oscillators during the fine measurement phase; T_c is an offset due to mismatches in the circuit of the TDC; T_R is an error term caused by relative jitter in the oscillators; and,

T_R is a term representing timing noise which arises due to the finite resolution of the TDC.

[0008] Assuming that the jitter is random, the jitter in the first set of measurements can be expressed as: σ ² = σ ² + σ ² (2) and the jitter in the second set of measurements can be expressed as:

^σn (3)

where: σ_n is the jitter in the measured values of T_D; σ_ris the jitter in the signal being measured; σ_R is internal jitter in the TDC; N₂ is N_C+N_F for the second set of measurements; and, Nj is N_C+N_F for the first set of measurements. .

The overbars in Equation (3) indicate average values.

The values for σ_τ and σ_R can be determined from Equations (2) and (3).

[0009] There is a general need for systems capable of making more accurate measurements of time intervals. There is a general need for systems capable of accurately measuring shorter time intervals as are found in high speed timing circuits.

Summary of the Invention

[0010] The invention relates to methods and apparatus for measuring signal characteristics. Timing noise, such as jitter may be measured by the methods of the invention.

[0011] One aspect of the invention provides a method for evaluating timing noise in a signal of interest. The method comprises: obtaining a first set of measurements for each of a plurality of intervals in the signal of interest. Each of the intervals begins at a first event and ends at a second event, for each of the intervals the method triggers a first oscillator upon the occurrence of the first event. The first oscillator subsequently produces a first output signal. The second oscillator is triggered upon the occurrence of the second event. The second oscillator subsequently produces a second output signal. When corresponding reference points in the first and second output signals have a first specified time relationship, the method reduces a difference between periods of the first and second oscillators. The method determines a number of cycles of the first output signal during a coarse measurement phase between the first oscillator being triggered and the corresponding reference points in the first and second output signals having the first specified time relationship. The method also determines a number of cycles of the first output signal in a fine measurement phase between the corresponding reference points in the first and second output signals having the first specified time relationship and the corresponding reference points in the first and second output signals having a second specified time relationship. The method computes a measure of timing noise in the signal of interest based at least in part upon the first set of measurements.

[0012] In some embodiments the method comprises obtaining at least second and third sets of measurements in substantially the same manner as the first set of measurements. For each of the second and third sets of measurements at least one of the first and second specified time relationships is different from the first and second relationships of the other sets of measurements. In such embodiments of the invention the measure of timing noise in the signal of interest is computed based upon the first, second and third sets of measurements.

[0013] Another aspect of the invention provides signal analysis apparatus comprising: first and second oscillators respectively configured to produce first and second output signals, the first and second oscillators having at least two states, wherein a difference between periods of the first and second output signals has a different value for each of the at least two states; a trigger circuit connected to cause the first oscillator to commence generating the first output signal on the occurrence of a first event and to cause the second oscillator to commence generating the second output signal on the occurrence of a second event; a first coincidence detector connected to detect when corresponding reference points of the output signals of the first and second oscillators have a first specified time relationship, the first coincidence detector configured to generate a first control signal causing the first and second oscillators to change to a state wherein the difference between the periods of the first and second oscillators is reduced; a counter connected to count periods of the output signal of the first oscillator at least until the first control signal is generated; a plurality of additional coincidence detectors each connected to detect when corresponding reference points of the output signals of the first and second oscillators have a different specified time relationship; and, a plurality of additional counters each connected to count periods of the output signal of the first oscillator until stopped by a signal originating from one of the additional coincidence detectors.

[0014] Further aspects of the invention and features of specific embodiments of the invention are described below.

Brief Description of the Drawings

[0015] In drawings which illustrate non-limiting embodiments of the invention,

Figure 1 is a block diagram of a time-to-digital converter according to one embodiment of the invention;

Figure 2 is a block diagram of a resolution switching control circuit which may be used in the time-to-digital converter of Figure 1;

Figure 3 is a schematic diagram of a coincidence detector which may be used in various embodiments of the invention; Figure 4 is a block diagram of a bank of coincidence detectors in a time quantizer circuit according to an alternative embodiment of the invention;

Figure 5 is a diagram illustrating the timing of different phases of operation of the time quantizer circuit of Figure 4;

Figure 6 is a more detailed schematic diagram of a time quantizer circuit having the general structure shown in Figure 4; and,

Figure 7 is a flow chart illustrating a method according to one embodiment of the invention.

Description [0016] Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense. [0017] This invention uses TDC apparatus similar to that disclosed in Tabatabaei et al., PCT publication No. WO169328, which is hereby incorporated herein by reference. The inventors have determined that the accuracy of interval measurements can be increased by using fine measurement intervals having more than two different lengths. For example, one may take four sets of measurements with each set of measurements characterized by a different fine measurement interval. The additional information available where there are three or more sets of measurements permits better separation between jitter in a signal being studied and jitter in the TDC.

[0018] Figure 1 is a block diagram showing major components of a TDC 10 according to the invention. Figure 7 illustrates a method which may be performed using TDC 10. TDC 10 comprises a first oscillator, 12A, and a second oscillator 12B. First oscillator 12A is connected to be triggered by a BEGIN signal. Second oscillator 12B is connected to be triggered by an END signal. A coincidence detector 14 is connected to receive output signals OSC_A and OSC_B from the first and second oscillators.

Coincidence detector 14 generates an end of conversion (EOC) signal when it detects a coincidence between the outputs of the first and second oscillators (OSC_A and OSC_B).

[0019] A resolution switching control circuit 16 is connected to receive output signals from the first and second oscillators. Resolution switching control circuit 16 has an output signal FINE CTRL. When resolution switching control circuit 16 detects that there is a coincidence between OSC B and a delayed version of OSC A, it changes the state of FINE CTRL. The change in state of FINE CTRL causes the difference in periods of oscillators 12A and 12B to change.

[0020] Counters 20C and 20F count features, such as edges, of OSC_A. Counter 20C counts features of OSC A until FINE CTRL changes state. Counter 20F counts the features of OSC A after FINE_CTRL changes state. A counter selector 18, which may comprise a multiplexer, determines whether OSC_A is counted by counter 20C or 20F. After each measurement, counter 20C contains a value N_c and counter 20F contains a value N_F.

[0021] By taking three or more sets of readings with a setting of resolution switching control circuit 16 different for each of the sets of readings, three or more sets of measurements may be made of the same input signal. Each set has a different ratio of the length of the coarse measurement phase to the length of the fine measurement phase. These sets of measurements may be processed, as described below to obtain various information about the input signal. For example, the sets of measurements may be processed to obtain information about jitter in the input signal or about the average lengths of measured intervals in the input signal.

[0022] In some cases a noise component in an input signal may be synchronized relative to a clock signal. To provide accurate measurements of jitter in such signals it can be important that the intervals measured in the input signal do not all have the same timing relationship to the clock signal. To ensure that this will be the case, a random delay 22 may be used to control the times at which intervals in the input signal are measured. In the illustrated embodiment, random delay 22 is triggered by the clock signal. After a random time period, random delay 22 generates a signal which arms edge sampler 21. Edge sampler 21 generates the BEGIN signal at a first edge of the input signal under test and generates the END signal at a second edge of the input signal.

[0023] Figure 2 shows a possible construction for resolution switching control circuit 16. Resolution switching control circuit 16 comprises a multiplexer 26 with a number of inputs (IN 1 to IN 4 in this example). Each input to multiplexer 26 receives a version of the output signal OSC_A from oscillator 12A which has been delayed by a different amount by one or more delays 24. In the example, there are four delays 24 A through 24D. The output from multiplexer 26 is provided to one input of a coincidence detector 28. The output signal OSC B from oscillator 12B is provided to the other input of coincidence detector 28. The output signal OSCJ3 may be delayed by a delay 24E before it is applied to the input of coincidence detector 28. Upon detecting a coincidence between the signals which are applied at its inputs, coincidence detector 28 changes the state of its output signal FINE_CTRL. The FINE_CTRL signal causes the period of oscillator 12A to change as described above.

[0024] Coincidence detector 28 (and/or coincidence detector 14) may be implemented as shown in Figure 3 using three flip flops 29A, 29B and 29C.

[0025] Figure 4 illustrates a time quantizer 29 according to an alternative embodiment of the invention. Time quantizer 29 receives output signals from first and second oscillators which may be triggered by events in a signal of interest as shown in Figure 1. Time quantizer 29 has one coarse counter 32C which counts cycles of OSC_A until FINE_CTRL changes state.

[0026] Time quantizer 29 also has four fine counters 32F-1 through 32F-4. The operation of fine counters 32F-1 through 32F-4 is controlled by coincidence detectors 30B through 30E which detect coincidences between versions of OSCJB delayed by delays 34A through 34D and OSC_A.

[0027] With RANGE_VALID initially in a logical "0" state, counter 32C is initially enabled and counts cycles of OSC A. When RANGE NALID changes to a logical "1" state and coincidence detector 30A detects a coincidence between OSC_B and OSC A, as delayed by delay 33 then gate 40 disables counter 32C. Counter 32C then stops counting. At this point, counter 32C contains a number N_c. Coincidence detector and delay 33 cause coarse counter 32C to stop counting some time before corresponding edges (i.e. the i* edges) of OSC B and OSC A coincide.

[0028] Counter 32F-1 is initially disabled. When counter 32C becomes disabled then counter 32F-1 becomes enabled and counts cycles of OSC A. Counter 32F-1 continues counting cycles of OSC A until coincidence detector 30B detects a coincidence between OSC_A and a version of OSC B delayed by delay 34A. [0029] Counters 32F-2 through 32F-4 are all initially disabled. When coincidence detector 30B detects a coincidence, and thereby disables counter 32F-1, counter 32F- 2 becomes enabled and begins to count. Counter 32F-2 continues counting until coincidence detector 30C detects a coincidence. When coincidence detector 30C detects a coincidence, and thereby disables counter 32F-2, counter 32F-3 becomes enabled and begins to count. Counter 32F-3 continues counting until coincidence detector 30D detects a coincidence. When coincidence detector 30D detects a coincidence, and thereby disables counter 32F-3, counter 32F-4 becomes enabled and begins to count. Counter 32F-4 continues counting until coincidence detector 30E detects a coincidence.

[0030] The coincidence detectors of time quantizer 29 may be implemented as shown in Figure 3. The counters of time quantizer 29 may be implemented as ripple counters.

[0031] Figure 5 is a timing diagram which illustrates the operation of the TDC of Figure 4. Counter 32C counts during the period Tl, Counters 32F-1 through 32F-4 respectively count during the periods T2 through T5. The value in counter 32F-1 is N_F for the fine measurement phase having a length τ_F1. N_F for fine measurement phases having durations τ_F2 through τ_F4may be obtained by adding together counts from counters which were enabled during the fine measurement phase. For example, the values in counters 32F-1 through 32F-3 may be added together to obtain a value of N_F corresponding to fine measurement phase τ_F3.

[0032] Figure 6 shows a possible implementation of a time quantizer constructed generally as shown in Figure 5. The signal rstb_DFF resets the flip flops which constitute coincidence detectors 30A through 30E. The signal rstb_cntr resets counters 32C and 32F-1 through 32F-4. The signal acc en enables the operation of time quantizer 27. [0033] It can be appreciated that time quantizer 29 can acquire several measurements simultaneously. The time quantizer illustrated in Figure 4 can acquire four measurements in a single cycle of operation While each measurement measures a different interval, the intervals measured by the different measurements differ from one another by constant offsets. These constant offsets do not affect variance computations. As shown in Figure 5, the intervals measured by the measurements overlap during the τ_c and partially overlap during τ_F (each measurement has a different value for τ_F). Four sets of measurements can be acquired by repeating the cycle of operation of quantizer 29.

[0034] The sets of measurements acquired by time quantizer 29 may be delivered by way of a suitable interface to a computer for further processing to yield information about the signal of interest. Where time quantizer 29 is on an integrated circuit die then the sets of measurements may be transferred to an external computer analysis system for processing. Time quantizer 29 and a circuit which generates the signal of interest may both be on the same integrated circuit.

[0035] There are a number of approaches which may be used to determine the jitter in a signal of interest and the jitter in a TDC apparatus given three or more sets of values N_c and N_F taken under different conditions, as described above. Some estimation techniques which may be applied in this context are described in Y. Bar-Shalom et al.

Tracking and Data Association, Academic Press, Boston, 1988; and L. Ljung System

Identification: Theory for the User, Prentice Hall, Upper Saddle River N.J., 1999, both of which are hereby incorporated herein by reference.

[0036] One approach is to perform a least squares estimation to obtain jitter information. Each set of values provides another equation in the form of Equation (3).

For example, where there are four different sets of measurements, one has the equations: σ ² = σ_T ² + σ ² (4) σ n. \ = CT_r + a_lσ_R (5)

• n2 = CΓ_T + a₂σ_R (6)

'«3 = c _τ + ₃σ_R (7)

The values for α in equations (5) to (7) are given by:

N_r + N_{Fl +}. ,.+ N Fi a_t = (8)

N_c + N_Fl

where N_FI is the value in counter 32F-1, Λ is the value in counter 32F-2; N_F3 is the value in counter 32F-3 and so on.

[0037] This set of equations can be expressed as a matrix relationship as follows:

Equation (9) does not have an exact solution, in general. However, there are many well known numerical techniques which may be applied to solve the system of equations represented in Equation (9). For example, a solution which minimizes

||7 — A #|| may be obtained by inverting A to yield:

θ_ls = (A^τAT¹A^τY (10) where θ_b is the vector containing the values for σ/ and σ_R predicted by the least squares computation; A^τ is the transpose of the matrix A of equation (9) and the superscript "-1" indicates inversion.

[0038] It can be appreciated that when the methods of the invention are performed using a time quantizer of the general type shown in Figure 1, then, the members of each set of measurements have a statistical behavior which obeys equation (2). For two such sets we have: σ_nl ² = σ_τι ² + σ_m ² (li)

and,

^σn = ^σT2 + ^aσR ⁽¹²⁾

If the sets of equations (11) and (12) were extremely large then σ_TJ and σ_n would be expected to be equal. However, for sets of reasonable sizes, there will be some differences between σ_n and σ^ because each is taken from a different set of period samples. This difference will propagate when solving equation (9) and cause some error in the results.

[0039] Where data is acquired in a time quantizer having a bank of coincidence detectors as shown in Figure 4 then equations (11) and (12) reduce to:

^σnx = < n + °m <¹³> and,

^σn2 = ^σn + ^σR2² <¹⁴⁾

because the same set of internal samples is used to determine σ_n in both sets of samples. Therefore, there is less statistical noise to affect the results of equations (13) and (14). This reduction in statistical noise is also obtained when more than two sets of measurements are taken. [0040] Measurements of jitter can be obtained to the same degree of precision with fewer sets of measurements made by the apparatus of Figure 4 than made by the apparatus of Figure 1. Furthermore, since several measurements with different values for v_fine are made simultaneously, the apparatus of Figure 4 can acquire sufficient data to make a jitter measurement having a desired accuracy much more quickly than can the apparatus of Figure 1, all other factors being equal.

[0041] Another method for obtaining estimated values of σ_τ ² and σ_R based on the observed sets of measurements is the maximum likelihood method. The maximum likelihood method is described, for example, in Proakis, Digital Communications (4th edition), McGraw Hill ISBN 007321113, which is hereby incorporated herein by reference. If one assumes that the jitter is a result of noise which has a particular distribution then one can define a probability function which expresses the probability that the observed sets of measurements would result from specific values of σ_τ ² , σj and f, where Tis the mean duration of the interval being measured and σ_υ is the RMS jitter of oscillators 12A and 12B.

[0042] Where, the distributions of input signal jitter and jitter in oscillators 12A and 12B are assumed to be Gaussian distribution and there are M measured values y_k for T , then one formulation of a probability function is:

where σ_k is given by: σ ² = σ ² + σ ² + N_kσ_v ² (16)

where σ_Q ² is a contribution to the jitter due to quantization noise which arises from the finite resolution of the counters and N_k is the sum of fine and coarse counts for the kf^h time interval sample. [0043] It can be easier to minimize the negative logarithm of equation (11) than to find values for σ_τ ² , σ_R and T which maximize equation (11). At the desired minimum, the partial derivatives of the negative logarithm of the right hand side of equation (11) with respect to each of σ_τ ² , σ_R and -Twill be zero. Thus, if we express the negative natural logarithm of the right hand side of equation (11) as L, the desired minimum will satisfy the following system of three equations:

These equations can be solved numerically using any suitable optimization method. Various suitable optimization methods are known. Some of these are described in J. Nocedal et al., Numerical Optimization, Springer, New York, 1999, which is hereby incorporated herein by reference. Gradient-based optimization methods such as the BFGS method may be used, for example, as can other non-linear optimization methods such as so-called genetic methods.

[0044] Another way to obtain values for σ_τ , σ_R ² and T\s to use an a posteriori estimation method. A posteriori estimation methods in which conditions are placed upon the expected result may be used. For example, the noise which results in jitter may be assumed to have a particular waveform, such as sinusoidal, and may be assumed to have a certain frequency, phase and/or amplitude. Maximum a posteriori estimation (MAP) may be used. [0045] If the probability density function of parameter θ is given by p(θ\ Y), where Y is a vector of the measured values^ then, using Baye's Rule one may write:

The MAP estimate of θ is given by:

θ_map can be obtained by numerically minimizing the cost function:

mmaapp

where:

M

Σ y_k k=\ k

~ (23)

[0046] Various numerical methods for minimizing functions such as the function of Equation (18) are known. Some of these are described in J. Nocedal et al., Numerical Optimization, which is noted above.

[0047] If it is known that the noise which results in jitter has certain characteristics (for example, if it is known that the noise is sinusoidal at a specific frequency) then additional constraints may be added in equation (22). One way to express a cost function for estimating input jitter in the presence of TDC internal jitter with random and sinusoidal components is as follows: Σ M M \ (Jyk_k - τ }f (T- T (σ_τ - σ_τy map *—> ik kt=^-l\ 2σ² _k 2σ²τ 2σ _&

(24)

(a - a) ² (ω- ω)² ^ , \

2σ σu ^"+ — 2σ —² _a + ^ 2σ² _υ + _k n(σ_k)

where: a is the amplitude of the sinusoidal noise component and ω is the frequency of the sinusoidal noise component. The cost function of equation (24) may be minimized using a suitable optimization method to estimate σ_τ For example, a gradient-based method such as the bfgs optimization algorithm could be used to estimate σ_τ

[0048] Where a component (e.g. a computer, software module, processor, assembly, device, circuit, etc.) is referred to above, unless otherwise indicated, reference to that component (including a reference to a "means") should be interpreted as including as equivalents of that component any component which performs the function of the described component (i.e., that is functionally equivalent), including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention.

[0049] As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example,

• the number of sets of measurements may be increased. The examples given above illustrate cases where three or four sets of measurements are made. Five or more sets of measurements could also be made.

• the example logic circuits illustrated herein may be replaced with any practical circuits which are their logical equivalents.

• In the embodiment of Figure 1, instead of stopping counting in coarse counter 20C when the FINE_CTRL signal is generated, one could accumulate a count of periods of OSC_A for the entire measurement and subtract the counts in counter 20F from the value in counter 20C to determine the number of cycles of OSC_A during the coarse measurement phase. This may require counter 20C to have a larger capacity than would otherwise be necessary. Similarly one could count in counter 20F for the whole period and subtract the counts from counter 20C to determine the number of cycles of OSC A during the fine measurement phase.

• It is not necessary that the FINE_CTRL signal affects only oscillator 12A.

FINE_CTRL may be supplied to oscillator 12B instead of, or in addition to oscillator 12A as indicated in dashed lines in Figure 1. The periods of either or both of oscillators 12A and 12B may be changed in moving from the coarse measurement phase to the fine measurement phase.

Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A method for evaluating timing noise in a signal of interest, the method comprising: obtaining a first set of measurements by, for each of a plurality of intervals in the signal of interest, each of the intervals beginning at a first event and ending at a second event: triggering a first oscillator upon the occurrence of the first event, the first oscillator subsequently producing a first output signal; triggering a second oscillator upon the occurrence of the second event, the second oscillator subsequently producing a second output signal; when corresponding reference points in the first and second output signals have a first specified time relationship, reducing a difference between periods of the first and second oscillators; determining a number of cycles of the first output signal during a coarse measurement phase between the first oscillator being triggered and the corresponding reference points in the first and second output signals having the first specified time relationship; determining a number of cycles of the first output signal in a fine measurement phase between the corresponding reference points in the first and second output signals having the first specified time relationship and the corresponding reference points in the first and second output signals having a second specified time relationship; and, computing a measure of timing noise in the signal of interest based at least in part upon the first set of measurements.

2. The method of claim 1 wherein: the method comprises also obtaining at least second and third sets of measurements wherein, for each of the second and third sets of measurements at least one of the first and second specified time relationships is different from the first and second relationships of each of the other sets of measurements; and, the measure of timing noise in the signal of interest is computed based upon the first, second and third sets of measurements.

3. The method of claim 1 wherein the measure of timing noise comprises a jitter measurement.

4. The method of claim 3 wherein computing the measure of timing noise comprises performing a least squares estimation.

5. The method of claim 3 wherein computing the measure of timing noise comprises performing a maximum likelihood estimation.

6. The method of claim 3 wherein computing the measure of timing noise comprises performing a maximum a priori estimation.

7. The method of claim 3 wherein computing the measure of timing noise comprises performing an a posteriori estimation.

8. The method of claim 1 wherein triggering the first oscillator comprises waiting for a delay after an edge of a clock signal before triggering the first oscillator upon the occurrence of the first event.

9. The method of claim 8 wherein the delay is a random delay.

10. The method of claim 1 wherein the first event comprises an edge of the signal of interest.

11. The method of claim 10 wherein the second event comprises an edge of the signal of interest.

12. The method of claim 2 wherein, for the first, second and third sets of measurements, the fine measurement phases overlap.

13. The method of claim 12 wherein, for the first, second and third sets of measurements, the coarse measurement phases are shared.

14. The method of claim 3 wherein obtaining the first set of measurements is performed using a time to digital converter having an internal jitter that varies periodically in time.

15. The method of claim 14 wherein computing the measure of timing noise comprises performing a maximum likelihood estimation.

16. The method of claim 14 wherein computing the measure of timing noise i comprises performing a maximum a priori estimation.

17. The method of claim 14 wherein performing a maximum a priori estimation is done subject to a constraint that a component of the timing noise is periodically varying.

18. The method of claim 17 wherein the maximum a priori estimation is done subject to a constraint that a component of the timing noise is sinusoidally varying.

19. A signal analysis apparatus comprising: first and second oscillators respectively configured to produce first and second output signals, the first and second oscillators having at least two states, wherein a difference between periods of the first and second output signals has a different value for each of the at least two states; a trigger circuit connected to cause the first oscillator to commence generating the first output signal on the occurrence of a first event and to cause the second oscillator to commence generating the second output signal on the occurrence of a second event; a first coincidence detector connected to detect when corresponding reference points of the output signals of the first and second oscillators have a first specified time relationship, the first coincidence detector configured to generate a first control signal causing the first and second oscillators to change to a state wherein the difference between the periods of the first and second oscillators is reduced; a counter connected to count periods of the output signal of the first oscillator at least until the first control signal is generated; a plurality of additional coincidence detectors each connected to detect when corresponding reference points of the output signals of the first and second oscillators have a different specified time relationship; and, a plurality of additional counters each connected to count periods of the output signal of the first oscillator until stopped by a signal originating from one of the additional coincidence detectors.

20. An apparatus according to claim 19 wherein the additional counters are connected to operate sequentially.

21. An apparatus according to claim 19 wherein each of the coincidence detectors is connected to receive as inputs the output signal from the first oscillator and a delayed version of the output signal from the second oscillator.

22. An apparatus according to claim 19 comprising a controller connected to cause the apparatus to operate repeatedly to acquire a plurality of sets of data.

23. An apparatus according to claim 22 comprising a memory connected to receive counts from each of the counters.