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WO2003012870A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2003012870A1
WO2003012870A1 PCT/JP2002/006554 JP0206554W WO03012870A1 WO 2003012870 A1 WO2003012870 A1 WO 2003012870A1 JP 0206554 W JP0206554 W JP 0206554W WO 03012870 A1 WO03012870 A1 WO 03012870A1
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WIPO (PCT)
Prior art keywords
terminal
semiconductor device
semiconductor substrate
power supply
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/006554
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French (fr)
Japanese (ja)
Inventor
Hiroshi Miyagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NSC Co Ltd
Original Assignee
Nigata Semitsu Co Ltd
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Application filed by Nigata Semitsu Co Ltd filed Critical Nigata Semitsu Co Ltd
Priority to US10/484,594 priority Critical patent/US20040217442A1/en
Publication of WO2003012870A1 publication Critical patent/WO2003012870A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a semiconductor device formed on a semiconductor substrate.
  • a bypass capacitor has been used to reduce noise that propagates by being superimposed on a power line or the like.
  • a bypass capacitor has been used to reduce noise that propagates by being superimposed on a power line or the like.
  • an external bypass capacitor to the power supply terminal of IC, it is possible to reduce noise output from IC and superimposed on the power supply line.
  • the present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device which can reduce noise appearing at terminals formed on a semiconductor substrate.
  • a semiconductor device includes a component formed on a semiconductor substrate, a terminal provided on the semiconductor substrate and connected to the component, and a semiconductor device formed on the semiconductor substrate. And the bypass capacitor connected to the terminal An inductive component that is external and is connected to the terminal. Since the capacitance of the bypass capacitor formed on the semiconductor substrate is small and cannot be reduced sufficiently, noise output from the terminal is absorbed by inductive components connected to the outside of the semiconductor substrate and converted to heat. By doing so, it is possible to sufficiently reduce it.
  • the above-mentioned terminal is a power supply terminal. Accordingly, it is possible to prevent noise generated in the semiconductor device from entering an external circuit through a power supply line connected to a power supply terminal.
  • the above-mentioned terminal is a clock terminal.
  • the above-mentioned terminal is a clock terminal.
  • the above-mentioned terminal is preferably a ground terminal.
  • the above-mentioned terminal is preferably a ground terminal.
  • the above-mentioned inductive component is preferably a magnetic component such as a ferrite core or a ferrite core closely arranged around a line connected to a terminal. Since the inductance of the line can be increased by bringing the magnetic component into close contact with the periphery of the line, an inductive component can be easily formed. Further, the above-described inductive component is preferably an inductor inserted into a line connected to a terminal. This makes it easy to reduce noise using inductive components.
  • FIG. 1 is a diagram showing a semiconductor device according to an embodiment
  • Figure 2 is a diagram showing a specific example of an inductive component
  • Figure 3 shows a specific example of an inductive component
  • FIG. 4 is a diagram showing a specific example of a conductive component
  • FIG. 5 is a diagram showing a modification of the semiconductor device
  • FIG. 6 is a diagram showing another modification of the semiconductor device.
  • BEST MODE FOR CARRYING OUT THE INVENTION a semiconductor device according to an embodiment of the present invention will be described in detail.
  • FIG. 1 is a diagram showing a semiconductor device of the present embodiment.
  • a semiconductor device 10 according to the present embodiment includes a rectangular semiconductor substrate 11 and components 12 formed on the semiconductor substrate 11 using a semiconductor process such as a MOS process. And a power supply terminal 20 and various terminals including a ground terminal 22 formed near the periphery of the semiconductor substrate 11.
  • the constituent parts 12 form, for example, respective circuits constituting a receiver. Also, this component 12 includes a bypass capacitor 14, one end of which is connected to the power terminal 20 and the other end of which is connected to the ground terminal 22. . An inductive component 30 is provided outside the semiconductor substrate 11, and one end of the inductive component 30 is connected to the power supply terminal 20, and the other end is connected to the power supply circuit 40. ing.
  • Each of the semiconductor device 10, the inductive component 30, and the power supply circuit 40 described above is mounted on the surface of the wiring board 100.
  • FIG. 2 to 4 are diagrams showing specific examples of the inductive component 30.
  • FIG. 2 to 4 are diagrams showing specific examples of the inductive component 30.
  • FIG. 2 is a perspective view showing a mounting example in the case of using a ferrite bead 3OA.
  • a ferrite bead 30A is integrated and closely attached to a lead wire in the middle of a line 50 connecting the power supply terminal 20 and the power supply circuit 40.
  • the inductance in the lead wire on which the ferrite bead 30A is formed increases.
  • FIG. 3 is a diagram illustrating an implementation example when the ferrite core 30B is used. As shown in FIG. 3, the ferrite core 30B is closely attached to a part of the line 52 connecting the power supply terminal 20 and the power supply circuit 40, so that the inductance of the line 52 passing therethrough is provided. The stance becomes partially large.
  • FIG. 4 is a diagram showing a mounting example when the chip inductor 30C is used. As shown in FIG. 4, a chip inductor 30 C as a surface mount component is inserted in the middle of a line 54 connecting the power supply terminal 20 and the power supply circuit 40.
  • the bypass capacitor 14 connected between the power supply terminal 20 and the ground terminal 22 is formed on the semiconductor substrate 11.
  • the ferrite bead 30 A, ferrite core 30 B, chip inductor 30 C, and other inductive components 30 as external components described above are provided outside the semiconductor substrate 11 to the power supply terminal 20. It is connected.
  • the bypass capacitor 14 formed on the semiconductor substrate 11 cannot secure a large capacitance in view of a practical area. For this reason, when a large noise is generated in the component 12, the noise cannot be sufficiently reduced only by the bypass capacitor 14.
  • the inductive component 30 is connected to the power supply terminal 20 of the semiconductor device 10 of the present embodiment and the power supply circuit 40, the power supply terminal 20 cannot sufficiently reduce the inductive component by only the bypass capacitor 14.
  • the noise output to the power supply line connected to the power supply terminal 20 can be reliably reduced by the inductive component 30.c
  • the present invention is not limited to the above embodiment. Various modifications are possible within the scope of the invention.
  • the inductive component 30 is connected only to the power terminal 20. However, as shown in FIG.
  • the inductive component 30 is separately connected to both the power terminal 20 and the ground terminal 22. This may c be connected to the, as possible out to reduce the noise output to the ground line or the ground layer connected to the connected power line and the ground terminal 2 2 to the power supply terminal 2 0.
  • FIG. 6 is a diagram illustrating a configuration of a semiconductor device that reduces noise output to a clock line. As shown in FIG. 6, when the clock terminal 24 is connected to the clock generation circuit 42 formed by the components 12, the bypass capacitor 14 and the inductive component 30 are connected to the clock terminal 24. May be connected. As a result, noise output from the clock terminal 24 to the clock line can be reduced.
  • noise output from a terminal that cannot be sufficiently reduced due to a small capacitance of a bypass capacitor formed on a semiconductor substrate is connected to the outside of the semiconductor substrate. Is converted into heat by absorbing It is possible to reduce more sufficiently

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

A semiconductor device in which noise appearing at a terminal provided on a semiconductor substrate is reduced. The semiconductor device (10) comprises a rectangular semiconductor substrate (11), constituent components (12) disposed on the semiconductor substrate (11), and terminals (22) including a power supply terminal (20) and a ground terminal both disposed along the periphery of the semiconductor substrate (11). The constituent components (12) include a bypass capacitor (14), one end of which is connected to the power supply terminal (20) and the other of which is connected to the ground terminal (22). An inductive component (30) is provided outside of the semiconductor substrate (11). One end of the inductive component (30) is connected to the power supply terminal (20), and the other end is connected to a power supply circuit (40).

Description

明 細 書 半導体装置 技術分野  Description Semiconductor device technical field

本発明は、 半導体基板上に形成される半導体装置に関する。 背景技術  The present invention relates to a semiconductor device formed on a semiconductor substrate. Background art

従来から、 電源ライン等に重畳して伝搬するノィズを低減するためにバイパス コンデンサが用いられている。 例えば、 I Cの電源端子に外付けのバイバスコン デンサを接続することにより、 I Cから出力されて電源ラインに重畳するノイズ を低減することができる。  Conventionally, a bypass capacitor has been used to reduce noise that propagates by being superimposed on a power line or the like. For example, by connecting an external bypass capacitor to the power supply terminal of IC, it is possible to reduce noise output from IC and superimposed on the power supply line.

また、 最近では各種の回路を M〇 Sプロセス等の半導体プロセスを用いて半導 体基板上に一体形成する技術の研究が進んでおり、 一部の装置では実用化されて いる。 半導体プロセスを用いて 1チップ上に各種の回路を形成することにより、 装置全体の小型化ゃコスト低減が可能になるため、 1チップ上に形成される回路 の範囲が今後拡大すると考えられる。  In recent years, research has been advanced on technology for integrally forming various circuits on a semiconductor substrate using a semiconductor process such as the MS process, and some devices have been put into practical use. By forming various circuits on one chip using a semiconductor process, it is possible to reduce the size and cost of the entire device, and the range of circuits formed on one chip is expected to expand in the future.

ところで、 バイパスコンデンサを含む回路の各構成部品を半導体基板上に形成 する場合に、 半導体基板上に形成するバイパスコンデンサの静電容量を大きくす ることができないため、 このバイパスコンデンサが接続される端子に現れるノィ ズを十分に低減することができないという問題があった。 発明の開示  By the way, when forming each component of a circuit including a bypass capacitor on a semiconductor substrate, it is not possible to increase the capacitance of the bypass capacitor formed on the semiconductor substrate. However, there is a problem that the noise that appears in the above cannot be sufficiently reduced. Disclosure of the invention

本発明は、 このような点に鑑みて創作されたものであり、 その目的は、 半導体 基板上に形成された端子に現れるノィズを低減することができる半導体装置を提 供することにある。  The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device which can reduce noise appearing at terminals formed on a semiconductor substrate.

上述した課題を解決するために、 本発明の半導体装置は、 半導体基板上に形成 された構成部品と、 半導体基板上に設けられて構成部品に接続された端子と、 半 導体基板上に形成されて端子に接続されるバイパスコンデンサと、 半導体基板の 外部であって端子に接続される誘導性部品とを備えている。 半導体基板上に形成 されたバイパスコンデンサの静電容量が小さいために十分に低減できずに端子か ら出力されたノイズを、 半導体基板の外部に接続された誘導性部品によって吸収 して熱に変換することにより十分に低減することが可能になる。 In order to solve the above-described problems, a semiconductor device according to the present invention includes a component formed on a semiconductor substrate, a terminal provided on the semiconductor substrate and connected to the component, and a semiconductor device formed on the semiconductor substrate. And the bypass capacitor connected to the terminal An inductive component that is external and is connected to the terminal. Since the capacitance of the bypass capacitor formed on the semiconductor substrate is small and cannot be reduced sufficiently, noise output from the terminal is absorbed by inductive components connected to the outside of the semiconductor substrate and converted to heat. By doing so, it is possible to sufficiently reduce it.

また、 上述した端子は、 電源端子であることが望ましい。 これにより、 半導体 装置内で発生したノイズが、 電源端子に接続される電源ラインを通して外部の回 路に侵入することを防止することができる。  Further, it is desirable that the above-mentioned terminal is a power supply terminal. Accordingly, it is possible to prevent noise generated in the semiconductor device from entering an external circuit through a power supply line connected to a power supply terminal.

また、 上述した端子は、 クロック端子であることが望ましい。 これにより、 半 導体装置内で発生したノイズが、 クロック端子に接続されるクロックラインを通 して外部の回路に侵入することを防止することができる。  Further, it is desirable that the above-mentioned terminal is a clock terminal. Thus, it is possible to prevent noise generated in the semiconductor device from invading an external circuit through the clock line connected to the clock terminal.

また、 上述した端子は、 グランド端子であることが望ましい。 これにより、 半 導体装置内で発生したノイズが、 グランド端子に接続されるグランドラインゃグ ランド層を通して外部の回路に侵入することを防止することができる。  Further, the above-mentioned terminal is preferably a ground terminal. Thus, it is possible to prevent noise generated in the semiconductor device from invading an external circuit through the ground line and the ground layer connected to the ground terminal.

また、 上述した誘導性部品は、 端子に接続される線路の周囲に密着配置したフ エライ トビ一ドやフェライ トコアなどの磁性体部品であることが望ましい。 線路 の周囲に磁性体部品を密着させることによりこの線路のィンダクタンスを大きく することができるため、 容易に誘導性部品を形成することができる。 また、 上述 した誘導性部品は、 端子に接続される線路に挿入されるインダク夕であることが 望ましい。 これにより、 容易に誘導性部品を用いたノイズの低減が可能になる。 図面の簡単な説明  The above-mentioned inductive component is preferably a magnetic component such as a ferrite core or a ferrite core closely arranged around a line connected to a terminal. Since the inductance of the line can be increased by bringing the magnetic component into close contact with the periphery of the line, an inductive component can be easily formed. Further, the above-described inductive component is preferably an inductor inserted into a line connected to a terminal. This makes it easy to reduce noise using inductive components. BRIEF DESCRIPTION OF THE FIGURES

図 1は、 一実施形態の半導体装置を示す図、  FIG. 1 is a diagram showing a semiconductor device according to an embodiment,

図 2は、 誘導性部品の具体例を示す図、  Figure 2 is a diagram showing a specific example of an inductive component,

図 3は、 誘導性部品の具体例を示す図、  Figure 3 shows a specific example of an inductive component,

図 4は、 導性部品の具体例を示す図、  FIG. 4 is a diagram showing a specific example of a conductive component,

図 5は、 半導体装置の変形例を示す図、  FIG. 5 is a diagram showing a modification of the semiconductor device,

図 6は、 半導体装置の他の変形例を示す図である。 発明を実施するための最良の形態 以下、 本発明を適用した一実施形態の半導体装置について詳細に説明する。 図 1は、 本実施形態の半導体装置を示す図である。 図 1に示すように、 本実施 形態の半導体装置 1 0は、 矩形形状の半導体基板 1 1と、 M O Sプロセス等の半 導体プロセスを用いて半導体基板 1 1上に形成された構成部品 1 2と、 半導体基 板 1 1の周辺近傍に形成された電源端子 2 0およびグランド端子 2 2を含む各種 の端子とを含んで構成されている。 FIG. 6 is a diagram showing another modification of the semiconductor device. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail. FIG. 1 is a diagram showing a semiconductor device of the present embodiment. As shown in FIG. 1, a semiconductor device 10 according to the present embodiment includes a rectangular semiconductor substrate 11 and components 12 formed on the semiconductor substrate 11 using a semiconductor process such as a MOS process. And a power supply terminal 20 and various terminals including a ground terminal 22 formed near the periphery of the semiconductor substrate 11.

構成部品 1 2によって、 例えば受信機を構成する各回路が形成されている。 ま た、 この構成部品 1 2にはバイパスコンデンサ 1 4が含まれており、 このバイパ スコンデンサ 1 4の一方端が電源端子 2 0に、 他方端がグランド端子 2 2にそれ それ接続されている。 また、 半導体基板 1 1の外部には誘導性部品 3 0が設けら れており、 この誘導性部品 3 0の一方端が電源端子 2 0に、 他方端が電源回路 4 0にそれそれ接続されている。  The constituent parts 12 form, for example, respective circuits constituting a receiver. Also, this component 12 includes a bypass capacitor 14, one end of which is connected to the power terminal 20 and the other end of which is connected to the ground terminal 22. . An inductive component 30 is provided outside the semiconductor substrate 11, and one end of the inductive component 30 is connected to the power supply terminal 20, and the other end is connected to the power supply circuit 40. ing.

上述した半導体装置 1 0、 誘導性部品 3 0、 電源回路 4 0のそれそれが配線基 板 1 0 0の表面に実装されている。  Each of the semiconductor device 10, the inductive component 30, and the power supply circuit 40 described above is mounted on the surface of the wiring board 100.

図 2〜図 4は、 誘導性部品 3 0の具体例を示す図である。  2 to 4 are diagrams showing specific examples of the inductive component 30. FIG.

図 2は、 フェライ トビ一ド 3 O Aを用いた場合の実装例を示す斜視図である。 図 2に示すように、 電源端子 2 0と電源回路 4 0とを接続する線路 5 0の途中に、 フェライ トビード 3 0 Aが一体になつてリード線に密着配置された部品を用いる ことにより、 このフェライ トビード 3 0 Aが形成されたリード線におけるインダ クタンスが大きくなる。  FIG. 2 is a perspective view showing a mounting example in the case of using a ferrite bead 3OA. As shown in FIG. 2, by using a part in which a ferrite bead 30A is integrated and closely attached to a lead wire in the middle of a line 50 connecting the power supply terminal 20 and the power supply circuit 40, The inductance in the lead wire on which the ferrite bead 30A is formed increases.

図 3は、 フェライ トコア 3 0 Bを用いた場合の実装例を示す図である。 図 3に 示すように、 電源端子 2 0と電源回路 4 0とを接続する線路 5 2の一部にフェラ イ トコア 3 0 Bを密着配置することにより、 その下側を通る線路 5 2のィンダク タンスが部分的に大きくなる。  FIG. 3 is a diagram illustrating an implementation example when the ferrite core 30B is used. As shown in FIG. 3, the ferrite core 30B is closely attached to a part of the line 52 connecting the power supply terminal 20 and the power supply circuit 40, so that the inductance of the line 52 passing therethrough is provided. The stance becomes partially large.

図 4は、 チップインダク夕 3 0 Cを用いた場合の実装例を示す図である。 図 4 に示すように、 電源端子 2 0と電源回路 4 0とを接続する線路 5 4の途中に、 表 面実装部品としてのチップィンダクタ 3 0 Cが挿入されている。  FIG. 4 is a diagram showing a mounting example when the chip inductor 30C is used. As shown in FIG. 4, a chip inductor 30 C as a surface mount component is inserted in the middle of a line 54 connecting the power supply terminal 20 and the power supply circuit 40.

このように、 本実施形態の半導体装置 1 0は、 電源端子 2 0とグランド端子 2 2との間に接続されるバイパスコンデンサ 1 4が半導体基板 1 1上に形成されて いるとともに、 半導体基板 1 1の外部に外付け部品としての上述したフェライ ト ビード 3 0 A、 フェライ トコア 3 0 B、 チップインダクタ 3 0 C等を用いた誘導 性部品 3 0が電源端子 2 0に接続されている。 As described above, in the semiconductor device 10 of the present embodiment, the bypass capacitor 14 connected between the power supply terminal 20 and the ground terminal 22 is formed on the semiconductor substrate 11. The ferrite bead 30 A, ferrite core 30 B, chip inductor 30 C, and other inductive components 30 as external components described above are provided outside the semiconductor substrate 11 to the power supply terminal 20. It is connected.

一般に、 半導体基板 1 1上に形成されるバイパスコンデンサ 1 4は'、 実用的な 面積を考えると、 大きな静電容量を確保することができない。 このため、 構成部 品 1 2において大きなノイズが発生したときにバイパスコンデンサ 1 4のみでこ れを十分に低減することができない。 しかし、 本実施形態の半導体装置 1 0の電 源端子 2 0には、 電源回路 4 0との間に誘導性部品 3 0が接続されているため、 バイパスコンデンサ 1 4のみで十分に低減できずに電源端子 2 0に接続された電 源ラインに出力されるノイズを、 誘導性部品 3 0で確実に低減することができる c なお、 本発明は上記実施形態に限定されるものではなく、 本発明の要旨の範囲 内において種々の変形実施が可能である。 例えば、 上述した実施形態では、 電源 端子 2 0のみに誘導性部品 3 0を接続したが、 図 5に示すように、 電源端子 2 0 とグランド端子 2 2の両方に別々に誘導性部品 3 0を接続するようにしてもよい c これにより、 電源端子 2 0に接続された電源ラインとグランド端子 2 2に接続さ れたグランドラインあるいはグランド層に出力されるノイズを低減することがで きる。 Generally, the bypass capacitor 14 formed on the semiconductor substrate 11 cannot secure a large capacitance in view of a practical area. For this reason, when a large noise is generated in the component 12, the noise cannot be sufficiently reduced only by the bypass capacitor 14. However, since the inductive component 30 is connected to the power supply terminal 20 of the semiconductor device 10 of the present embodiment and the power supply circuit 40, the power supply terminal 20 cannot sufficiently reduce the inductive component by only the bypass capacitor 14. In addition, the noise output to the power supply line connected to the power supply terminal 20 can be reliably reduced by the inductive component 30.c The present invention is not limited to the above embodiment. Various modifications are possible within the scope of the invention. For example, in the above-described embodiment, the inductive component 30 is connected only to the power terminal 20. However, as shown in FIG. 5, the inductive component 30 is separately connected to both the power terminal 20 and the ground terminal 22. This may c be connected to the, as possible out to reduce the noise output to the ground line or the ground layer connected to the connected power line and the ground terminal 2 2 to the power supply terminal 2 0.

また、 上述した実施形態では、 電源端子 2 0に着目したが、 それ以外の端子か ら出力されるノイズを低減するようにしてもよい。 図 6は、 クロックラインに出 力されるノイズを低減する半導体装置の構成を示す図である。 図 6に示すように、 構成部品 1 2によって形成されたクロック生成回路 4 2にクロック端子 2 4が接 続されている場合に、 このクロック端子 2 4にバイパスコンデンサ 1 4と誘導性 部品 3 0を接続するようにしてもよい。 これにより、 クロック端子 2 4からクロ ックラインに出力されるノイズを低減することができる。 産業上の利用可能性  Further, in the above-described embodiment, the power supply terminal 20 is focused, but noise output from other terminals may be reduced. FIG. 6 is a diagram illustrating a configuration of a semiconductor device that reduces noise output to a clock line. As shown in FIG. 6, when the clock terminal 24 is connected to the clock generation circuit 42 formed by the components 12, the bypass capacitor 14 and the inductive component 30 are connected to the clock terminal 24. May be connected. As a result, noise output from the clock terminal 24 to the clock line can be reduced. Industrial applicability

上述したように、 本発明によれば、 半導体基板上に形成されたバイパスコンデ ンサの静電容量が小さいために十分に低減できずに端子から出力されたノイズを、 半導体基板の外部に接続された誘導性部品によって吸収して熱に変換することに より十分に低減することが可能になる As described above, according to the present invention, noise output from a terminal that cannot be sufficiently reduced due to a small capacitance of a bypass capacitor formed on a semiconductor substrate is connected to the outside of the semiconductor substrate. Is converted into heat by absorbing It is possible to reduce more sufficiently

Claims

請 求 の 範 囲 The scope of the claims 1 . 半導体基板上に形成された構成部品と、  1. a component formed on a semiconductor substrate; 前記半導体基板上に設けられて前記構成部品に接続された端子と、  A terminal provided on the semiconductor substrate and connected to the component, 前記半導体基板上に形成されて前記端子に接続されるバイパスコンデンサと、 前記半導体基板の外部であって前記端子に接続される誘導性部品と、 を備える半導体装置。  A semiconductor device comprising: a bypass capacitor formed on the semiconductor substrate and connected to the terminal; and an inductive component external to the semiconductor substrate and connected to the terminal. 2 . 前記端子は、 電源端子である請求の範囲第 1項記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the terminal is a power terminal. 3 . 前記端子は、 クロック端子である請求の範囲第 1項記載の半導体装置。 3. The semiconductor device according to claim 1, wherein said terminal is a clock terminal. 4 . 前記端子は、 グランド端子である請求の範囲第 1項記載の半導体装置。4. The semiconductor device according to claim 1, wherein the terminal is a ground terminal. 5 . 前記誘導性部品は、 前記端子に接続される線路の周囲に密着配置した磁性 体部品である請求の範囲第 1項記載の半導体装置。 5. The semiconductor device according to claim 1, wherein said inductive component is a magnetic component closely arranged around a line connected to said terminal. 6 . 前記磁性体部品は、 フェライ トビードである請求の範囲第 5項記載の半導 体装置。  6. The semiconductor device according to claim 5, wherein the magnetic component is a ferrite bead. 7 . 前記磁性体部品は、 フェライ トコアである請求の範囲第 5項記載の半導体  7. The semiconductor according to claim 5, wherein the magnetic component is a ferrite core. 8 . 前記誘導性部品は、 前記端子に接続される線路に挿入されるインダク夕で ある請求の範囲第 1項記載の半導体装置。 8. The semiconductor device according to claim 1, wherein the inductive component is an inductor inserted into a line connected to the terminal.
PCT/JP2002/006554 2001-07-30 2002-06-28 Semiconductor device Ceased WO2003012870A1 (en)

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