WO2003092155A1 - Distortion compensation amplifier by digital predistortor method - Google Patents

Abstract

A distortion compensation amplifier by a digital predistortor method comprising an adder for adding a first digital signal and a correction signal, a digital/analog converter for converting the output signal of the adder into a first analog signal in synchronism with a first clock, a first amplifier for amplifying the first analog signal with a first gain, a second amplifier for amplifying the input signal originated from the output signal of the first amplifier to the input level of the input signal of the first amplifier, an analog/digital converter for converting the signal originated from the output signal of the second amplifier into a second digital signal in synchronism with a second clock, a first delay circuit for delaying the first clock for the time from the input of the signal into the digital/analog converter until the feedback to the analog/digital converter via the first and second amplifiers so as to output the second clock, a second delay circuit for delaying the first digital signal so as to output a third digital signal, and a comparator for outputting a differential signal of the second and third digital signals as a correction signal.

Description

 Description Distortion-compensated amplifier using digital prism method

 The present invention relates to a distortion-compensating amplifier that performs distortion compensation by a digital pre-register method.

 Background technology

 An amplifier is used in a wireless transmitter or the like to amplify a transmission signal or the like. The amplifier generates distortion depending on the band of the signal to be amplified. If the distortion signal mixes with the main signal, the communication quality deteriorates, so the distortion is compensated by the distortion removal circuit. The distortion compensation includes, for example, a digital register system.

 FIG. 7 is a configuration diagram of a distortion-compensating amplifier using the digital prism method. As shown in Fig. 7, the distortion compensating amplifier is composed of an LSI 10, which consists of an adder 2, a divider 4, a delay circuit 6, and a comparator 8, a reference clock generator 12, and a D / A converter. 14, Local signal generator 16, Mixer 18, Amplifier 20, Power blocker 22, Amplifier 24, Local signal generator 26, Mixer 28, and A / D converter 30 You. The adder 2 adds the input signal S 2 (for example, 12 bits at 30.72 MHz) and the correction signal S 4 of the comparator 8 to output a signal S 6. The reference clock generator 12 outputs a reference clock signal CLK0 of, for example, 12.2.88 MHz. The divider 4 branches the reference clock signal CK0 into two reference clocks CLK1 and CLK2.

The D / A converter 14 uses the reference clock CLK 1 as a DZA clock, for example, samples the signal S 6 at the rising edge of the clock CLK 1, and converts it to an analog signal S 8. The local signal generator 16 generates a local signal for frequency conversion from the baseband to an intermediate frequency band (for example, 2.1 G). The mixer 18 frequency-converts the analog signal S8 to an intermediate frequency band based on the local oscillation signal, and outputs a signal S9. The amplifier 20 amplifies the output signal S9 of the mixer 18 with a constant gain and outputs the signal S10. The signal S10 includes the distortion signal S12 in addition to the main signal S11. Coupler 22 splits output signal S 10 of amplifier 20 into two Then, a part of the signal is output to the outside, and the remaining signal S 13 is output to the amplifier 24.

 The amplifier 24 amplifies the input signal S13 with a predetermined gain so that the main signal level of the input signal S13 becomes equal to the level of the input signal S9 to the amplifier 20. Is output. The local oscillator 26 outputs a local oscillator for conversion to the input frequency band (base band) of the mixer 18. The mixer 28 performs frequency conversion for converting the output signal S 14 of the amplifier 24 into an input frequency band of the mixer 18 based on the local oscillation signal, and outputs a signal S 15. The A / D converter 30 samples the output signal S15 of the mixer 28 at the timing of the rising edge of the clock CLK2, for example, using the reference clock CLK2 as the A / D clock. Convert to digital signal S16.

 The delay circuit 6 converts the input signal S 2 to a part of the adder 2 and the D / A to match the input signal corresponding to the output signal of the A / D converter 30 input to the comparator 8. Delay until feedback to comparator 8 via converter 14, mixer 18, amplifier 20, power bra 22, amplifier 24, mixer 28, A / D converter 28. The signal S17 is output with a delay by the time. Comparator 8 subtracts output signal S16 of A / D converter 30 from output signal S.17 of delay circuit 6, and outputs correction signal S4 as an inverse distortion component.

 The adder 2 adds the correction signal S4 and the input signal S2, and outputs a signal S6. The signal S 6 is converted into an analog signal by the DZA converter 14, frequency-converted by the mixer 18, and then amplified by the amplifier 20. At this time, the distortion component of the main signal S 9 is output by the amplifier 20. Since this distortion component is similar to the distortion component S 12, it is multiplexed with the inverse distortion component S 4 of the distortion component. This compensates for distortion.

 However, the distortion compensating amplifier using the conventional digital prism method has the following problems.

FIG. 8 is a diagram showing a conventional problem. As shown in FIG. 8, the analog signal S 8 obtained by sampling the input signal S 2 at the rising edge of the D / A clock CLK 1 by the D / A converter 14 is converted into a mixer 18, an amplifier 20, It is input to the A / D converter 30 after T time via the power bra 22, the amplifier 24 and the mixer 28. A / The D converter 30 samples the signal S15 at the rising edge of the AZD clock CLK2 and converts it into a digital signal S16.The reference clocks CLK1 and CLK2 are output from the reference clock CLK1 by the device 4. Since 0 is divided into two and rises at the same time, the D / A converter 14 and the A / D converter 30 perform analog / digital conversion at the same time.

 On the other hand, to the A / D converter 30, a signal corresponding to T time after the signal input to the D / A converter 18 is input to the D / A converter 18 is input. This is equivalent to sampling the signal with a clock that is shifted from the current clock by the amount of the T-time clock, which is the interval between the solid line and the broken line in FIG. Due to this clock generation, the A / D-converted digital signal S 16 deviates from the D / A-converted digital signal S 6 in timing, making it difficult to accurately perform distortion compensation. there were.

 Disclosure of the invention.

 An object of the present invention is to perform a D / A conversion and an A / D conversion at the same timing, thereby stably compensating for a distortion, thereby improving the quality of the digital pre-storage system. To provide a distortion-compensating amplifier.

According to one aspect of the present invention, there is provided a distortion compensation type amplifier using a digital pre-storage method, wherein an adder for adding a first digital signal and a correction signal, and an output of the adder based on a first clock. A digital / analog converter for converting a signal into a first analog signal, a first amplifier for amplifying with a first gain based on the first analog signal, and an input signal based on an output signal of the first amplifier. A second amplifier that amplifies the input signal to match the input level of the input signal of the first amplifier; and an analog / digital conversion that converts a signal based on an output signal of the second amplifier into a second digital signal based on a second clock. A signal from the input of the signal to the digital / analog converter until the signal is fed back to the analog / digital converter via the first amplifier and the second amplifier. A first delay circuit that delays a clock and outputs the second clock, a second delay circuit that delays the first digital signal and outputs a third digital signal, the second digital signal and the second (3) a comparator that outputs a difference signal from the digital signal as the correction signal. A distortion-compensated amplifier using a rigid-toother method is provided.

 Preferably, the first delay circuit is a variable delay circuit that delays an input signal based on a control signal indicating a delay amount, and a delay amount that controls a delay amount of the first delay circuit based on the difference signal. It further comprises a control unit.

 More preferably, the delay amount control unit needs to change a delay amount of the first delay circuit based on a detector for detecting a level of the differential signal and a detection signal detected by the detector. If it is determined that the delay amount of the first delay circuit is variably controlled, the control unit controls the delay amount of the first delay circuit to be variably controlled. And a holding unit that outputs a signal output from the comparator as a correction signal to the adder at other times as a correction signal as a correction signal to the adder. .

 BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a diagram illustrating the principle of the present invention;

 '' Fig. 2 is an illustration of the effect of Fig. 1;

 FIG. 3 is a diagram showing a configuration example of a digital predistortion / distortion / compensation amplifier according to an embodiment of the present invention;

 Figure 4 is a block diagram related to the correction in Figure 3;

 Figure 5 shows the error level detection table;

 Figure 6 is a flowchart;

 Fig. 7 shows an example of the configuration of a conventional digital pre-distortion type distortion-compensating amplifier;

 FIG. 8 is a diagram showing a conventional problem.

 BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a diagram illustrating the principle of the present invention. As shown in Fig. 1, the distortion compensating amplifier based on the digital-prescribed-evening method includes a first delay circuit 50, a comparator 52, an adder 54, a D / A converter 56, a first amplifier 58, A power amplifier 60, a second amplifier 62, an A / D converter 64, and a second delay circuit 66. The adder 54 adds the digital signal S 20 and the output signal S 22 of the comparator 52 to output a signal S 24. The D / A converter 56 uses the first reference clock CLK 1 as a D / A clock, for example, the clock CLK 1 The signal S 24 is sampled at the rising edge of the analog signal S.

Convert to 2 6

 The first amplifier 58 amplifies the analog signal S26 and outputs a signal S28. The signal S28 is obtained by adding the distortion signal S32 to the main signal S30. The power bra 60 outputs a part of the signal S 28, the signal S 34, to the second amplifier 62. The second amplifier 62 receives the signal S

The main signal S36 of 34 is amplified to match the level of the analog signal S26, and the signal S40 is output. The signal S40 is input to the A / D converter 64 after T time from when the corresponding signal S24 is input to the D / A converter 56. The second delay circuit 68 is used to transmit the first reference clock CLK 1 from the time when the signal S 24 is input to the D / A converter 56 to the time when the signal S 24 is input to the A / D converter 64. Outputs the second reference clock CLK 2 with a time delay. The / 0 converter 64 uses the second reference clock CLK2 as an A / D clock, for example, at the rising edge of the clock CLK2, the signal S

40 is sampled and converted into a digital signal S46.

FIG. 2 is a time chart of D / A conversion and A / D conversion of the present invention. DZA clock Signal sampled at the rising edge of CLK1. S24 is data D1. The data D 1 is input to the A / D converter 64 as data 131, after T time from the input to the D / A converter 56. On the other hand, since the A / D clock CLK 2 is delayed by T time from the D / A clock CLK 1, the data D 1 corresponding to D 1 will be lost at the timing when the A / D clock CLK 2 rises. 1, but will be input to the a / D converter 6 4, data D l, but digital. _c Thus is converted into barrel signals, data converted a Roh D by the a / D converter 6 4 Corresponding to the data D / A-converted by the D / A converter 56, the same data is converted at the same timing, and the clock jitter can be ignored.

 On the other hand, the first delay circuit 50 delays the signal S 21 from the input of the digital signal S 20 to the input of the digital signal S 46 to the comparator 52 by the signal S 21.

5 Output to 2. The comparator 52 outputs a difference signal between the signal S 21 and the signal S 46 as a correction signal S 22. At this time, since the clock signal of the signal S 46 can be ignored, the correction signal 22 is a digital signal in which the clock signal of the opposite phase of the distortion signal S 32 generated by the first amplifier 56 is ignored. It is. Adder 54 is digital The signal S20 is added to the correction signal S22 to output a signal S24.

 The signal S 24 is converted into an analog signal S 26 by the DZA converter 54 in synchronization with the D / A clock CLK 1, and is amplified to a signal S 28 by the first amplifier 56. At this time, although a distortion signal is generated in the first amplifier 56, good distortion compensation can be performed because the negative-phase signal of the distortion signal is input and the negative-phase signal can be ignored in the clock signal. Made to improve the quality of the amplifier.

 FIG. 3 is a configuration diagram of a distortion compensating amplifier using a digital pre-register system according to an embodiment of the present invention. Components that are substantially the same as those in FIG. 7 are given the same reference numerals. are doing. The distortion compensation type amplifier using the digital prism type shown in FIG. 3 has the following steps: (i) The reference clock CLK 1 is input to the D / A converter 14 and then fed back to the A / D converter 30 (Ii) The delay time T is variable because the delay time T may fluctuate due to temperature changes and the aging of the amplifiers 20 and 24. The control is different from the conventional distortion compensation type amplifier. .,.

 Therefore, it is necessary to detect the correct delay time T. However, the pilot signal is input to the D / A converter 14 and then to the A / D converter 30.時間 Measuring the time until the feedback signal is fed back is measured by detecting the level of the correction signal output from the comparator 8 due to the complexity of the device. Detects whether or not the reference clock CLK1 is delayed by T, and changes the delay amount so that the reference clock CLK1 is delayed with the correct delay time. Since the correction signal is a signed digital signal, the error level is the absolute value indicated by the correction signal. The error level may be a moving average value (integral value) within a fixed time from the current time, or may be an instantaneous level. The fact that the delay time T fluctuates due to the output level (error level) of the comparator 8 is detected for the following reason.

 (i) When the reference clock is delayed by the correct delay time

 When the distortion compensation is stably performed, the error level of the output of the comparator 8 is considered to be within a certain level range since the clock jitter is negligible.

 (ii) The reference clock is not delayed by the correct delay time.

Clock jitter can not be ignored and distortion compensation can be performed stably. Without distortion compensation amplifier according to the digital pre-Soo toe evening formula as shown in _c Figure 3 error level is thought to exceed a certain level range of the output of the comparator 8, an adder 2, Debaiza 4, the delay circuit 6 , A comparator 8 and a holding unit 98, an LSI 100, a reference clock generator 12, a 0 / converter 14, a local oscillator 16, a mixer 18, and a first amplifier 20, power brass 22, 2nd amplifier 24, local signal generator 26, mixer 28, A / D converter 30, detector 102, control unit 104 and ττ corrector 1 It has 0 6. FIG. 4 is a diagram showing a part related to the correction in FIG. The detector 102 has the following functions. Initial start-up (initial start-up operation), delay time Τ is set correctly, distortion compensation is performed well (normal control operation), delay time is not set correctly, distortion compensation Is output to the holding unit 98 and the control unit 104, indicating whether the operation is not properly performed (control operation with respect to the temperature of the AMP system and aging). Whether the AMPs 20 and 24 are correctly set in the compensator 106 with the delay time T due to temperature change or aging depends on the relationship between the signal error and the operating state in the error level detection chip. Remember and refer to it.

 FIG. 5 is a diagram showing an error level detection table. As shown in Fig. 5, the operation states of the normal control gauge, the control operation for the temperature and aging of the AMP system, and the initial startup operation are classified according to the error level. In normal control operation, the delay time T is set correctly, and the error level is considered to be below a certain level because it is considered that distortion compensation is performed well. When there is. In the control operation for the temperature and aging of the AMP system, the delay time is not set correctly, and the distortion compensation is not performed properly due to the clock jitter. It is assumed that the error level is larger than the error level of, for example, a range of 3 to 5. Also, in the initial start-up operation, since the distortion compensation has not yet converged, it is assumed that the error level is higher than the other operations, for example, in the range of 6 to 10. Each operation is as follows.

(i) At the time of initial startup, the output signal S74 from the comparator 8 passes through the holding unit 98 and is supplied to the adder 2, so that the delay amount controlled by the control unit 104 is maintained. Repeat until the error signal level falls within the range of 0 to 3 levels. Start operation at initial startup Since the correct delay amount measured before is set in the corrector 106, the compensation converges after a certain period of time from the start of operation, and the normal control operation starts.

 (ii) In the normal control operation, the output signal S74 from the comparator 8 passes through the holding unit 98 and is supplied to the adder 2, so that the delay amount controlled by the control unit 102 is maintained.

 (iii) In the control operation for the temperature and aging of the AMP system, the compensation signal S76 to the adder 2 is set to a constant value in the normal control operation slightly earlier than that, and the control unit 104 Then, control the compensator 106 to search for the comparison result of the comparator 8 or a value approaching 0, and find the optimum value that minimizes the error level when the error signal level is in the range of 0 to 3. The value is set in the corrector 106. After that, the holding of the correction signal S74 from the comparator 8 to the adder 2 is released, and the operation returns to the normal control operation. ■ The holding unit 98 has the following functions. (I) When the detection signal S70 output from the detector 102 indicates the initial start-up operation or the normal control operation, the output S74 of the comparator 8 is output as it is and Discard the stored value and retain the current value. (Ii) When the detection signal S70 indicates a control operation for the temperature and aging of the AMP system, the held value is output to the adder 2. In this way, the reason why the detection signal S70 is not passed to the adder 2 through the detection signal S70 is that the delay time set in the compensator 106 in the control operation for the temperature and aging of the AMP system This is because the output signal S 74 of the comparator 8 is not an accurate reverse distortion signal because the output signal S 74 of the comparator 8 is not correct, and the correction signal S 76 used in the immediately preceding normal control operation is used. .

 The control unit 104 has the following functions. (0 In the initial start-up operation, the control signal S68 corresponding to the delay time calculated by actual measurement or calculation is output to the corrector 106 before operation starts. (Ii) In the normal control operation, the current The control signal S68 corresponding to the controlled delay time is continuously output to the compensator 106. (iii) In the control operation for the temperature and aging of the AMP system, the delay time is gradually increased. Alternatively, the control signal S68 corresponding to the delay time is output to the r corrector 106 so that the error level of the output signal S74 of the comparator 8 converges to 0. Reference numeral 106 denotes, for example, a programmable delay chip that delays by a corresponding delay amount according to a control signal S68 output from the control unit 104.

FIG. 6 is a flowchart of the τ correction. (a) At initial startup

At the time of initial startup, the delay time is accurately measured before the operation starts, and in step st16, the control unit 104 outputs a corresponding control signal S68, and in step st18, , corrector 1 0 6 Te, the control signal S 6 to 8 delays the reference clock CLK 1 only during the time delay corresponding to at _c step st 2 and outputting an a / D clock CLK 2, the digital signal S 5 0 Is entered. In step st4, the adder 2 adds the digital signal S50 and the correction signal S76 output from the holding unit 98, and outputs a signal S52. In step st6, the D.ZA converter 14 converts the signal S52 into an analog signal S54 in synchronization with the D / A clock CLK1.

 The mixer 18 converts the frequency of the analog signal S54 and outputs a signal S56. The first amplifier 20 amplifies the signal S56. The power blur 22 branches the signal S 58 and outputs a part of the signal S 60 to the second amplifier 24. The second amplifier 24 amplifies the signal S60. At step st8, the A / D converter 30 samples the signal S64 in synchronization with the A / D clocks CL and K2, and outputs the digital signal S66. At this time, at the time of initial startup, an accurate delay time is measured, and since the clock CLK1 is delayed by the delay time, the clock generation becomes negligible. In step st 10, the delay circuit 6 delays the signal S 50 for a fixed time and outputs a signal S 72. The comparator 6 outputs a difference signal S74 between the signal S66 and the signal S76 to the holding unit 98. At the time of the initial start-up operation, the holding unit 98 passes the signal S74 through to the adder 2 and holds the signal S74. Steps st2 to st12 and st20 are repeated. In step st 14, the detector 102 detects that the error level of the signal S 74 output from the comparator 6 is equal to or lower than a predetermined value, and outputs a signal S 70 indicating that the control operation is normal. Output.

 (b) Normal control operation

In the normal control operation, the control unit 104 continuously outputs the control signal S66 corresponding to the current delay time to the corrector 106 in step st16. The holding unit 98 outputs and holds the output signal S74 of the comparator 8 as the correction signal S76. <Thus, in the normal control operation, the delay time is changed by the corrector 106 in the normal control operation. Don't be Clock CLK 1 is delayed.

 (c) Control operation for temperature and aging of AMP system

 Since the delay time changes due to the temperature change of the AMP system ゃ 絰 yearly change, etc., the control signal S 68 output from the control unit 104 does not correspond to the correct delay amount.- The output S of the comparator 8 The error level of 7 4 exceeds a certain value. In step st 14, the detector 102 detects that the error level of the signal S 74 has exceeded a certain value, and performs a control operation on the temperature and aging of the AMP system so as to perform the control operation. And the control unit 10.4. In step st16, the control unit 10.4 controls the compensator 106 to gradually change the delay time so that the signal S74 converges to zero.

 In step st 18, the corrector 106 delays the clock CLK 1 by a delay amount corresponding to the control signal S 66. In step st20, the holding unit 98 outputs the held signal as a correction signal S76. In step st 14, when the detector 102 detects that the normal control operation has been started, the detector 102 keeps the detection signal S 70. And notifies the holding unit 98 and the control unit 104. At step st16, the control section 1Q4 continues to output the control signal S68 corresponding to the currently controlled delay time to the compensator 106. In step st 20, the holding unit 98 outputs and holds the signal S 74.

 Industrial applicability

 As described above, according to the present invention, the D / A conversion and the A / D conversion are performed at the same timing so that the peak jitter can be ignored, so that the accuracy of distortion compensation increases. Even if the reference clock is skipped or the clock is lost, the 0/8 conversion and the / 0 conversion are performed at the same timing, so failures are less likely to occur. Furthermore, since the control is made variably in accordance with the delay time changed by the temperature / year change, the distortion compensation is stably and effectively performed.

Claims

The scope of the claims 1. Digital distortion amplifier with distortion compensation type,  An adder for adding the first digital signal and the correction signal,  A digital / analog converter for converting an output signal of the adder to a first analog signal based on a first clock;  A first amplifier that amplifies at a first gain based on the first analog signal; and a second amplifier that amplifies an input signal based on an output signal of the first amplifier so as to match an input level of the input signal of the first amplifier. Amplifier and  An analog / digital converter for converting a signal based on the output signal of the second amplifier into a second digital signal based on a second clock;  The first clock is delayed for a time from when a signal is input to the digital / analog converter to when the signal is fed back to the analog / digital converter via the first amplifier and the second amplifier. A second delay circuit that delays the first digital signal and outputs a third digital signal; and a first delay circuit that outputs the second clock.  A comparator that outputs a difference signal between the second digital signal and the third digital signal as the correction signal,  A distortion-compensated amplification using a digital register system, comprising:  2. The first delay circuit is a variable delay circuit that delays an input signal based on a control signal indicating a delay amount, and a delay amount control unit that controls the delay amount of the first delay circuit based on the difference signal. The distortion-compensated amplifier according to claim 1, further comprising: a digital bridge-to-digital converter. 3. The delay amount control unit needs to change a delay amount of the first delay circuit based on a detector for detecting a level of the differential signal and a detection signal detected by the detector. If it is determined, the control unit variably controls the delay amount of the first delay circuit, and the control unit variably controls the delay amount of the first delay circuit, A holding unit that outputs a signal different from the signal output from the comparator to the adder as a correction signal, and otherwise outputs a signal output from the comparator to the adder as a correction signal. 3. The distortion-compensated amplifier according to claim 2, wherein the distortion-compensated amplifier is of a digital prism type.