WO2003088095A1 - Integrated circuit development method, program storage medium containing integrated circuit development method, system for concurrent development of asic and programmable logic device, development program, and development method - Google Patents

Abstract

An integrated circuit development method for generating a net list called a core (logical core) composed of a net connecting ports of a block not depending on a device technology by using only connection information in the block port specification which is a result of circuit architecture study and a part of logical design document, selecting blocks as objects from the core (logical core), grouping the blocks, and using the grouped core (logical core) data. A system for concurrent development of ASIC and FPGA is constituted by a fire wall for monitoring access from the Internet, a Web server for communicating with the Web client used by a user, an authentication server for performing user authentication, a user management server for managing a user, a logical synthesis server for executing an ASIC and FPGA development program, a mail server for distributing a mail to those associated with the project, a file server for storing design information, an application server for executing an ASIC implement design program, and a monitoring server for monitoring the ASCI and FPGA development state.

Description

 Description Integrated circuit development method and program storage medium storing the integrated circuit development method, and concurrent development system for ASIC and programmable logic device, development program and development method

 The present invention relates to a method for developing an integrated circuit, a program storage medium storing the method for developing an integrated circuit, a control device for a logic synthesis tool, and an ASIC and a programmable logic device used by a user from a computer connected to a network. It relates to concurrent development systems, development programs and development methods.

 More specifically, it relates to a method for configuring a programmable logic device in the development of integrated circuits, and uses only the connection information of the port specifications of the block, which is the result of studying the circuit architecture and is a part of the logic design document. Generates a netlist called a core (logical core) consisting of ports between ports of blocks that do not depend on each other, selects target blocks from the cores (logical cores), groups them, and groups the cores (logical cores) Integrated data development method using integrated data, and seamless concurrent development of ASICs and programmable logic devices, while ensuring both design quality and shortening the development period. ASICs and professionals that can reduce such human resources and costs Gramabu ^ / ■ Concurrent development system, development program and development method for logic devices. Background art

In the integrated circuit procedure, when deciding the specifications, first carefully consider whether there are any leaks, and then design according to the specifications. FIG. 11 is a flowchart showing the procedure for designing an integrated circuit. First, from the product specifications, ASIC Get the specifications of (IC) (gl). Next, we examine the circuit architecture (g2). Next, a circuit is designed based on the results of the circuit architecture study (g3). This circuit design is performed while performing logic verification (g4).

 Next, when the circuit design is completed, the logic of the circuit is synthesized (g5). When the logic synthesis is completed, the layout is developed based on the result of the logic synthesis (g6). At this stage, the circuit has been designed. After the circuit is designed, the circuit is manufactured (g7), and the actual machine is evaluated using the manufactured circuit (g8). In the above sequence, the part according to the present invention is the part relating to the logic synthesis in step g5.

 In the development of integrated circuits, the following flow is used to study functions to realize specifications as inputs and to study circuit configurations to realize functions. Normally, in the development of integrated circuits, the functions that realize the product are thoroughly identified from the product specifications, and the circuit configuration that realizes the identified functions is examined, and the IP (Inte 1 1 ectu 1 Proprty: intellectual property) Consider macros such as. Here, a macro refers to a macro that can be used without modification, such as RAM and ROM including IP.

 An initial estimate of the scale of the circuit or IP for which the configuration was studied is calculated.At this time, if the number of gates is known in advance, calculation is performed using the number of gates. It calculates the number of mouthpieces and estimates the realization scale. Here, a plurality of functions are grouped into one block based on the estimated scale and the number of input / output signals (hereinafter referred to as ports) of each function. This grouping is performed for all functions.

 In the logic design, a circuit design is performed for a programmable logic device by means of HDL (hardware description language) or the like based on the above-described functions and the estimated scale, and the on-board function evaluation is performed. After the evaluation was completed, re-design and re-verification were performed when converting to ASIC.

If the cost reduction by implementing AS IC is performed after the completion of the functional evaluation, the program-the AS from the point of designing for the logic device (for example, FPGA) It is rarely designed in consideration of Ic, and I / O buffers, device test circuits, macros such as memory, etc. are programmable. '' Programmable for ASICs due to differences between logic devices and ASICs '' Redesign occurs based on device design data, and double management of design data by redesigning, prolonging the development period and increasing development costs by redesigning and re-verifying functions are emerging. ASICs have a long development period but low cost, while programmable logic devices (FPGAs) have a short development period but high costs.

 The present invention has been made in view of such a problem, and has been developed in consideration of a circuit architecture applied to logic design in the development of a large-scale ASIC and concurrent (parallel) development of logic synthesis and layout. A method of generating an inter-block netlist as connection information between ports from port information of a block obtained by functionally dividing a block and port information of a chip (see Japanese Patent Application Laid-Open No. 2000-90042). The logic synthesis tool is controlled so as to generate an arbitrary size and number of blocks and interblock nets constituting blocks of an integrated circuit developed by the integrated circuit development method by applying the above method from the interblock netlist. A method and an integrated circuit for providing an apparatus, realizing an architecture, and avoiding redesign and reverification as much as possible. And its object is to provide a program storage medium storing a developing method of the road.

 In recent years, ASICs with more than 10M gates can be developed due to the miniaturization of semiconductors. However, as electronic devices have become more sophisticated and complex, specification design, logic design and floor planning, logic synthesis, It has become difficult to secure design quality as the implementation of layout design and timing verification has become longer and longer. In particular, the remake of ASIC development not only prolongs the development period of electronic equipment but also increases costs and leads to loss of opportunity for market introduction.

As a result, the TAT (Turn Around Time) is short and the design is easy to change. Logic devices are becoming more popular, but programmable logic devices are costly and difficult to miniaturize. ASICs are often used at the time of birth.

 However, even if verification is performed by prototyping a programmable logic device on the premise of ASIC implementation, it is difficult to reduce the total development turn in serial development from a logic device to an ASIC. There's a problem. In particular, if a timing problem occurs in the implementation design during ASIC development, there is a possibility that the redesign of the programmable logic device will start over, and if a third party such as a semiconductor vendor is outsourced, human resources at the outsourcing site will be required. And increase costs associated with securing human resources.

 Furthermore, if a redesign occurs exclusively for an ASIC due to the difference in structure between the programmable logic device and the ASIC device, not only will debugging with a programmable logic device become meaningless, but the development period will be prolonged and costs will increase. Also increase. Either way, you will lose the opportunity to get to the market.

 As a countermeasure for prolonging the development period due to the increase in the scale of ASICs, as described in Japanese Patent Application Laid-Open No. 2000-90042, circuit architecture study, logic design-verification, and implementation design were implemented. Although they are conducting concurrently, due to the complexity of electronic device functions and the speed of market movement, it has become difficult to shorten the development steps by lengthening the specification design, logic design, and verification. Furthermore, when developing concurrently, human resources and development tools with ASIC development knowledge are required, and there is a need for education on development tools that become more complex as semiconductor technology advances. Birth.

Therefore, the present invention enables seamless and concurrent development of ASICs and programmable logic devices, while ensuring both design quality and shortening the development period, and reducing human resources and costs involved in development. ASICs and programmable logic device concurrent development systems, development programs and 03 04787

It also aims to provide development and development methods. Disclosure of the invention

 FIG. 1 is a flowchart showing the principle of this effort method. The invention described in Claim 1 (1) is characterized in that the ASIC core (logical core) power, which is the connection information of the blocks and the port connection information, is arbitrarily selected by means of selecting and grouping any blocks having connection relations. Generates an HDL format core (logical core) that can be read by the logic synthesis tool ^^, which consists of the block and port connection information of the block and the number of blocks (step 1), and uses the logic synthesis tool from the chip terminal information. A temporary chip design is created, terminals are generated in this design (step 2), the same design as in step 2 is generated as cells inside the created design (step 3), and the same name between the design and the cell is created. Connect the ports (Step 4), insert device-technology dependent I / O buffers for the nets between the connected ports (Step 5), and Replace the cell with the core (logical core) created in Step 1 and expand the design hierarchy, which is the top hierarchy, to generate a netlist (Step 6).

In the invention described in claim 1, an entity that is a block port specification is created from a port name, a range, and an input / output definition and output to a file (writing to a file). Check that there is no mistake in the output port name of the output source instance specified for the input port of a certain block by means of creating an output signal file for the ports defined for input and output, and specify the device in the output source instance name. If there is a key word definition such as I / O to connect to the package terminal, the name in the output port name of the output source instance is used as the device package terminal name. Vector) means for judging whether the terminal is an input or output from the input / output definition, and means for judging whether the terminal is an input or output, and judging from the type definition whether the terminal is bidirectional. By means, create an entity that is a port specification of the core (logical core) and output it to a file. Where insta JP03 / 04787

A sense is a circuit unit.

 Means for checking whether a pair of the output source instance name of the block and the output port name of the output source instance exists in the output signal file when the block port is input-defined in the input / output definition; As a result of the check, if it is determined that a port connection between the instances is possible, a signal for connecting the instances is generated and output to a file. When the processing is completed, including checking all instances, the above-mentioned core (logical core) entities and inter-instance nets are read, and a core (logical core) is generated and output to a file.

 If there is no problem with the check result, the HDL (hardware hardware), which consists of the connection net between the block input / output port specifications and the instance, and the connection net between the instance and the external terminal that is the terminal of the device package, has no logical design part This is a computer-readable recording medium that stores a program that causes a computer to execute a method of outputting a file of a description language (hereinafter referred to as a core (logical core)).

 Therefore, according to the program storage medium storing a program for causing a computer to execute the method of generating a core (logical core) according to the first aspect of the present invention, a block serving as an input of an RTL design in integrated circuit development The quality of the port specifications can be ensured in advance, and in the development of large-scale integrated circuits with many functional blocks and large design resources, the connection between the blocks can be confirmed in advance, so It is possible to guarantee that the chip is assembled.

The invention described in claim 2 is an invention in which concurrent development of an ASIC and a programmable logic device is performed, and an arbitrary connection relationship is established from an ASIC core (logical core) comprising block connection information and port connection information. A core (logical core) consisting of port and port connection information of an arbitrary scale and number of blocks is generated by means of selecting and grouping the blocks (step 1), and logic synthesis is performed from the terminal information of the chip. A temporary chip design is created with the tool (Step 2), and a terminal is generated in this design with the name in the terminal information of the chip (Step 3). T JP03 / 04787

The same design as above is generated as a cell inside the cell (step 4), and the port created with the same name between the design and the cell created in step 2 is connected (step 5). An I / O buffer depending on the device technology is inserted from the information (step 6), the core (logical core) generated in step 1 is replaced with the cell (step 7), and the top hierarchy of this core (logical core) is obtained. The method is characterized in that the created design hierarchy is expanded to generate a netlist of programmable logic device chips (step 8).

 The invention described in claim 2 relates to the concurrent development of an ASIC and a programmable logic device. The functions of a logic synthesis tool from the ASIC core (logic core) according to claim 1 will be described later. A netlist generation method according to claims 3 and 4 is controlled by a control device equipped with a program storage medium storing a program for causing a computer to execute the method, and any blocks having a connection relation are grouped, An integrated circuit characterized by cutting out as a core of a programmable logic device (logic core), inserting an I / O buffer depending on a programmable logic device, and generating a netlist of chips of the programmable logic device. It is a development method.

 Therefore, according to the integrated circuit development method described in claim 2, since the ASIC core (logical core) is cut out as a programmer's logic device core (logical core) while retaining interblock connections, However, if verification of a programmable logic device using this core (logic core) is performed, it is possible to avoid duplication of verification with at least the same configuration in an ASIC. Therefore, concurrent development of ASIC and programmable logic devices can be efficiently promoted.

Also, when inserting the IZO buffer, a temporary core (logical core) is generated from the terminal information of the chip, and is replaced by a core (logical core) generated from the block. The port information of the chip and the terminal information of the chip can be cross-checked, ensuring the quality of both the block port specification and the chip terminal specification. 03 04787

8 You can

 The invention described in claim 3 is a method for selecting an arbitrary block having a connection relationship from an ASIC core (logical core) consisting of block port and port connection information and forming an arbitrary block by means of a group. It is characterized by generating a netlist consisting of block size and number of block ports and port connection information.

 With this configuration, it is possible to generate a netlist including ports of arbitrary size and number of blocks and connection information of the ports.

 The invention according to claim 4 is a method of selecting and grouping arbitrary blocks having a connection relationship from an ASIC core (logical core) comprising block port and port connection information, thereby providing blocks of an arbitrary size and number. A core (logical core) consisting of port-to-port connection information is generated (step 1), and a tentative chip design is created from the terminal information of the chip using a logic synthesis tool, and the terminal information of the chip is written in this design. A terminal is generated with the name in the report (step 2), the same design as above is generated as a cell therein (step 3), and a port having the same name is connected between the design and the cell (step 4). For this connection net, an I / O buffer depending on the device and technology is inserted from the terminal information of the chip (step 5), and the core generated in step 1 is (Logical core) is replaced with the cell (Step 6), and a chip net list is generated by expanding the design hierarchy created in Step 2, which is the top hierarchy of this core (Logical core) (Step 7). It is characterized by.

 With this configuration, it is possible to generate a chip netlist from a netlist composed of port information of ports of arbitrary size and number of blocks. The invention described in Claim 5 is a method for generating a netlist including ports of arbitrary size and number of blocks and connection information of the ports, and the port name of the top hierarchy is converted from the net name to the connection destination block. The feature is to modify the port name so that it matches the port name of the block, and to generate a netlist consisting of block ports and port connection information.

The invention described in claim 5 relates to an ASIC and a programmable logic device. 3 04787

In block concurrent development, it consists of block port and port connection information

ASIC cores (logical cores) When any arbitrary blocks that have a connection relationship are grouped together and cut out as programmable logic device cores (logical cores) using the functions of a logic synthesis tool, the cores that are usually cut out The port name at the top of (logical core) is the net name connected to the port.

 This is a logic synthesis tool control method characterized by controlling the function of the logic synthesis tool, tracing the net from the port to the inside of the core (logical core), and replacing it with the port name of the first block found. is there.

 Therefore, according to the storage medium storing the program for causing the logic synthesis tool to execute the method for generating the core of the programmable logic device (logical core) according to claim 5, it is possible to determine the function of the port. This can prevent a decrease in debugging efficiency such as logic verification when a net name that is difficult to use becomes a port name.

 As described above, a core (logical core) is generated from the data of the design document, and the core (logical core) is newly created for the programmable logic device while retaining the hierarchical structure and connection information. (Logical core) can be used to share the circuit architecture. The circuit data can be loaded, and the circuit data independent of the device technology in the instance whose function has been verified and the nets between the instances can be stored in ASICs. In this case, re-verification can be avoided, and re-design due to the difference between ASIC and programmable and magic devices can be avoided.

Further, in the present invention, an arbitrary block constituting the ASIC is selected from an ASIC core (logical core) consisting of connection information between the ports of the block and the ports, and the blocks are configured by the selected block. A logic synthesis tool control device that controls the generation of a programmable logic device core (logic core) consisting of block port-to-port connection information, consisting of blocks selected by the designer who generated the logic synthesis tool The logic synthesis tool assigns a port name to the port of the programmable logic device core (logic core) From the net connected to the port to the name of the port of the block that constitutes the connected programmable logic device, and from the terminal information of the chip, Means for generating a design of a temporary chip having a port specified by the terminal information with a logic synthesis tool, means for generating the design of the temporary chip as cells inside the design, and design of the temporary chip. Ports with the same name between cells are connected, and an I / O buffer depending on device technology is inserted from the chip terminal information into the connected net, and a logic synthesis tool whose name is changed is generated. Swap the core of a programmable logic device (logic core) consisting of blocks selected by the designer with senoré A stage, means for generating a chip netlist Pro Guramabunore ■ logic devices by developing the top-level of the core (logic core), characterized by including the capital.

 With this configuration, it is possible to generate a chip netlist of a programmable logic device.

The present invention also relates to a method for concurrently developing an ASIC and a programmable logic device, wherein functional blocks constituting the ASIC are grouped based on information on connection between ports, and ports and ports of the grouped functional blocks are provided. List generation step of generating a netlist consisting of interconnect information as a programmer's logic device core (logic core), and logic synthesis data for ASIC and programmable logic data from the circuit data of the functional blocks constituting the ASIC. A logic synthesis step of creating logic synthesis data for a device; and a programmable memory for the grouped functional blocks. The logic synthesis data for a magic device is inserted into the netlist generated in the netlist generation step and programmed. ■ Record the logic device circuit A ROM data generating step for generating the ROM data for actual machine evaluation, and an ASIC layout creation and timing verification using the ASIC logic synthesis data created in the logic synthesis step, by the ROM data generating step. Layers for generating and concurrently generating evaluation ROM data And a difference reflection step of reflecting a change in circuit data based on an actual device evaluation result using the ROM data generated in the ROM data generation step in the layout creation and timing verification of the ASIC. It is characterized by including.

 Further, the present invention is a concurrent development program for an ASIC and a programmable logic device, wherein functional blocks constituting the ASIC are grouped based on connection information between ports, and the ports of the grouped functional blocks are connected to each other. A netlist generation procedure for generating a netlist consisting of connection information as a core of a programmable logic device (logical core), and logic synthesis data for ASIC and programmable logic device from circuit data of a function block constituting the ASIC. A logic synthesis procedure for creating logic synthesis data, and a programmable logic logic data for the grouped function blocks are inserted into the netlist generated by the netlist generation procedure. Data generation procedure for generating actual machine evaluation ROM data that records the circuit of the ASIC, and ASIC layout creation and timing verification using the ASIC logic synthesis data created by the logic synthesis procedure. A rate creation procedure for performing concurrently with the generation of the ROM data for the actual device evaluation by the data generation procedure, and a change of the circuit data based on the actual device evaluation result using the ROM data generated by the ROM data generation procedure. The difference reflection procedure to be reflected in the layout creation and the timing verification, and the step of causing the computer to execute the steps are specially provided.

According to the invention, the function blocks constituting the ASIC are grouped based on the inter-port connection information, and the netlist including the grouped function block ports and the inter-port connection information is programmed / re-logic device. Logic synthesis data for ASICs and logic synthesis data for programmable logic devices are created from the circuit data of the function blocks that make up the ASIC. The logic synthesis data is inserted into the generated netlist to create a programmable logic Generates RM data for actual device evaluation that records the circuit of the ASIC device, and performs ASIC layout creation and timing verification using the created ASIC logic synthesis data concurrently with the generation of the RM data for actual device evaluation. Circuit data changes based on the actual machine evaluation results using the generated R〇M data are reflected in ASIC layout creation and timing verification, so efficient concurrent development of ASICs and programmable devices ASIC development time can be shortened.

 Further, the present invention is a concurrent development system of an ASIC and a programmer-free logic device, wherein functional blocks constituting the ASIC are grouped based on connection information between ports, and ports and ports of the grouped functional blocks are provided. Netlist generating means for generating a netlist consisting of indirect information as a core (logic core) of a programmable logic device; and logic synthesis data for ASIC and programmable logic from circuit data of function blocks constituting the ASIC. Logic synthesis means for creating logic synthesis data for the device; programmable logic data for the grouped function blocks; programmable by inserting the logic synthesis data for the logic device into the netlist generated by the netlist generation means. 'Logic device Data generating means for generating actual machine evaluation ROM data recording the circuit of the ASIC, and ASIC layout creation and timing verification using the ASIC logic synthesis data created by the logic synthesis means. And a layout generating means for concurrently generating the real machine evaluation ROM data by the data generating means and the layout generating means.

According to the present invention, the function blocks constituting the ASIC are grouped based on the inter-port connection information, and a netlist including the grouped function block ports and the inter-port connection information is programmed by a programmable logic device core (logical core). ) Logic synthesis data for ASIC and programmable 'Logic synthesis data for logic devices are created from the circuit data of the function blocks constituting the ASIC, and the logic synthesis data for the grouped function blocks are programmable' for logic devices. Logic synthesis data is inserted into the generated netlist to generate ROM data for actual equipment evaluation that records the programmable logic device circuits, and ASIC layout creation and timing verification are performed using the created ASIC logic synthesis data. Since the machine evaluation ROM data is generated and performed concurrently, efficient concurrent development of ASICs and programmable logic devices becomes possible, and the development period of ASICs can be shortened.

 The present invention also provides an ASIC logic synthesis means for executing logic synthesis of an ASIC in response to a user request in a concurrent development system of an ASIC and a programmable logic device used by a user from a computer connected to a network. ASIC logic synthesis result judging means for judging whether the logic synthesis result of the ASIC created by the ASIC logic synthesis means satisfies the speed performance requested by the user, and the ASIC logic synthesis result judging means Programmable logic device logic synthesis means for executing logic synthesis of a programmable logic device based on the determination result by the ASIC logic synthesis means executed by the ASIC logic synthesis means and programmable logic device logic synthesis means by the programmable logic device logic synthesis means '' Logic device logic Logic synthesis result display means for displaying the execution result of the synthesis on the computer; ASIC logic synthesis execution start and execution result by the ASIC logic synthesis means; and programmable logic device logic logic by the programmable logic device logic synthesis means. Logic synthesis notifying means for notifying the user of the start of execution of synthesis and the execution result by e-mail.

Further, the present invention provides a concurrent development method of an ASIC and a programmable logic device used by a user from a computer connected to a network, wherein the ASIC logic synthesis step executes logic synthesis of the ASIC in response to the user's request. An ASIC logic synthesis result determining step of determining whether the logic synthesis result of the ASIC created in the ASIC logic synthesis step satisfies the speed performance requested by the user; and Based on the judgment result, Programmable logic device logic synthesis process that executes logic synthesis of a logic device logic device, ASIC logic synthesis execution result by the ASIC logic synthesis process, and programmable logic device logic synthesis process by the programmable logic device logic synthesis process. A logic synthesis result display step of displaying the execution result of the ASIC logic synthesis on the computer, and an execution start and execution result of the ASIC logic synthesis by the ASIC logic synthesis step, and a programmable logic device logic synthesis by the programmable logic device logic synthesis step. A logic synthesis notifying step of notifying the user of the execution start and the execution result to the user by e-mail. According to the invention, the logic synthesis of the ASIC is executed in response to the request of the user, and the creation is performed. ASIC logic synthesis results Judge whether or not the speed meets the speed performance to be performed.Based on the judgment result, execute logic synthesis of the programmer's logic device, and execute the execution result of the ASIC logic synthesis and the execution result of the programmable logic device logic synthesis on the computer. The start of execution of ASIC logic synthesis and the execution result and the programmable logic device logic synthesis execution start and execution result are notified to the user by e-mail. There is no need to set up a user, the logic synthesis can be executed at any time, the quality of the synthesis can be kept uniform as if by a dedicated person, and the start of the logic synthesis and notification of the result can be received by e-mail. This eliminates the need to regularly check the progress of logic synthesis on a computer.

Also, the present invention provides a netlist generating means for generating a netlist including inter-port connection information of a plurality of function blocks specified by the user from a function block configuring the ASIC in response to the user's request, ROM data generating means for inserting ROM data of a logic-synthesized target functional block into a netlist generated by the netlist generating means to generate ROM data recording a circuit of a programmable logic device; ROM data generation result display means for displaying the generation result of the R〇M data generated by the ROM data generation means on the computer 4787

15 and a ROM data generation result notifying means for notifying the user of the generation result of the ROM data generated by the ROM data generating means to the user by e-mail.

 According to the present invention, a netlist including connection information between ports of a plurality of function blocks specified by a user is generated from a function block configuring an ASIC in response to a user request, and logical synthesis is performed on the generated netlist. By inserting the data of the target function block and generating ROM data that records the circuit of the programmable logic device, the generated results of the generated ROM data are displayed on a computer and the user is notified by e-mail. This eliminates the need for a dedicated development environment for programmable logic devices, reducing the load, time, and cost of creating ROM data that records the circuit of a programmable logic device. .

 Further, the present invention provides a method of using a temporary flip-flop or the like for the input terminal and the output terminal of the function block when the design of the function block configuring the ASIC specified by the user is not completed and there is no circuit data. And a temporary netlist generating means for generating a netlist incorporating the existing circuit.

 According to the present invention, when the design of the functional block constituting the ASIC specified by the user is not completed and there is no circuit data, a temporary flip-flop or the like is used for the input terminal and the output terminal of the function block. Since we decided to generate a netlist with the circuit inserted, we will proceed with prototyping verification of the programmable logic device even if the design of the functional blocks that are not to be verified has not been completed in the verification using prototype pink '. And the efficiency of verification can be improved.

Further, the present invention provides a monitoring means for monitoring the scale of change between the latest circuit data held by the user and the circuit data taken by the implementation designer in the implementation design, and a monitoring result and a rate design by the monitoring means. When the scheduled date and time is reached based on the time, the change is implemented in the ASIC implementation design. Change timing notifying means for notifying the user and the ASIC implementation designer of the timing of the reflection by e-mail, and in response to the change timing notifying means, the user sets the date of the reflection. And a reflection suspension requesting means for requesting suspension by changing.

 According to the present invention, the magnitude of a change between the latest circuit data held by the user and the circuit data taken by the implementation designer in the implementation design is monitored, and the plan designed based on the monitoring result and the time required for the layout design is described. When the time arrives, the user and the ASIC implementation designer are notified by e-mail that it is time to reflect the change to the ASIC implementation design, and the user changes the reflection date in response to this notification and stops. Changes can be efficiently reflected in the ASIC layout design, and the user can determine when changes can be made by setting the timing to reflect the changes. Schedule can be reviewed at an early stage.

On the other hand, the present invention provides a first design in which terminal information of an FPGA including all or a part of functional blocks of a plurality of functional blocks is described, and a first design described as a lower layer of the first design. From the second design in which the same terminal information as the FPGA is described, the design information for FPGA in which the same terminals in the first design and the second design are connected and a buffer corresponding to the FPGA is inserted between the terminals. On the other hand, a ^third design in which terminal information of an ASIC including the plurality of functional blocks is described, and a ^third design in which terminal information similar to that of the ASIC described as a lower layer of the third design are described. From the four designs, ASIC design information in which the same terminal between the third design and the fourth design is connected, and an ASIC-compatible buffer is inserted between the terminals, and the second design is generated. design It is characterized by generating netlists of FPGA and ASIC by replacing each of the fourth designs with circuit information generated based on the connection information of function blocks included in each design.

According to the present invention, on the other hand, all or some of the functional blocks of the plurality of functional blocks are provided. The first design, which describes the terminal information of the FPGA including the logic, and the second design, which describes the same terminal information as the FPGA described as the lower layer of the first design, from the first design, the second design Generates FPGA design information in which the same terminals in the design are connected and an FPGA-compatible buffer is inserted between the terminals. On the other hand, a third design in which the ASIC terminal information including a plurality of functional blocks is described And the fourth design in which the same terminal information as the ASIC described in the lower layer of the third design is described, the same terminals are connected between the third design and the fourth design, and between the terminals. Generates ASIC design information in which ASIC-compatible buffers are inserted, and converts the second and fourth designs based on the connection information of the function blocks included in each design. By replacing the information with information, a netlist for FPGAs and ASICs was created, enabling efficient concurrent development of ASICs and programmable logic devices and shortening the ASIC development period. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a flowchart showing the principle of the method of the present invention, FIG. 2 is an explanatory diagram of the operation of the first embodiment of the present invention, and FIG. 3 is a block diagram of the logic synthesis tool control device of the present invention. FIG. 4 is a block diagram illustrating an embodiment of a control device, and FIG. 5 is a flowchart illustrating a core (logical core) generation program. 1), FIG. 6 is a flowchart (2) showing a core (logical core) generation program, FIG. 7 is a flowchart showing a detailed procedure of the first embodiment of the present invention, and FIG. FIG. 9 is a flowchart showing a core (logical core) design check control. FIG. 9 is a flowchart showing a grouping control. FIG. 10 is a flowchart showing an I / O buffer input control. Processing image Fig. 11 is a flowchart showing the procedure for designing an integrated circuit. Fig. 12 explains the concept of concurrent development of ASIC and FPGA according to the second embodiment. FIG. 13 is a diagram for explaining the second embodiment. FIG. 14 is a functional block diagram showing a system configuration of a concurrent development system of AS IC and FPGA. FIG. 14 is a diagram showing an example of a directory configuration for storing data in a file server. FIG. 16 is a diagram showing an example of a logical CORE generation table. FIG. 16 is a flowchart showing a processing procedure of a concurrent development system of an AS IC and an FPGA according to the second embodiment. FIG. 18 is a diagram showing an example of a login screen, FIG. 18 is a diagram showing an example of a procedure screen, FIG. 19 is a flowchart showing a processing procedure of a logical CORE generation interface program, and FIG. FIG. 21 is a diagram showing an example of a logical CORE generation interface screen, FIG. 21 is a flowchart (1) showing a processing procedure of an AS IC logical CORE generation program, and FIG. FIG. 23 is a flowchart showing a processing procedure of a logical CORE check program, and FIG. 24 is a flowchart showing an example of a status display selection screen. FIG. 25 is a diagram showing an example of a logical CORE generation status screen. FIG. 26 is a flowchart showing a processing procedure on a logical CORE generation status display screen of an ASIC. FIG. 28 is a diagram showing an example of a CORE generation interface screen. FIG. 28 is a flowchart (1) showing a processing procedure of an FPGA logic CORE generation program. FIG. 29 is a flowchart showing a processing procedure of an FPGA logic CORE generation program. FIG. 30 is a flowchart showing an example of a compatible package table, and FIG. 31 is a flowchart showing a processing procedure of a logic synthesis interface program. FIG. 32 is a diagram showing an example of a logic synthesis interface screen, FIG. 33 is a flowchart showing an FPGA logic synthesis interface processing procedure, and FIG. 34 is an example of a logic synthesis status display screen FIG. 35 is a diagram showing an example of a fitting data input and execution screen. FIG. 36 is a diagram showing an example of a ROM data generation status screen. Fig. 38 is a diagram showing an example of the schedule and results screen. Fig. 38 is a diagram showing an example of the manual operation time. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1

 FIG. 2 is an operation explanatory diagram of Embodiment 1 of the present invention. In this figure, the circuit architecture is considered; ¾ is input, the design data is shared, and the integrated circuit is developed while sharing the circuit architecture.

 When designing a function to be realized by means of HDL, the chip, which is the product itself, is composed of instances that have a certain function. This instance refers to a block composed of multiple functions designed in HDL, and refers to multiple blocks if a specific block is necessary to realize the function of the chip. is there.

 The flow of the present invention will be described with reference to FIG. X, Y, and 、 are tables that define the port specifications of the block created from the results of the circuit architecture study in accordance with a defined format. These tables X, Υ, Ζ are always created when designing a block, and include the block name, instance name, port name, range, input / output, type, output source instance name, and output of the output source instance. It consists of a port name. These data are entered manually by the user. It is the point of the present invention to prepare each table in advance as described above.

 S1 receives the table data of all the above-mentioned instances as input, and checks whether the external terminals defined between the instances and between the instances and the terminals of the device package are connected without contradiction. This is the step of generating a core (logical core) consisting only of the port of the block and the connection information between the blocks by means of the definition. If there is an error in step S1, an error is returned to the user, and the user performs data entry again (circular arrow 1 in the figure indicates repetition).

S2 refers to the FPGA table ^^ 2, reads the core (logic core) of step S1 output into the logic synthesis tool, and creates a programmable logic device. Step S that selects a logic group by controlling the function of the logic synthesis tool, generates a new core (logical core) while maintaining the hierarchical information, and does not include the 1 / o buffer, etc., which depends on the device technology. This is the step of outputting the same core (logical core) netlist as the one output. In this figure, X and Y are user specified.

 The S3 generates a temporary core (logical core) from the terminal names of the device package terminal specification table data, which is a defined format 1, and temporarily stores the iZo buffer that depends on the specified device 'technology in the table data. This is the step of replacing the netlist with the output of step S2 after inserting it into the port of the core (logical core) of this step, which is the point of the present invention. After a netlist of the target device's chip is created by this process, the logic synthesis tool functions are controlled to read the logic-synthesized circuit data from the target device 'technology from the FPG Α synthesis result library 3 and respond. To complete the netlist of the desired device. The netlist generated as FPGA is fitted with the FPGA layout tool and converted to ROM data.

 Further, from step S2, the process is converted into an ASIC by referring to the ASIS synthesis result library 4.

 According to the first embodiment, in the development of an integrated circuit, there is an effect that the quality of a port specification of a block, which is an input of an RTL design, can be secured in advance, and further, there are many functional blocks, and large-scale integration with many design resources. In circuit development as well, it is possible to guarantee that the chip will be assembled by confirming the connection between the blocks in advance.

 FIG. 3 is a block diagram showing an embodiment of the logic synthesis tool control device of the present invention. In the figure, 22 is a control device for controlling the overall operation, 24 is a CRT for displaying various information, 21 is an input device for inputting various commands and the like to the control device 22, and 23 is a control device 22 It is a storage device that is connected to and stores various information.

Input device 21 is a core (logical core) generation program start command, logic synthesis The storage device 23 stores a logic synthesis tool, a core (logical core) generation program, and a logic synthesis control program. When a core (logical core) generation program start command is input from the input device 21 by specifying a block table file, the core (logical core) generation program reads the table file and generates a core (logical core). The file is output to the storage device 23. If there is an error during this process, the error information is displayed on the display device CRT 24.

 If there is an error, the designer corrects the table file and executes the command again. In the control of the logic synthesis tool, first, necessary data for control is prepared as a file, and a predetermined data in the storage device 23 is stored together with the core (logical core) file generated by the core (logical core) generating program. In the location. Then, when a control command of the logic synthesis tool is input from the input device 21, the logic synthesis tool is activated, and the processing result is displayed on the CRT 24. If the process fails in the middle, the status at the time of failure is displayed in CRT24.

 FIG. 4 is a block diagram showing an embodiment of the control device 22 of FIG. The same components as those in FIG. 3 are denoted by the same reference numerals. In the figure, 31 is a CPU for controlling the whole operation, 32 is a memory for storing various information, 21 is a keyboard for inputting various commands and the like, and 24 is a CRT as a display device. Reference numeral 23 denotes a storage device, which comprises a core (logical core) generation program 36, a logic synthesis tool control program 35, a logic synthesis tool 34, and an operating system (OS) 33. Reference numeral 37 denotes a path connecting the components. As the storage device 23, for example, a hard disk device is used.

 In the system configured as described above, when a command is input from the keyboard 21, the CPU 31 searches the storage device 23, calls a corresponding program, and executes the corresponding program.

FIGS. 5 and 6 are flowcharts showing a core (logical core) generation program. Here, the explanation will be made using the table data of X, Y, Ζ in FIG. The Reads the data files X, Υ, ブ ル (instances are also X, Υ, Ζ) and processes them one by one. F1 reads the data of X, F2 extracts all the data of the table of port し て, stores it in the memory, and performs the following processing while referring to the data in this memory. At F 2 ′, the port checks whether it is an output. Since port A is an input, skip step F3 of outputting the instance name and port name to file A, and proceed to F3 '. In F3, check whether the keyword connected to the package terminal has a certain force. Next, since there is no package terminal connection keyword, F4 for storing package terminal information in memory is skipped, and all data of the next port B is stored in memory.

 Since port B is an output, "XB" is output to file A of the storage device 23 in the step of F3. Where X is the file name and B is the port name. Next, since there is no connection key for the package terminal, F4 is skipped and all data of the next port Z is stored in the memory. Since the port Z is an output, “XZ [2: 0]” is output to the file A in step F3. Here, [2: 0] indicates 2, 1, 0.

 Next, since there is no connection keypad for the package terminal, F4 is skipped and all data of the next port I is stored in the memory. Since port I is an input, skip F3, and then there is a package terminal connection key word "IO", so "I NPU T, in, 2: 0" is used as the core (logical core) port name. Store in memory. Next, check whether all ports are terminated (F4,). If not, return to step F2.

 With this, the processing of all ports of X is completed, and if it is VHDL, an entity file having the following information is output to the storage device 23.

 A: instd-logic;

 B: o u t s t d l l o g i .c;

Z: outstd one logicvector (2 downto 0); I: instd one logic; The above processing is also performed on the data of Y and Ζ. When all the files are completed (F5,), if it is VHDL by the step of F6, the entity of the core (logical core) having the following information The file is output to the storage device 23.

 I NPUT: inst d_log ic;

 OUT: o u t s t d d l l o g i c;

The following data is recorded in file A.

 XB, XZ [2: 0], YC [1: 0], YO, ZF

 Next, the data of the file A is read in the step F7, stored in the memory in the step F8, and processed one file at a time. In step F8 ', check if the port is an input. Here, the table data of X will be described as an example. Since port A is an input, the output source Y and port name C are extracted in step F9, and YC [1: 0] is searched for in the data stored in F8 in the subsequent step F10. . Then check with F 10 'for a match.

 As a result of the search, it exists, so the following connection information is output to file B in the step of F12. If the results do not match, error information such as a difference in port name or range is output to a log file in the storage device 23 and displayed on the CRT 24.

 A => YC

Next, similarly, since port B is an output, the following connection information is output to file B in step F11.

 B => XB

Next, similarly, since port Z is an output, the following connection information is output to file B in step F11.

 z => xz

Next, although port I is an input, "IOI NPUT" cannot be found in the search of the step F10, and is output to the log file as an error in the step F13, and is also displayed on the CRT 24. However, the port connected to the package terminal In this case, there is no problem. On the other hand, the error information output to the log can be used to confirm which port of which instance is connected to which terminal of the package. Next, in step F12, the following connection information is output to file / file B.

 I => I O I NPUT

In step F12 ', it is checked whether all ports in all tables have been completed. If not, the flow returns to step F8'.

 The above processing is also performed for the tape data of Y and Ζ. When the processing is completed, the port for which connection information could not be created is output to the log file by the step of F14, and the port is output by the step of F6 by the step of F15. Combine the entity list of the core (logical core) with the connection information output in steps F11 and F12, generate a netlist of the core (logical core), output it to storage device 23, and terminate the program .

 Next, a detailed procedure of the first embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart showing a detailed procedure of the first embodiment of the present invention. This flowchart shows in detail the processing in and after S2 in which the core (logical core) output in S1 in the first embodiment described with reference to FIG. 2 is input. In the figure, the solid line indicates the flow of processing, and the dashed line indicates the flow of data. Before executing the processing, operate the input device and, if necessary, the core (logical core) output in step S2 to the location in the storage device where the control program refers to the control file described in the following description. Prepare by copying or other means.

First, check the core (logical core) design (a 1). Then, check whether the core (logical core) design is OK (a 1 ′). ₀ If not OK, check the table data described in FIG. 2 and execute again (a l′ O). If 〇K, group by referring to files 12 and 13 (a 2) and store as core (logical core) 10. Next, a dummy core (logical core) is generated with reference to Table 4 consisting of the terminal name and buffer name (a3). As a result, a dummy core (logical core) 11 is generated. Next, an I / O buffer is inserted based on the dummy core (logical core) 11 and the table 14 (a4). Next, the core (logical core) 10 and the dummy core (logical core) 11 are compared and checked (a5). Then, it is checked whether or not it is OK (a 5 ′). As a result of the comparison, if it is OK, termination processing is performed (a 6). If it is not OK, check the terminal specifications of the device package (a 9), check the tape data shown in FIG. 2 and execute again (a 10).

 When the termination processing of step a6 is completed, the circuit data is inserted with reference to the synthesis result file 15 (a7), and the DFT circuit is inserted with reference to the file 16 (a8).

 Next, each step described in FIG. 7 will be described in more detail. FIG. 8 is a flowchart showing a core (logical core) design check control. First, check if there is a core (logical core) file (a11), and if so, read it with a logic synthesis tool (a12). If not, do nothing. In step a1 (see Fig. 7), the core (logical core) output in step S2 is used as input, and the HDL description grammar of the core (logical core), an empty input port, and the like are checked. If the file exists, the core (logical core) is read by the logic synthesis tool in step a12. The logic synthesis tool has a function to check the grammar, etc. when it is read. If the result is an error, the content is checked on the CRT, and as shown in step a10, a tape node describing port specifications of the block is written. Review the data and perform the design check again.

FIG. 9 is a flowchart showing the grouping control, and shows the details of step a2 in FIG. First, it checks whether there is a file of the core (logical core) (a13), and if so, checks whether there is a file of the instance to be grouped (a14). In some cases, that is, when there is no problem with the result of step a1, if there is a file 13 in which the names of blocks to be converted into programmable logic devices are written one block at a time, read them (a2 1) While maintaining the hierarchical information of the target block, logical integration is performed as a new core (logical core). 'Control the grouping function of the tool by grouping (a22).

 When the grouping function is used, the port name of the core (logical core) becomes the net name connecting the instances, so that all the ports of the core (logical core) go inside the core (logical core). Traces the net, generates a new port on the core (logical core) with the port name of the first instance found, and generates a net connected to the port of the core (logical core) that is the name of the net. Connect to the port and delete the port that is the net name (a23). This is to create a new port and delete the old port.

 Next, check whether there is monitor port information (a23,). In some cases, a port is generated for the core (logical core) with the port name of the specified instance, and connected to the terminal of the block (a24). If not, a netlist that does not include an IZO buffer or the like that depends on the device technology is output to the storage device 10 (see FIG. 7) (a25). In this case, on the display device, it can be confirmed using the display function of the logic synthesis tool.

 In this step a2, if necessary, the ports of the grouped blocks can be generated as ports of the core (logical core) (a24). Use this function when there is a port you want to monitor when evaluating the function of a programmable logic device. The specification method is performed by reading a file in which the port names are described one by one per line as shown in File 12 after grouping and port name change.

Up to this point, since the designer himself generates the core (logical core) using the data that determines the port specifications of the block, the port connection between the blocks in the core (logical core) should be correct. However, in the case of an ASIC that uses the core (logical core) generated in step S1 (see Fig. 2) as it is, the terminal name of the device package defined in the table data of the block in the core (logical core) is the device package. It is common to refer to the terminal specifications of this item, so there may be differences due to simple mistakes or changes from the printed circuit board design. Conversely, step a 2 ( If the port of the core (logical core) generated in (7) becomes a terminal of the device package, there is a possibility that there is a difference as described above because the port becomes the specification. This problem is solved by steps a3 to a5.

 FIG. 10 is a diagram showing a flow chart showing the IZO buffer insertion control and a processing image. This flowchart shows the process of step a4 in FIG. In the following explanation, a 3 to a 5 are different, but the processing is one command — a series of processing.

 First, it is checked whether there is a file of external terminal information and a core (logical core) (al5). In some cases, the following processing is performed. In a3, unlike a2, the pin specification of the device package that defines the terminal name in the first column and the I / O buffer name depending on the device technology used in the second column as shown in 14 in Fig. 7 If the table data exists, it is read and a dummy chip design (first design describing the terminal information of the name of the first column) is created (a 31), and the dummy chip Is generated as a cell (a second design describing the same terminal information as the first design described as a lower layer of the first design), and the ports of the same name between the design and the cell are connected and stored. Outputs dummy core (logical core) to device 11.

 In step a4, the dummy core (logical core) of the storage device 11 is read, and the I / 〇 buffer in the second column of the terminal package tape data 14 of the device package is replaced with the dummy core (logical core). An I-noise buffer depending on the device technology is inserted from the terminal information of the chip into the net (a32).

In step a5, of the ports of the dummy core (logical core), the ports for testing, etc., which are unique to the device and have no relation to the function and are not related to the logic, are deleted, and the core (logical core) of the storage device 10 is used as an internal cell (A33), and check whether there is any mismatch of the terminal names (a33 '). If all the port names match between the two cores (logical cores), the insertion is successful. In this way, the terminal name of the terminal specification table data of the device package and the port name of the core (logical core) can be clicked. Loss check can be performed and the above problems can be solved. If there is, the process ends; otherwise, the netlist is output.

 If it fails, check the terminal specifications of the device package as shown in step a9 and re-execute from step a3, or use table data that defines the terminal specifications of the block as shown in step a10. Check and re-run from step S1 (see Fig. 2). If successful, it becomes a chip by expanding the core (logical core) hierarchy.

 In step a6, flip-flops are connected to the input / output ports of all blocks of the chip inside the block and terminated. This terminating process is for generating a netlist without any problem even if there is a block for which circuit design has not been completed, thereby enabling a layout operation.

 In step a7, the logic-synthesized circuit data is read from the library of the synthesis result, and inserted into the corresponding block. At this time, if there is no synthesis result for the block inside the chip and the design name or cell name of the block complies with the naming rule, the input port and output port of the block are preliminarily specified. Then, connection processing is performed inside the block.

 This processing does not exist in the case of a programmable logic device, and is performed when a specific block such as DLL of a program-logic device is used as an ASIC. The architecture can be maintained by connecting this block inside the block without deleting this block. If a block such as a memory exists inside the block, replace it with the circuit data of the device-specific memory.

 a8 is a process in the case of ASIC, in which an SCAN test circuit for automatically testing a device is automatically inserted, or a file 16 that defines a sequence of blocks for connecting the SCAN test circuit is input and connected in the defined order.

As described above, according to the first embodiment, the core (logical core) is generated from the data from the design document, and the hierarchical structure and the connection information are held from this core (logical core). · New core for logic devices (Logic Generating a core) has the effect of sharing the circuit architecture. This core (logical core) is filled with circuit data and its function is verified. This network can avoid re-verification when it is converted to AS IC. Therefore, there is an effect that the concurrent development of the AS IC and the programmable logic device can be efficiently advanced.

Embodiment 2.

 Next, the concurrent development system of ASIC and FPGA according to the present invention will be described in detail. The logic design language includes C language, UML, and the like. In the second embodiment, HDL is described as the design language.

 First, the concept of concurrent development of ASIC and FPGA according to the second embodiment will be described. FIG. 12 is an explanatory diagram for explaining the concept of concurrent development of an ASIC and an FPGA according to the second embodiment. As shown in the figure, the feature of this concurrent development of ASICs and FPGAs is that in order for the prototyping verification by the FPGA to proceed concurrently with the AS IC implementation design, a ROM that records the FPGA circuit necessary for prototyping verification The data can be provided from the AS IC implementation design, and the development of FPGA and AS IC can be done seamlessly.

 In this concurrent development of AS IC and FPGA, considering the prototyping verification by FPGA in the circuit architecture study, the division of the realization function in the realization circuit of an appropriate expected scale, the structural difference between AS IC and FPGA The functions related to the above are hierarchized, and a common function block configuration between ASIC and FPGA design and port specifications of function blocks are created. The function block configuration and port specification data of the function block are common data for the floor plan, logic synthesis, and layout design of the ASIC implementation design.

In RTL design and verification, RTL design common to AS IC and FPGA is performed according to the structure of the circuit architecture study result, and logic analysis is performed with emphasis on corner cases for each function. Perform software verification using a certification tool. Perform logic synthesis of the AS IC concurrently with this RTL design verification, and if the same characteristics as the AS I can be secured, then perform logic synthesis of the FPGA and form the circuit in the FPGA on the sequential prototyping board. And enable verification by FPGA prototyping.

 On the other hand, in the AS IC layout, based on the common functional block configuration between the ASIC and the FPGA design, the verification results by the soft verification and prototyping are reflected constantly as needed, and the verification by FPGA prototyping is performed. To shorten the period from completion of AS IC development to completion of AS IC development.

 Next, a system configuration of a concurrent development system of ASIC and FPGA according to the second embodiment will be described. FIG. 13 is a function block diagram showing a system configuration of a concurrent development system of ASIC and FPGA according to the second embodiment. As shown in the figure, this concurrent development system 200 of AS IC and FPGA includes a firewall 210, a web server 220, a user authentication server 230, a user management server 240, a logic synthesis server 250, and a mail server. Server 260, a file server 270, an application server 280, and a monitoring server 290. The concurrent development system 200 of ASIC and FPGA can be used from the Web client 100 via the Internet.

 The firewall 210 is a computer that accepts only an access request according to a set communication procedure in response to an access request from the Internet, and prevents an unauthorized external access to the concurrent development system 200 of the AS IC and the FPGA. prevent.

The web server 220 is a computer that transmits information in response to a request from the web client 100 made through the Internet, and has connection information between a port of a function block and a port of a function block constituting an AS IC or FPGA. Logic CORE generation interface program for generating a logical CORE from only logic synthesis interface program 222, fitting interface Program 223, a status display interface program 224, a format file required for generating a logical CORE and a format file required for logic synthesis, and the computer executes these programs in response to a request from the web client 100. And send the result to the Web client 100.

The user authentication server 230 is a computer for authenticating a user, and a user name and a password to be used based on a contract are registered. User management server 240, a user of the registration, a computer to perform the deletion, logic synthesis server 250 p _r oject name and e-mail address, which will be described later with the user name you want to use on the basis of the contract has been registered, AS IC logic A computer having a CORE generation program 251, an FPG A logic CORE generation program 252, an AS IC logic synthesis program 253, an FPG A logic synthesis program 254, and a fitting program 255 that is an FPGA layout. The logic synthesis and fitting program in the logic synthesis server 250 is started from the logic synthesis interface program 222, reads the RTL source stored in the file server 270, and executes the logic synthesis and FPG A of AS IC and FPGA. Perform PGA fitting.

 The mail server 260 is a computer having mail sending / receiving software, and distributes processing information executed from the web server 220 and information from the web client 100 to the user and the system.

 The file server 270 is a storage medium for storing a logic synthesis target RTL source, a logic synthesis result, FPG A ROM data, and the like. FIG. 14 is a diagram showing an example of a directory structure for storing data in a file server. Project 41 shown in the figure is a directory of the Project name for developing ASIC and FPGA or a nickname of ASIC, and this name is set based on the contract.

I〇42 is a directory that stores data for generating a logical CORE. There is a directory ASIC48 for storing a logical CORE generation table file describing the port specifications of the functional blocks shown in Fig. 15, and a logical CORE generation interface program 221 for each functional block constituting the AS IC. And a directory FPGA 49 for copying and storing the file of the logical core generation tape in the directory AS IC 48 in accordance with the specification of the user. In addition, under the directory FPGA49, there are directories of the number of FPGA numbers specified by the user. The details of the logical CORE generation table and the logical CORE generation interface program 221 will be described later.

 CORE 43 is a directory for storing the logical CORE generated by the logical CORE generation program. The directory AS IC 50 for storing the logical CORE of the AS IC generated from the port specifications of the functional blocks constituting the AS I I, and the FPG It has a directory FPGA51 that stores the logic CORE of the FPGA from the port specifications of the functional blocks that make up A.

 The RTL44 is a directory that stores circuit design data (hereinafter referred to as RTL) expressed in HDL (hardware description language) uploaded by the user from the logic synthesis interface described later, and is a functional block that constitutes the logic CORE of ASIC. SYNTHES IS45, which has a directory AS I C52 to store in units and a directory F PGA 53 to copy and store the RTL in the AS IC directory according to the user's specification, is the result of logical synthesis of the RTL by the logical synthesis server 250. A directory that stores the results of AS IC logic synthesis in units of functional blocks that make up the logic core of AS IC AS AS 54, and stores the results of logic synthesis for each FPGA Has a directory F PGA 55 with a directory to be changed.

The ROM 46 is a directory for storing ROM data for storing FPGA circuit data generated after the fitting, which is a layout of the FPGA based on the logic synthesis result of the FPGA, and a directory for storing for each FPGA. Have. LAYO UT47 is a work directory where a layout designer of AS IC designs a layout of AS IC.

 The application server 280 is a computer having a program for performing floor planning, layout design, and timing verification of ASIC. With this computer, the implementation designer performs the ASIC floor plan, layout design, and timing verification.

 The monitoring server 290 acquires the user name and the project name registered in the user management server 240, and stores the data in the directory of each project name in the directory LAYOUT 47 managed by the implementation designer. The time required by the tool to compare the data with the data in other directories, synthesize the data, and process the layout twice a day, twice a day, the first being the changes to the implementation designer This is a computer that notifies the user and updates the schedule to reflect changes based on the second collected time.

 Next, a processing procedure of the concurrent development system 200 of the ASIC and the FPGA according to the second embodiment will be described. FIG. 16 is a flowchart showing a processing procedure of the concurrent development system 200 of ASIC and FPGA according to the second embodiment. As shown in FIG. 16, the concurrent development system 200 of AS IC and FPGA is used. When accessing using the web client 100, the web server 220 sends display control data of the login screen shown in FIG. 17 to the web client 100, and the web client 100 displays the screen based on the received data. To When the user inputs the user name and password registered based on the contract on this login screen and presses the Login button, the web client 100 sends the user name and password to the web server 220. .

 The web server 220 sends the received user name and password to the user authentication server 2

Contact 30. The user authentication server 230 checks whether or not the user name and the password are registered (step S501), and compares the result with the Web server 22. Returns to 0. The web server 220 is rejected by the user authentication server 230

Then, the display control data of the login rejection screen is sent to the web client 100, and the web client 100 displays the login rejection on the screen based on the received data and ends (step S502).

 When the web server 220 receives the login from the user authentication server 230, the web server 220 sends display control data of the procedure screen shown in FIG. 18 to the web client 100, and the web client 100 performs the procedure based on the received data. The screen is displayed (step S503). ·

 The user selects a menu according to the procedure screen shown in Fig. 18 and performs concurrent development of PGA with 31〇. When the user selects “Format 1” and “Format 2” (Yes in step S504), the format files required for the target design in the web server 220 are downloaded to the web client 100 ( Step S505).

 “Format 1” is the format data of the logical CORE generation table shown in FIG. “Format 2” is the format of a tape drive that defines the AS IC package pin names and pin numbers used in AS IC logic synthesis described later, and defines the IO buffer that electrically interfaces between the AS IC and external devices. Data.

 When the user selects the logical CORE generation (Yes in step S506), the web client 100 sends to the web server 220 that the logical core generation is selected, and the web server 220 sends the logical core generation interface program 221. Is started (step S507).

 When the user selects the logic synthesis (Yes in step S508), the Web client 100 sends the selection of the logic synthesis to the web server 220, and the web server 220 transmits the logic synthesis interface program 222. Activate (Step S509).

When the user selects the fitting (Yes at step S510), the Web Ryan MO 0 sends the selection of the fitting to the web server 220, and the web server 220 activates the fitting interface program 223 (step S511).

 When the user selects the status display (Yes in step S512), the web client 10◦ sends the selection of the status display to the web server 220, and the web server 220 displays the status display The interface program 224 is started (step S5 13).

 Next, the processing procedure of the logical CORE generation interface program 221 will be described. FIG. 19 is a flowchart showing a processing procedure of the logical CORE generation interface program 221. As shown in the figure, the logical CORE generation interface program 221 sends display control data of the logical CORE generation interface screen shown in FIG. 20 to the web server 220, and the web server 220 receives the display control data. The display control data of the logical CORE generation interface screen is sent to the Web client 100, and the Web client 100 displays the logical CORE generation interface screen based on the received display control data of the logical CORE generation interface screen. It is displayed (step S8001).

The user inputs a project name, selects an execution button, and follows a file selection screen displayed by the web client 100 to display a function block of an AS IC for generating a logical core of the AS IC according to a file selection screen. _D that specifies the file of the logical CORE generation table shown in Fig. 15 that defines the IO specifications

The web client 100 sends the specified data of the project and the file of the logical CORE generation table of the IO to the web server 220, and the web server 220 stores the file in the file server 270 in FIG. Create directories such as I〇42, CORE43, RTL44, SYNTHESIS45, ROM46, LAYOUT47, etc. (step S802), and generate a logical CORE in the directory AS IC48 under I042. Stores the file of the tape inserter, specifies the project name, executes the ASIC logic CORE generation program 251, and executes the process ID. Is stored in the memory (step S803).

 Here, the processing procedure of the ASIC logical core generation program 251 will be described. FIGS. 21 and 22 are flowcharts showing the processing procedure of the ASIC logic CORE generation program 251. As shown in FIG. 21, the ASIC logical CORE generation program 251 reads the logical CORE generation tables X, Y, and 示 し shown in FIG. 15 from the directory AS I C48 of FIG. The processing is performed one by one.

 The logical CORE generation tables X, Y, and Ζ are tables that define the port specifications of the functional blocks created from the results of the circuit architecture study according to the defined “Format 1”. This table is always created when designing a functional block, and includes the function block name, instance name, port name, range, input / output, type, output source instance name, output port name of the output source instance, etc. Consisting of An instance refers to a functional block that constitutes an ASIC. When multiple function blocks having the same function are used, the name of this instance is changed and inserted.

 First, the data of X is read (step S1001), all data of the table ^ "of port A is extracted and stored in the memory (step S1002), and it is checked whether or not port A is an output (step S1003). As a result, since port A is an input, the presence or absence of the package terminal connection keyword "I0 ,," is checked next (step S1005). As a result, since there is no connection keyword "IO", all data of the next port B is stored in the memory.

Since port B is an output, "XB" is output as a file to directory AS IC 50 in FIG. 14 under the name of A (step S1004). Next, since there is no package terminal connection keyword "IO", all data of the next port Z is stored in the memory. Since port Z is an output, output "XZ [2: 0]" to file A. Next, since there is no connection key "IO" for the package terminal, all data of the next port I is stored in the memory. Since port I is an input, and next there is a package terminal connection key word "IO", "INPUT, in, 2: 0" is stored in the memory as a logical CORE port name (step S1006). This completes the processing of all ports of X (Yes in step S1007), and stores an entity file defining port names, input / output and range information in accordance with the HDL syntax in the directory AS IC 50 in FIG. To output the file (step S1008). The output contents for VHDL are as follows.

 A: in std— logic;

 B: out std ー ogic;

 Z: out std—logic one vector (2 downto 0);

 I: in std—logic;

 Then, the above processing is also performed on the data of Y and Ζ. Also, at this stage, the following data is recorded in file Α.

 XB, XZ [2: 0], YC [1: 0], YO, ZF

 When the processing of all the files X, Υ, and 上 記 is completed (Yes at Step S1009), the data of the file Α (Step S1010) is read and stored in the memory (Step S1011), and the processing is performed one file at a time. Do. Here, the table data of X will be described as an example. First, it is checked whether or not the port A is an input (step S1012). As a result, since the port A is an input, the output source Y and the port name C are extracted (step S1013). Then, the memory is searched with YC [1: 0] (step S1014), and the presence or absence of matching data is checked (step S1016). As a result, since the matching data exists in the memory, the following connection information is output to the directory ASIC 50 in FIG. 14 as a file with the name B (step S1018). If the results do not match, error information such as a different port name or range is output to a log file in the directory ASIC 50 (step S1017).

A => YC Similarly, since port B is an output, the following connection information is output to file B of directory AS IC 50 (step S1015).

 B => XB

 Similarly, since port Z is an output, the following connection information is output to file B of directory ASIC 50.

 Z => XZ

 Similarly, since port I is an input and "'IO I NPUT" cannot be found by searching, an error is output to the log file in directory AS IC 50. However, this is not a problem in the case of a port connected to a package terminal. Conversely, the error information output to the port can confirm which port of which instance is connected to which terminal of the package. Next, the following connection information is output to the file / file B of the directory A SIC 50.

 I => I O I NPUT

 When the above processing is performed on the table data of Υ and Ζ and the processing is completed (Yes at step S1019), the port for which the connection information could not be created is output to a log file (step S1020). The entity file of the logical CORE of the AS IC having the information as described above is output to the directory AS IC 50 (step S1021).

 INPUT: in std— logic;

 OUT: out std_logic;

 Also, the logical CORE entity file is combined with the connection information, and the logical CORE of the AS IC is output to the directory AS IC 50 as a file with the project name specified in FIG. 17, and the processing is terminated. The processing returns to the logic CORE generation interface program 221 (step S1022).

The logical CORE generation interface program 221 searches the log files in the directory AS IC 50 for errors. If an error has been recorded (Yes at step S804), the error is read (step S805), and P The mail address, error information, and process ID of the user obtained by querying the user management server 240 with the P roject name, and the process ID are sent to the mail server 260, and mail is sent from the mail server 260 to the user (step S 806). The user confirms the contents of the error with this e-mail and repeats the logical CORE generation process until the error disappears.

 On the other hand, if no error is recorded in the log file (rejection of step S804), the proc name, the e-mail address of the user obtained by querying the user management server 240 with the proc name, the process ID, The logical CORE generation end message and the mail server 260 are sent to the mail server 260 (step S807), and the mail is sent from the mail server 260 to the user.

 In addition, a directory is created in the directory AS IC 50 with the name of “CORE + process ID + date and time”, and the logical CORE and log files generated under the project name are moved to this directory in the directory AS IC 50. Create a directory with the name of IO in the directory, move the table data in the directory AS I C48 used to generate the logical CORE to this I〇 directory, and add this project to the logical CORE check program in the logic synthesis server 250. Specify the directory name of the logical core created with the name “C〇RE + process ID + date and time” and start the logical CORE check program (step S808).

 This logical CORE check program checks the syntax of the ASIC's logical CORE, checks the unconnected state of the input / output ports of each instance that constitutes the logical CORE, and describes the commands of the logic synthesis tool to output a report. ing.

Here, the processing procedure of the logical CORE check program will be described. FIG. 23 is a flowchart showing a processing procedure of the logical CORE check program. This logical CORE check program is located under the directory of the received project name, and the AS IC Check if there is a logical CORE directory (step S1201), and if so, create a WORK directory in the ASIC directory where the logical CORE directory is located (step S1202), and The synthesis tool performs a check (step S1203).

 When the execution is completed, error information is extracted from the report file in the WORK directory, and the user ID obtained by querying the user management server 240 with the project name and the process ID extracted from the logical CORE directory name At the same time, the mail is sent to the mail server 260, and the mail is sent from the mail server 260 to the user (step S1204). The user confirms the intendedness of the error information in the content of the sent mail.

 The logical C ORE generated by this series of steps guarantees that it will always be built as an AS I C unless there is a connection error between the instances that constitute the A S IC in the user's logic design. This effect appears in logic verification. If the operation of a plurality of instances constituting the AS I C is performed in a different manner than expected in the function verification, the connection between the instances can be guaranteed, so that it is possible to perform debugging focused on each function constituting the instance.

Next, the processing when the user selects the status display on the procedure screen of FIG. 18 will be described. When the user selects the status display on the procedure screen shown in FIG. 18, the status display interface program 224 is started. The status display interface program 224 sends the display control data of the status display selection screen shown in FIG. 24 to the web server 220, and the web server 220 transmits the received display control data of the status display selection screen to the web client 100. And the Web client 100 displays the screen based on the received display control data of the status display selection screen. When the user selects the logical CRE creation on this screen, the status display interface program 224 generates display control data without the logical CORE name display on the logical CORE generation status screen shown in FIG. b server 220, and the web server 220 transmits the received logical CORE generation status screen display control data to the web server 220. Send to the b client 100, and the web client 100 displays the screen based on the received display control data of the logical core generation status screen.

 On this screen, when the user inputs the Project name and selects the display button, the Web client 100 sends the Project name to the Web server 220 and receives the Project name from the Web server 220, a status display interface program. 224 extracts the directory name of the logical CORE in the directory AS IC 50 in FIG. 14 from the directory of the designated project name, updates the display control data on the logical CORE generation status screen, and sends it to the web server 220. Web server 220 sends the received display control data of the logical CORE generation status screen to Web client 100, and Web client 100 displays the screen based on the received logical CORE generation status display control data. I do. This screen shows the directory name of the previously created ASIC logical core.

 Here, the processing procedure on the logical core generation status display screen of ASIC will be described. FIG. 26 is a flowchart showing a processing procedure on the logical CORE generation status display screen of ASIC. As shown in the figure, when the user selects one of the displayed logical cores and selects download (step S1501), the target logical core can be downloaded to the web client 100. (Step S 1502). The downloaded logical CORE can be used for logic verification as an ASIC chip-level netlist, and enables debugging that focuses on the functions that make up the instance as described above.

On the other hand, when the user specifies the logical CORE name and selects the FPG conversion button (step S1503), the Web client 100 confirms that the Project name, the logical CORE name, and the F PGA conversion have been selected. The data is sent to the b server 220, and the web server 220 sends the received data to the status display interface program 224. The status display interface program 224 extracts the file name of the table data in the I〇 directory under the directory of the target logical CORE name in the directory AS IC 50 in FIG. Figure Create the display control data of the FPGA logic CORE generation interface screen as shown in (1) and send it to the Web server 220.

 The web server 220 sends the received display control data of the FPGA logic CORE generation interface screen to the web client 100, and the web client 100 displays the screen based on the received display control data of the FPGA logic CORE generation interface screen. It is displayed (step S1504). In this screen, a list of the specified Project name, fflunli CORE name, and instance names constituting the logical CORE are listed in the left list box. In this screen, it is also possible to change the target logical CORE. If the user specifies a Project name and a logical CORE name, the screen is updated by the same processing specified in FIG. Furthermore, this screen is an interface for generating the FPGA logic CORE from the table data of the instances that make up the target AS IC logic CORE, and the user specifies the instance from the left list box and clicks the add button. Select to add an instance to the right list box. The instance listed in the right list box is one FPGA. When the user selects an instance, sets the FPGA name and the FPGA number, which is a unique integer of 1 or more, which is an additional number for management, and selects an execution button, the Web client 100 and the target P The roject name, the logical CORE name of the AS IC, the FPGA name, the list of instance names to be used as the FPGA, and the FPGA number are sent to the web server 220, and the web server 220 displays the status of the received data. Send to interface program 224.

Then, the status display interface program 224 creates a directory with the number of the FPGA specified in the directory FPGA49 in FIG. 14 according to the received list of instance names, and creates a directory named CORE in the directory AS I C50 in FIG. The table data with the same name is copied from the IO directory below to the directory with the above number, and the FPGA logic CORE generation program 252 is executed with the list of table data names as an argument. Here, the processing procedure of the FPGA logic CORE generation program 252 will be described. FIG. 28 and FIG. 29 are flowcharts showing the processing procedure of the FPGA logic CORE generation program 252. FIG. 28 is the same as the process shown in FIG. 21, and FIG. 29 is the same as the process shown in FIG. 22 except for step S1717 and step S1720. Explanation of steps In step S1017 of Fig. 22, if the instance name of the connection partner defined for the input port of the target instance and the output port name are not in the information stored in the memory, an error occurs. However, in step S1717 in Fig. 29, the connection between the ports of the instances was originally guaranteed as the logic CORE of the AS IC, so in this step S1717, not the error but the input terminal information of the package And store it in memory.

 In step S1020 in FIG. 22, the information about the unconnected ports that have finally been left is output to the log file. On the other hand, in step S1720, the log file and the step S in the directory of the logical CORE of the target AS IC created by “CORE + process ID + date” under the directory AS IC 50 in FIG. The log file output in step 1720 is compared, and an output port not included in the log file output in step S1020 is additionally stored in the memory as output terminal information of the package. Thereafter, a logical CORE is output as a file with the designated FPG A name in the designated directory under the directory FPGA 51 in FIG. 14 in the same manner as the processing in step S1020.

And the status display interface program 224 is? . The logical 001 E file is read, the number of terminals that become the input and output of the package is counted, and the ratio of all the IOs in the second column of the compatible package table shown in Fig. 30 is calculated, and the package with the largest ratio is calculated. and extracting the compatible package data, the package name of F PGA logic CORE generating interface screen shown in FIG. 27, and updates the screen display control data I_〇 utilization, sent to We b server ² 20. We b sir The bar 220 sends the received display control data of the FPGA logic CORE generation interface screen to the web client 100, and the web client 100 displays the input screen based on the received display control data of the FPGA logic CORE generation interface screen. Update.

 If the user is not satisfied with this result, re-generate the FPGA logic CORE again. When the user selects the decision, the web client 100 sends the decision and the F PGA number, the package name, and the data of the IO usage to the web server 220, and the web server 220 transmits the data. The received status display interface program 224 creates a directory with the number specified in the directory FPGA55 in FIG. 14, and outputs the received data in the form of a plist, for example, in the form of a file.

 Next, the processing procedure of the logic synthesis interface program 222 will be described. FIG. 31 is a flowchart showing a processing procedure of the logic synthesis interface program 222. As shown in the figure, the logic synthesis interface program 222 sends display control data of a logic synthesis interface screen as shown in FIG. 32 to the web server 220, and the web server 220 receives the logic synthesis interface screen. Is transmitted to the web client 100, and the web client 100 displays a screen based on the received display control data of the logic synthesis interface screen (step S2001).

 The user specifies the name of the project, the name of the target logical CORE displayed in Fig. 25, the name of the functional block to be synthesized, and the number of the FPG A to be incorporated. Specifying De bug (do not execute logic synthesis of FPGA) or Fix (execute logic synthesis of FPGA) (Step S 2002), and select the execution button (Step S 2003) The web client 100 displays a data selection screen.

When the user selects an RTL source to perform logic synthesis according to this screen, the Web client 100 sends these data to the Web server 220, and the Web server The logic synthesis interface program 222 that has received the data from the 220 creates a directory with the designated function block name in the directory AS IC 52 of FIG. 14 and stores the RTL source in the directory AS IC 52 (step S2004). Then, the RTL source was read one file at a time, and the operating frequency data defined by the user was extracted in the header that describes the change history and version number in the RTL source, and the value was increased by 20% from the extracted value. Execute the AS IC logic synthesis program 253 of the AS IC logic synthesis tool by specifying the functional block name of the logic synthesis target with the frequency value and the speed-first or area-first logic synthesis condition specified by the user as the constraint of the logic synthesis. (Step S 2005).

 When the logic synthesis of the AS IC is completed, the logic synthesis interface program 222 generates a report file output by the AS IC logic synthesis program 253 in the directory of the specified functional block under the directory AS IC 54 in FIG. The mail address and block name of the user obtained by inquiring of the user management server 240 with the project name are sent to the mail server 260, and the mail is transmitted from the mail server 260 to the user (step S2006).

 Then, the logic synthesis interface program 222 executes this processing for all the RTL sources existing in the directory created under the specified function block name under the directory ASIC 52 in FIG. When the logic synthesis of all RTL sources is completed (Yes in step S2007), the logic synthesis interface program 222 reports the result of logic synthesis of all RTLs when speed priority is specified (Yes in step S2008). To determine whether the force satisfies the operating frequency defined in the RTL source (step S2009 to step S2010). Nothing is done in case of emphasis on area.

Next, the F i X designation is checked (step S 2011). If the F i X designation is made, the logic synthesis interface program 222 creates a directory under the directory FPGA 55 in FIG. 14 with the designated FPGA number. The R in the specified function block directory under the directory AS IC 52 in FIG. The TL is copied and stored, and the FPGA logic synthesis interface program is executed using the specified project name and FPGA number as arguments (step S2012).

 Then, the logic synthesis interface program 222 activates the logic synthesis tool, and issues a command to the logic synthesis tool using the logic CORE of the specified logic core in the specified logic core in the directory AS IC 5 ° in FIG. A file that defines the package pin assignment of the AS IC, which is uploaded from the user and exists in the directory AS IC 54 in FIG. 14, and a buffer that electrically interfaces with an external device connected to the AS IC. By loading commands into the logic synthesis tool according to the definition, the test circuit, such as the buffer and scan of the AS IC, is inserted between the chip pins connected to the logic core terminal of the AS IC and the package terminal. 14 and the functional blocks in all directories under the directory AS IC 52 in FIG. Data is input into the logic synthesis tool by reading commands and loaded into the logic CORE, and a netlist of AS IC is generated for layout design, and a file is output as a project name to the directory AS IC 54 in Fig. 14. (Step S 2013).

Next, the processing procedure of the FPGA logic synthesis interface program will be described. FIG. 33 is a flowchart showing a processing procedure of the FPGA logic synthesis interface program. As shown in the figure, this FPGA logic synthesis interface program creates a directory in the directory FPGA55 in FIG. 14 with the FPGA number specified by the logic synthesis interface program of the ASIC, and creates a directory in FIG. The FTL source in the directory with the specified number under the bird F PGA53 is read one file at a time, and the operating frequency data defined by the user in a part of the header that describes the change history, version number, etc. in the RTL source And execute the FPGA logic synthesis program 254 of the FPGA logic synthesis tool by specifying the function block name of the logic synthesis target as the logic synthesis constraint with the frequency value increased by 20% from the extracted value as the logic synthesis constraint. (Step S2201). When the logic synthesis of the FPGA is completed, the FPGA logic synthesis program 254 outputs the logic synthesis result to the directory of the target number in the directory FPGA55 in FIG. 14 by the name of the functional block. By doing so, the user can proceed with the design work while checking the gut usage rate on the logic synthesis status display in FIG. 34 described later. Then, the FPGA logic synthesis interface program sends to the mail server 260 the logic synthesis end message, the FPGA number, the block name, and the mail address of the user who has inquired of the user management server 240 with the project name. The mail is transmitted from the mail server 260 to the user (step S2202).

 Next, the FPGA logic synthesis interface program confirms that the logic synthesis of all the functional blocks constituting the FPGA of the designated number has been completed (step S2203). This confirmation is performed by extracting the name of the function block in the directory of the number targeted for the directory FPGA 51 in FIG. 14 and comparing it with the name of the function block for which the logic synthesis has been completed. If there is no difference, then the FPGA logic synthesis interface program extracts the file name of the logic CORE, which is the FPGA name in the directory of the target number in the directory FPG A51 in FIG. In the directory of Fig. 14, the FPGA 55 defines the layout of the FPG A, the correspondence between the package pin names and pin numbers that are the same as the port names of the logic CORE of the FPGA used for fitting, the operating frequency, etc. It is checked whether the fitting control file thus uploaded exists from the user (step S2206).

If it exists, the FPGA logic synthesis interface program specifies all functional blocks constituting the FPGA and the logic CORE of the FPGA in the directory of the target number under the directory FPGA 51 in FIG. Run synthesis program 254. Then, when the logic synthesis of the FPGA is completed, the FPG A logic synthesis interface program starts the fitting program 255 and inputs the netlist of the logic synthesis result to the fitting program 255. Then, ROM data that is the layout result of the FPGA and records the circuit information is generated, and output to the directory of the target number under the directory ROM 46 in FIG. 14 with the FPGA name (step S2207). Then, the end message of the ROM data generation, the FPGA number, the Project name, and the user's e-mail address obtained by inquiring of the user management server 240 are sent to the e-mail server 260, and the e-mail is transmitted. Yes (step S2208).

 If there is a difference, it is determined whether or not an execution button is selected on the input and execution screen of the fitting data described later (step S2204), and if not selected, the process is terminated. For all function blocks that have not yet been set, flip-flops are provided for all input / output ports inside each function block in the logic CORE of FPG A in the directory of the target number under the directory F PGA 51 in FIG. Connect the output ports of all flip-flops on the input side to an appropriate gate, for example, the input port of a 2-input NAND, and connect the outputs of all NAND gates to the input ports of a new 2-input NAND gate. Connect, repeat the multi-stage connection of 2-input NAND as described above, and enter the HDL description that connects the output of the final 2-input NAND to the input ports of all flip-flops on the output side. Can be logically synthesized The state is set (step S2205).

 After that, the process is the same as when there is no difference. Power depending on the verification strategy at the start of development In the case of a functional block configuration that can be largely divided into upstream and downstream in circuit architecture study, use a dummy circuit using the above-mentioned flip-flop As a result, if the design of the upstream function is completed, verification can be performed even if the design of the downstream function is incomplete, which greatly contributes to efficient verification.

Next, the logic composition status display screen of FIG. 34 will be described. This screen is displayed when the user selects the logic synthesis in the status display screen of Fig. 24 with the web client 100, the web client 100 sends the selection of the logic synthesis to the web server 220, and the web server Status display interface that received data from 220 The program 224 queries the user management server 240 with the name of the logged-in user for all project names obtained from the user management server 240. The logical program in the directory of all numbers under the directory FPG A 55 in FIG. Extract the gate size from the synthesis result.

 Then, the package information is extracted from the plist in the same directory created by the FPGA logic CORE generation described above, and based on this package information, the gate scale ratio in the table of FIG. The following packages are selected, and the display control data of the logic synthesis status display screen shown in FIG. 34 is generated and sent to the web server 220. The web server 220 sends the display control data of the logic synthesis status display screen to the web client 100, and the web client 100 displays the screen based on the received display control data of the logic synthesis status display screen. I do.

 Here, the gate size ratio of 75% is briefly explained. Usually, the F PGA logic synthesis tool suggests an appropriate package and gate utilization from the database of the logic synthesis tool based on the gate size of the logic synthesis result. However, in the fitting of the FPGA, a unit block that realizes logic by the FPGA is used for wiring in order to increase the efficiency of the arrangement and the di in the process of arranging the cells. Therefore, considering that the gate size will be larger than the result of logic synthesis, the gate utilization rate after fitting is set to 75% so that it does not exceed 100%, and it may be different for FPGA. . For this reason, it is effective to execute the FPGA logic synthesis described above for each function block.

Next, the fitting data input and execution screen will be described. FIG. 35 is a diagram showing an example of a fitting data input and execution screen. When the user selects the fitting in the procedure screen shown in FIG. 18 with the web client 100, the web client 100 sends the selection of the fitting to the web server 220 and the web server 2 The fitting interface program 2 23 which received the data from the server 20 receives the query name from the user management server 240 using the name of the logged-in user. And the file name of the netlist that is the result of logic synthesis in each directory, that is, the FPGA name under the directory F PGA 55, is extracted, and the fitting data input and execution screen shown in Fig. 35 are displayed. Generates display control data and sends it to the Web server 220.

 The web server 220 sends the fitting data input and execution screen display control data to the web client 100, and the web client 100 receives the fitting data and executes the received screen display control data based on the received fitting data. Display the screen. When the condition data input on this screen is selected, the web client 100 displays a data selection screen.

 According to this screen, when the user selects the fitting control file described above, the web client 100 sends the selected FPGA number and the fitting control file to the web server 220, and transmits data from the web server 220. The received fitting interface program 223 stores the fitting control file in the directory of the target number under the directory FPGA 55 in FIG.

 When the user selects the execution button, the web client 100 sends the selected FPGA number, the project name, and the execution selection to the web server 220, and sends the data from the web server 220 to the web server 220. The fitting interface program 223 receiving the command executes the FPGA logic synthesis interface program using the project name and the FPGA number as arguments. The processing of the FPGA logic synthesis interface program is as described above.

 Next, the ROM data generation status screen will be described. FIG. 36 is a diagram showing an example of a ROM data generation status screen. When the user selects R〇M data on the status display selection screen shown in FIG. 24 with the Web client 100, the Web client 100 sends a message to the Web server 220 that the ROM data has been selected.

The status display interface program 224 that has received the data from the web server 220 queries the user management server 240 with the name of the logged-in user. For all the obtained project names, the number names of all directories under the directory ROM 46 in FIG. 14 and the ROM data name, that is, the FPGA name as the fitting result in each directory, were extracted, and the results are shown in FIG. 36. The display control data of the ROM data generation status screen is generated and sent to the web server 220.

 The web server 220 sends the display control data of the ROM data generation status screen to the web client 100, and the web client 100 displays the screen based on the received display control data of the ROM data generation status screen. The user can download the ROM data by selecting the attached part of the target FPGA on this screen.

 Next, the processing of the monitoring server 290 will be described. First, what the monitoring server 290 monitors is used for implementation design based on whether RTL has been changed, the time required for logic synthesis, fitting, layout design tool processing, and the scale of function block changes defined by the designer. This is the time required for manual work required to reflect changes, other than the processing time of the tool to be used.

 The directory LAYOUT47 in Fig. 14 managed by the implementation designer has a directory named Project for each Project, and work proceeds in that directory. In the directory with each project name, there is a LAY directory that stores the layout design data and an RTL directory that stores the RTL source. The directories below the RTL directory are the same as the directories AS IC 52 and below in Fig. 14. It has a configuration.

The monitoring server 290 monitors the LAY and RTL directories. The schedule reflecting the results of the aggregation of time is stored in the directory named Project under the name of Schedu 1 e. In the initial state, based on the contract, the scheduled date of 1 stR TL and Sign Of f Is set. 1s tRTL is defined as an RTL for which layout design can be undertaken, no major changes are expected at that time, and functional verification has been completed about 80%. Sign Off is to pass AS IC manufacturing data to device vendor after completion of AS IC layout design Day.

 FIG. 37 is a diagram showing an example of the schedule and results screen. In the figure, the Schedu1e file is converted into screen display control data, and is displayed by the Web client 100. That is, when the user selects the result and the schedule on the status display screen of FIG. 24, the web client 100 displays the status that the result and the schedule are selected via the web server 220. Send to interface program 2 2 4 The status display interface program 2 2 4 receiving the selection of the result and schedule converts the Schema 1 e file into screen display control data and sends it to the web client 100 via the web server 220. . The Web client 100 that has received the screen display control data displays a screen based on the screen display control data.

 FIG. 38 is a diagram showing an example of a work time setting file set by a layout designer. This file is stored under the name MANUA1 in the same directory as the SCHEDU1 file.

 When the monitoring time comes, the monitoring server 290 acquires the user name, the Project name to which the user belongs, and the mail address from the user management server 240. Then, the Sch edu 1e file is read, and the scheduled date of 1 st RTL is extracted. If this scheduled date is later than the monitoring execution date, nothing is done and the process ends. If the scheduled date is earlier than the monitoring execution date 0, the subsequent processing is executed.

 First, if there is no RTL source in the RTL directory in the directory V named Project under the LYAOT directory managed by the implementation designer, the processing is interrupted. If there is an RTL source, a comparison is made between the RTL sources in the directory of each block under the directory ASIC52 in FIG.

If there is a difference, the block name with the difference, the project name, and the mail address of the implement designer are sent to the mail server 260, and the mail server 260 sends it to the implement designer. The implementation designer will use this email to estimate how long it will take to reflect the changes. As a result of the estimation, the implementation designer updates or adds time data in the Schema 1 Caro, delete.

 Next, the monitoring server 290 extracts the names of the blocks constituting the ASIC from the logical CORE of the ASIC with the latest creation time under the directory ASIC50 in FIG. 14 and stores the extracted block names in the memory. Then, the logic synthesis processing time is extracted from the report file of the logic synthesis result in the directory of each block under the directory ASIC 54 in FIG. If there is no report file for the block name previously stored in the memory, that is, if logical synthesis has not yet been performed, apply the average time of the time extracted from the existing report file, calculate the total time, and store it in the memory I do.

 This time, among the layout design results in the directory named Project under the directory LAYOUT 47 of FIG. 14 managed by the implementation designer, a file of the timing verification result which is the final step of the layout design process If exists, the processing time is extracted from the processing result file output by the tool used in the entire process of the layout design, and the total time is calculated by combining the processing time with the time previously stored in the memory. If the timing verification result file does not exist, the time set by the layout designer in advance and temporarily set in the monitoring server is applied at the time of contract.

 Next, the monitoring server 290 calculates the number of days by taking the sum of the total time and the time set in Manua 1 described above as 1 day to 12 hours, and saves the Schedu 1 e file. Update if necessary. In other words, in the initial state, the Schedule 1 e file has only the scheduled date of 1st RTL, and the total time is added to this scheduled date, and as shown in Fig. 37, it is implemented as the reflection start date. Add a planned date for incorporating changes to the design.

In the next monitoring, if the reflection start date is later than the monitoring execution date, compare and compare the number of days from the 1st RTL scheduled date, which is one time before the reflection start date, to the scheduled date set as the reflection start date. The reflection start date is not updated if it is longer than the calculated number of days for the implementation design. When the reflection start date is before the monitoring execution date, the monitoring server 290 provides the user and the implementation designer with the e-mail addresses and the opportunity to start the reflection. Message to the mail-server 260, and mail is sent from the mail server 260 to the user and the implementation designer. At this time, if the newest reflection start date is before the date of monitoring execution, the monitoring server 290 does not update the Schemadu 1 e file unless there is no actual date on the actual reflection start date. .

 When the approval and rejection emails from both the user and the designer arrive at the monitoring server 290 for the message email that is the opportunity to start the reflection, if both are approved, the Schedu 1 e file is immediately reflected. Set the date when the e-mail was received on the actual date of the start date, and in the next monitoring, the latest scheduled reflection date is before the monitoring date of 13th, and the actual date of the scheduled reflection date is If so, calculate the number of days for implementation design based on track record 13 and add a new reflection start date. If this process is continued, the reflection start date approaches Sig nO f.

 When the scheduled date of the reflection start date is calculated, and if the date exceeds the Sign Off date, the monitoring server 290 sends the message and the user who have reached the date and time when the scheduled date of the reflection start cannot be set. And the e-mail address of the implement designer to the mail server 260, and mail is sent from the mail server 260 to both sides.

 If the user has rejected the email of the message that is the opportunity to start the reflection, the mail server sends a message to the user to set the scheduled date from the Web client 100 and the mail address of the user and the implementation designer. Send to 260 and send mail from mail server 260 to both sides.

Next, the schedule and results screens will be described. FIG. 37 is a diagram showing an example of the schedule and results screen. The logical FIX button and the change button in the figure are before the execution date S of the monitoring of the monitoring server 290, and are arranged beside the newest reflection start date. When the user specifies the date in the date field below this button and selects the change button, the web client 1000 displays that the set date and the change have been selected. The status program that sent the data to the eb server 220 and received the data from the web server 220, the interface program 224 sets the scheduled date of the latest reflection start date in the schedule file to the specified date. Changes, and a message stating that the changes The mail addresses of the user and the implementation designer are sent to the mail server 260, and mail is sent from the mail server 260 to both sides.

 If the logical F i X button in FIG. 37 is selected together with the date (≡!), The status display interface program 224 performs the same processing as when the change button is selected, and then executes the monitoring server Performs the process of stopping monitoring at 290. This will clarify the short-term goals of both the user and the implementation designer, and the greater the number of trials of the implementation design, the more likely the change start date will be. In response to this, it is possible for both the user and the implementation designer to give an opportunity to think about how to proceed, and as a result, greatly contribute to the improvement of efficiency.

 As described above, in the second embodiment, the AS IC logic synthesis program 253 performs AS IC logic synthesis based on a user request from the Web client 100, and the FPGA logic synthesis program 254 The logic synthesis of A is performed, the logic synthesis interface program 222 displays the result of the logic synthesis of AS IC and FPGA on the Web client 100, and the mail server 260 starts the logic synthesis of AS IC and FPGA and the result. Is notified to the user by e-mail, so that the user does not need to have a dedicated logic synthesis person, the logic synthesis can be executed at any time, and the quality of the logic synthesis is kept uniform as if the dedicated staff executed it. As well as being able to receive the start of logic synthesis and notification of the result by e-mail, there is no need to periodically check the progress of logic synthesis on a computer.

Also, in the second embodiment, based on a user request from the web client 100, the AS IC logical core generation program 251 specifies a plurality of function block ports designated by the user from the function blocks constituting the AS IC. ROM data that records the programmable logic device circuit by generating a netlist consisting only of interconnection information and inserting the data of the logic-synthesized target function block into the netlist generated by the FPGA logic CORE generation program 252. And displays the results of the ROM data generated by the logical CORE generation interface program 221 on a computer, and the mail server 260 e-mails the user. The notification configuration eliminates the need for a dedicated development environment for programmable logic devices, reducing the load, time, and cost of creating ROM data that records the circuits of programmable logic devices. be able to. Further, in the second embodiment, when the design of the function block that constitutes the ASIC specified by the user is not completed and there is no circuit data, the FPGA logic CORE generation program 252 uses the input terminal of the function block and the Because a netlist that incorporates a circuit using a temporary flip-flop at the output terminal is generated, the design of a functional block that is not the target of verification is verified in verification by prototyping of a programmable device. Even if it has not been completed, verification by prototyping can be advanced, and verification efficiency can be improved.

 Further, in the second embodiment, the monitoring server 290 monitors the scale of the change between the latest circuit data held by the user and the circuit data incorporated by the implementation designer in the implementation design, and monitors the monitoring result and When the planned date and time is reached based on the time taken for the layout design, the main server 260 notifies the user and the ASIC implementation designer by e-mail that it is time to reflect the changes to the ASIC implementation design. However, in response to this notification, the user has requested the stop by changing the date of reflection, so that the generated change can be efficiently reflected in the ASIC layout design, and the timing of reflecting the change Setting allows the user to determine when changes can be made. It is a review of Yuru.

 As described above, according to the present invention, the following effects can be obtained.

According to the first aspect of the present invention, there is provided a program storage medium storing a program for causing a computer to execute a method of generating a core (logical core) according to the first aspect of the present invention. In development, it has the effect of ensuring the quality of the port specifications of the block that will be the input of the RTL design in advance.In addition, even in the development of a large-scale integrated circuit with many functional blocks and large design resources, Ensure that the chip is assembled by confirming the connection of be able to.

 According to the invention set forth in claim 2, the core (logical core) is cut out from the ASIC core (logical core) as a program 'logic device core (logical core) while maintaining the connection between blocks. By verifying the programmable logic device used, ASICs can at least avoid duplication of verification with the same configuration. Therefore, concurrent development of ASIC and programmable logic devices can be efficiently promoted.

 In addition, when inserting an IZO buffer, a temporary core (logical core) is generated from the chip terminal information, and is replaced with a core (logical core) generated from the block. The port information of the chip and the terminal information of the chip can be cross-checked, and the quality of both the port specification of the block and the chip terminal specification can be ensured.

 According to the invention set forth in claim 3, it is possible to generate a netlist including ports of arbitrary scale and number of blocks and connection information of the ports.

 According to the invention described in claim 4, a chip net list can be generated from a net list including ports of arbitrary size and number of blocks and connection information of the ports.

According to the invention described in claim 5, according to the storage medium storing a program for causing a logic synthesis tool to execute a method of generating a core (logic core) of a programmable logic device, the function of the port is determined. It is possible to prevent a decrease in debugging efficiency such as logic verification when a net name that is difficult to perform becomes a port name. As described above, a core (logical core) is generated from the data of the design document, and the core (logical core) is newly programmed for the logic device while maintaining the hierarchical structure and connection information. (Logical core) can be used to share the circuit architecture. The circuit data can be loaded, and the circuit data independent of the device technology in the instance whose function has been verified and the nets between the instances can be stored in ASICs. ASICs can be used to avoid re-verification. It is also possible to avoid redesign due to differences between programmable logic devices.

 As described above, according to the present invention, there is provided an integrated circuit development method capable of realizing architecture sharing and avoiding redesign and re-verification as much as possible, and a programmable storage medium storing the integrated circuit development method. be able to.

 Further, according to the present invention, the functional blocks constituting the ASIC are grouped based on the inter-port connection information, and the netlist including the ports of the grouped functional blocks and the inter-port connection information is converted into a programmable logic device. Generates ASIC logic synthesis data and programmable logic device logic synthesis data from the circuit data of the functional blocks that make up the ASIC, generated as a core (logic core), and creates programmable logic for the functional blocks that are grouped. The logic synthesis data for the device is inserted into the generated netlist to generate ROM data for the evaluation of the actual device that records the circuit of the programmable logic device, and the ASIC layout is created using the logic synthesis data created for the ASIC. And timing verification of ROM data for actual machine evaluation This is done concurrently with the generation, and the circuit data changes based on the evaluation results of the actual machine using the generated ROM data are reflected in the ASIC layout creation and timing verification. This enables effective concurrent development, and shortens the ASIC development period.

Further, according to the present invention, the function blocks constituting the ASIC are grouped based on the inter-port connection information, and the netlist including the grouped function block ports and the inter-port connection information is used as the core of the programmable logic device. Logic synthesis data for ASICs and programmable logic synthesis data for logic devices created from the circuit data of the functional blocks that make up the ASIC, and programmable logic devices for the functional blocks that are grouped. Logic data for programmable logic devices was inserted into the generated netlist to generate logic data for evaluation of actual devices. ASIC layout creation and timing verification using logic synthesis data for ICs are performed concurrently with the generation of ROM data for actual machine evaluation, enabling efficient concurrent development of ASICs and programmable logic devices. This has the effect of shortening the development period of the ASIC.

 Further, according to the present invention, logic synthesis of an ASIC is executed in response to a user request, and it is determined whether or not the created logic synthesis result of the ASIC satisfies the speed performance requested by the user, and based on the determination result. Performs logic synthesis of programmable logic devices, displays the results of ASIC logic synthesis and the results of programmable logic device logic synthesis on a computer, and starts and executes the results of ASIC logic synthesis and programmable logic devices. The user is notified of the start of logic synthesis execution and the execution result by e-mail, so there is no need for the user to assign a dedicated logic synthesis user. As described above, the quality of the logic synthesis can be kept uniform, and the start of the logic synthesis and the notification of the result can be received by e-mail. Can, there is an effect that need to check periodically computer Susumu涉 logic synthesis is eliminated.

 Further, according to the present invention, a netlist including port-to-port connection information of a plurality of functional blocks specified by a user is generated from a functional block configuring an ASIC in response to a user request, and the generated netlist is generated. Generates ROM data that records the circuit of the programmable logic device by filling in the data of the logic-synthesized target function block, displays the generated ROM data on a computer, and notifies the user by e-mail. This eliminates the need for a dedicated development environment for programmable logic devices, reducing the load, time, and cost of creating ROM data that records the circuits of programmable logic devices. This has the effect that it can be performed.

Further, according to the present invention, when the design of the functional block constituting the ASIC designated by the user is not completed and there is no circuit data, a temporary flip-flop or the like is applied to the input terminal and the output terminal of the function block. Netlist with inserted circuit Therefore, even if the design of a functional block that is not the target of verification has not been completed in verification by prototyping of a programmable logic device, verification by prototyping can be advanced, and verification efficiency can be improved. If it can be achieved, it will have a ray effect.

 Further, according to the present invention, the scale of a change between the latest circuit data held by the user and the circuit data incorporated in the implementation design by the implementation designer is monitored, and based on the monitoring result and the time required for the layout design! At the scheduled date and time, the user and the ASIC implementation designer are notified by electronic mail that it is time to reflect the change in the ASIC implementation design, and the user reflects in response to this notification Since the stop was requested by changing the date of the change, the generated change can be efficiently reflected in the ASIC layout design, and by setting the timing to reflect the change, the user can change until how long. It is possible to judge whether or not the schedule is possible, and it is possible to review the schedule at an early stage.

According to the present invention, on the other hand, a first design in which terminal information of an FPGA including all or some functional blocks of a plurality of functional blocks is described, and an FPGA described as a lower layer of the first design From the second design in which the same terminal information is described, the design information for the FPGA is generated in which the same terminals in the first design and the second design are connected and a buffer corresponding to the FPGA is inserted between the terminals. On the other hand, a third design in which terminal information of an ASIC including a plurality of functional blocks is described, and a fourth design in which terminal information similar to that of the ASIC described as a lower layer of the third design are described. The same terminal between the third design and the fourth design is connected, and the ASIC design information in which an ASIC-compatible buffer is inserted between the terminals is generated. Each of them is replaced with circuit information generated based on the connection information of the function blocks included in each design, thereby generating the FPGA and ASIC netlists. Enables efficient concurrent development of devices This has the effect of shortening the ASIC development period. Industrial applicability

 As described above, the integrated circuit development method according to the present invention, the program storage medium storing the integrated circuit development method, the concurrent development system of the ASIC and the programmable logic device, the development program and the development method are provided for the integrated circuit. Suitable for development, especially for ASIC and programmable logic devices.

Claims

The scope of the claims 1. From the ASIC core (logical core) consisting of block port and port connection information, select and group any blocks that have a connection relationship by means of grouping and connecting information of block ports and ports of any size and number. Generates an HDL format core (logical core) that can be read by logic synthesis tools (step 1).  A temporary chip design is created with a logic synthesis tool from the chip terminal information, and terminals are generated in this design (step 2).  Generate the same design as Step 2 as a cell inside the created design (Connect the port with the same name between the design and the cell (Step 4),  Insert a device technology dependent I / O buffer into the net between the connected ports (step 5)  Swap the cells with the core (logical core) created in Step 1, expand the design hierarchy, which is the top hierarchy, and generate a netlist (Step 6)  A program storage medium storing a method for developing an integrated circuit. 2. In the case of concurrent development of ASIC and programmable logic device,  ASIC cores (logical cores) consisting of block port information and port connection information, called netlisters, etc., and the means of selecting and grouping any blocks that have a connection relationship, with ports of any size and number of blocks A core (logical core) consisting of connection information of ports and ports is generated (step 1),  From the chip terminal information, create a temporary chip design using a logic synthesis tool (Step 2). A terminal is generated in this design by the name in the terminal information of the chip (step 3) ヽ  The same design as above is generated as a cell therein (step 4), and a port having the same name is connected between the design and the cell (step 5),  Insert an I / O buffer depending on the device technology from the chip pin information into this connection net (step 6),  Replace the core (logical core) generated in step 1 with the above cell (step 7). Expand the hierarchy of the created design, which is the top layer of this core (logical core), and create a netlist of programmable logic device chips. Generate (step 8) A method for developing an integrated circuit, comprising: 3. From the ASIC core (logical core) consisting of block port and port connection information, select and group any blocks with connection relationship by means of arbitrary size and number of block ports and port numbers. 2. The program storage medium according to claim 1, wherein the program storage medium generates a netlist including connection information. 4. From the ASIC core (logical core), which consists of block port and port connection information, select and group any blocks that have a connection relationship by any means. Generates a core (logical end) consisting of connection information (step 1),  From the terminal information of the chip, a design of a tentative chip is created by a logic synthesis tool, and a terminal is generated in the design with the name in the terminal information of the chip (step 2). Generating (step 3), connecting the same named port between the design and the cell (step 4), Depends on device 'technology from chip terminal information for this connection net Buy I / O buffer (step 5),  The core (logical core) generated in step 1 is replaced with the cell (step 6). The chip hierarchy is created by expanding the design hierarchy created in step 2, which is the top hierarchy of this core (logical core) ( Step 7), A program storage medium on which an integrated circuit development method is recorded. 5. When generating a netlist consisting of ports of arbitrary size and number of blocks and connection information of the ports,  Claims characterized in that the port name of the top hierarchy is modified from the net name to match the port name of the block to which the connection is made, and a net list consisting of port information of the block and port connection information is generated. The integrated circuit development method described in paragraph 2. 6. Group the function blocks that compose the ASIC based on the connection information between the ports, and generate a netlist consisting of the ports of the grouped function blocks and the connection information between the ports as the core of the logic device (logical core). Netlist generation process,  A logic synthesizing step of creating logic synthesis data for an ASIC and logic synthesis data for a programmable logic device from circuit data of the functional blocks constituting the ASIC;  Programmable logic for the grouped functional blocks is inserted into the netlist generated by the netlist generating step by inserting logic synthesis data for a logic device into a netlist generated by the netlist generating process. A ROM data generation process for generating M data, Using the ASIC logic synthesis data created in the logic synthesis process, ASIC layout creation and timing verification are performed in the ROM data generation process. A rate creation step for concurrently generating and evaluating the ROM data for machine evaluation, and a rate creation and rate change for the ASIC based on the result of the actual machine evaluation using the ROM data generated in the ROM data creation step. A difference reflection process to be reflected in the timing verification;  A concurrent development method for ASICS and programmable logic devices that includes: • 7. The layout creation step starts before or at the same time as the ROM data creation step, and the difference reflection step uses the circuit data changes made after the start of the layout creation step for ASIC layout creation and timing verification. 7. The concurrent development method of an ASIC and a programmable logic device according to claim 6, wherein the method is reflected. 8. The ROM data generation step includes, for the function blocks for which the programmable logic device logic synthesis data has not been created by the logic synthesis process in the grouped function blocks, input terminals and output terminals. The logic synthesis data for the programmable logic device into which the dummy circuit is inserted is inserted into the netlist generated in the netlist generation process to generate ROM data for evaluation of the actual device in which the circuit of the programmable logic device is recorded.  8. A concurrent development method of an ASIC and a programmable logic device according to claim 6 or 7. 9. Group the function blocks that constitute the ASIC based on the inter-port connection information, and generate a netlist consisting of the ports of the grouped function blocks and the inter-port connection information as the core of the programmable logic device. Netlist generation means, ASIC logic synthesis data is derived from the circuit data of the function blocks constituting the ASIC. Logic synthesis means for generating logic synthesis data for data and programmable logic devices;  ROM for generating logic data for evaluation of an actual device in which a programmable logic device circuit is recorded by inserting logic synthesis data for programmable logic devices for the grouped functional blocks into a netlist generated by the netlist generation means. Data generation means;  Layout creation means for concurrently performing ASIC layout creation and timing verification using the ASIC logic synthesis data created by the logic synthesis means and real-machine evaluation ROM data by the ROM data generation means. Concurrent development system for ASICs and programmable logic devices, characterized by 10. Function blocks that constitute the ASIC are grouped based on the inter-port connection information, and a netlist consisting of the ports of the grouped function blocks and the inter-port connection information is programmable. コ ア Logic device core (logical core) Netlist generation procedure to generate as  A logic synthesis procedure for creating logic synthesis data for ASIC and logic synthesis data for programmable logic device from circuit data of the function block constituting the ASIC;  The logic synthesis data for the programmable logic device for the grouped function blocks is inserted into the netlist generated by the netlist generation procedure to generate ROM data for evaluation of the actual device which records the programmable logic device circuit. OM data generation procedure and A layout creation procedure for performing ASIC layout creation and timing verification using the ASIC logic synthesis data created by the logic synthesis procedure concurrently with generation of actual machine evaluation ROM data by the ROM data generation procedure; Actual machine evaluation results using ROM data generated by the ROM data generation procedure A difference reflecting procedure for reflecting the change of the circuit data based on the result to the ASIC layout and timing verification;  A concurrent development program for ASIC and programmable magic devices that allows a computer to execute 1 1. In a concurrent development system of an ASIC and a programmable logic device used by a user from a computer connected to a network, an ASIC logic synthesis means for executing an ASIC logic synthesis in response to the user's request;  A ASIC logic synthesis result determining means for determining whether or not the ASIC logic synthesis result created by the ASIC logic synthesis means satisfies the speed performance required by the user;  Programmable 'programmer that performs logic synthesis of a logic device' based on the result of the determination by the A SIC logic synthesis result determination means, logic device logic synthesis means,  Logic synthesis result display means for displaying on the computer the execution result of the ASIC logic synthesis by the ASIC logic synthesis means and the execution result of the programmable logic device logic synthesis means by the programmable logic device logic synthesis means, and the ASIC logic. Start of execution of ASIC logic synthesis by synthesis means and execution result and programmable logic by the programmable logic device logic synthesis means Logic synthesis notification to notify the user of the execution start and execution result of logic device logic synthesis by e-mail Means,  Concurrent development system for ASICS and programmable logic devices, characterized by: 1 2. Before the function block that configures the ASIC according to the user's request Netlist generating means for generating a netlist comprising connection information between ports of a plurality of function blocks specified by the user; and data of a target function block which has been logically synthesized into the netlist generated by the netlist generating means. ROM data generating means for generating ROM data recording the circuit of the logic device, and generating the ROM data generated by the ROM data generating means to the computer. ROM data generation result displaying means for displaying, and ROM data generation result notifying means for notifying the user of the generation result of the ROM data generated by the ROM data generating means to the user by electronic mail. The concurrent development system of ASICs and programmable logic devices according to claim 11, characterized in that: 1 3. If the design of the function block that configures the ASIC specified by the user is not completed and there is no circuit data, generate a netlist with dummy circuits inserted into the input and output terminals of the function block. 13. The concurrent development system for an ASIC and a programmer logic device according to claim 12, further comprising a temporary netlist generating means. 14. A monitoring means for monitoring the magnitude of a change between the latest circuit data held by the user and the circuit data taken by the implementation designer in the implementation design, and a monitoring result by the monitoring means and a time required for the rate design. A change timing notifying means for notifying the user and the ASIC implementation designer by e-mail that the change is reflected in the implementation design of the ASIC when the date and time scheduled based on the change are reached; and 11. The anti-B-stop requesting means for requesting a stop by the user changing the reflection date in response to the timing notifying means, further comprising: anti-B-stop request means. A concurrent development system for ASICs and programmable logic devices as described in paragraph 2 or 13. 15 5. In a concurrent development method of an ASIC and a programmable logic device used by a user from a computer connected to a network, an ASIC logic synthesis process for executing a logic synthesis of the ASIC in response to the user's request;  An ASIC logic synthesis result determining step of determining whether or not the ASIC logic synthesis result created in the ASIC logic synthesis step satisfies the speed performance required by the user;  A programmable logic device that performs logic synthesis of a logic device based on the result of the determination by the A SIC logic synthesis result determination process;  A logic synthesis result display step of displaying, on the computer, the execution result of the ASIC logic synthesis in the ASIC logic synthesis step and the execution result of the programmable logic device logic synthesis in the programmable logic device logic synthesis step;  Logic synthesis that notifies the user of the start and execution results of ASIC logic synthesis by the ASIC logic synthesis process and the execution start and execution results of the logic device logic synthesis by the programmable logic device logic synthesis process to the user. Notification step,  A concurrent development method for ASIC and programmable logic devices. 16. On the other hand, a first design in which terminal information of an FPGA including all or a part of a plurality of functional blocks is described, and a terminal similar to the FPGA described as a lower layer of the first design From the second design in which the information is described, the same design terminals in the first design and the second design are connected, and FPGA design information in which a buffer corresponding to the FPGA is inserted between the terminals is generated. On the other hand, a third design in which terminal information of an ASIC including the plurality of functional blocks is described, and a fourth design in which terminal information similar to that of the ASIC described as a lower layer of the third design are described. Generating the ASIC design information in which the same terminals between the third design and the fourth design are connected and a buffer corresponding to the ASIC is inserted between the terminals;  Replacing each of the second design and the fourth design with circuit information generated based on connection information of a function block included in each design; To generate FPGA and ASIC netlists.