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WO2003067599A1 - Memoire a ports d'ecriture multiples - Google Patents

Memoire a ports d'ecriture multiples Download PDF

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Publication number
WO2003067599A1
WO2003067599A1 PCT/GB2003/000371 GB0300371W WO03067599A1 WO 2003067599 A1 WO2003067599 A1 WO 2003067599A1 GB 0300371 W GB0300371 W GB 0300371W WO 03067599 A1 WO03067599 A1 WO 03067599A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit
bits
working
memory
digital memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2003/000371
Other languages
English (en)
Inventor
Paul David Burns
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qinetiq Ltd
Original Assignee
Qinetiq Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qinetiq Ltd filed Critical Qinetiq Ltd
Priority to AU2003207002A priority Critical patent/AU2003207002A1/en
Publication of WO2003067599A1 publication Critical patent/WO2003067599A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Definitions

  • the present invention relates to electronic digital storage devices.
  • it relates to configurations of elemental logic devices that provide a ' digital storage, wherein the data stored within the store may be accessed and changed from two or more independent ports.
  • Digital storage devices are commonly employed in electronic systems for storing data.
  • This data may be for any purpose, and may comprise executable instructions, or may comprise information required or generated by the execution of instructions, as typically takes place inside a microprocessor.
  • the digital storage devices also known as memory devices, can be built up by combining elemental logic devices such as AND, OR and NOT gates to produce circuit elements capable of retaining data written to them and reproducing the stored data on demand.
  • Such storage devices typically have a plurality of locations, known as addresses, at which data may be stored, and the data at each location will comprise one or more binary digits of information.
  • the locations are chosen using an address bus, and the data at a location accessed by a data bus.
  • the most common form of this storage is accessible from a single port, so that just one location may be addressed, either by writing to it, or reading from it, at a time.
  • This memory has a single address bus and a single data bus.
  • FPGA Field Programmable Gate Arrays
  • a scoreboard register acts as an access controller for one or more logical resources.
  • Scoreboard registers are commonly used in microprocessors to indicate the state of, and control usage of, registers and execution units. Modern , microprocessors can often execute more than one instruction at a time, but there can be a problem if two instructions are simultaneously attempting to access the same register. As the number of registers in a typical microprocessor is not large, the size of the scoreboard register itself does not need to be large. However, implementation using the standard multiple write- port memories available in FPGA may mean that much of the memory is wasted, as they are typically much larger than required for this application.
  • a digital memory for storing information in bit form, characterised in that the memory includes locations for storing at least one information bit as a plurality of working bits, and combinatorial logic output circuitry for generating the information bit from the working bits.
  • the present invention allows a multiple port memory to be implemented using a relatively small amount of additional logic functions, Having the information bit stored as a combination of working bits allows the modification of the information bit by manipulation of at least one of the working bits.
  • the working bits are preferably divided into sets, where each set consists of at least one working bit for each separately addressable location. The sets of working bits are arranged such that each set may be addressed for writing through a single port but may be addressed for reading through a plurality of ports.
  • the working bits from the particular address being read are combined together through a combinatorial logic function which takes all information bits into consideration from the address in question, and provides as an output a single bit, this being the required information bit.
  • the combinatorial logic used to manipulate the working bits during a read operation or during a write operation comprises a one bit addition of the logic's inputs.
  • this may be achieved using an Exclusive OR gate (XOR)
  • the current invention is particularly suitable for implementation as a two port 5 system, providing a simultaneous read and write facility from two independent ports.
  • the invention is also suitable for systems requiring more than two read or write ports. Additional ports may be added by providing storage for additional sets of working bits. The working bit storage for any additional ports must be connected to the working bit storage of the existing ports by 0 means of combinatorial logic as discussed above. Additional ports may be read-only, or may be full read-write ports
  • a scoreboard register having a plurality of flag bits, each of at least two of said flag bits 15 being allocable to a logical resource so as to indicate the state of the logical resource, wherein each flag bit has associated with it a plurality of working bits, each of which may be addressed from a different port, and an output
  • the present invention allows a scoreboard register to be produced in an efficient manner, particularly when implemented using logic functions available on typical programmable logic devices.
  • the present invention is particularly suitable for implementation on an FPGA.
  • Implementation of the current invention on an FPGA or other programmable logic device may be performed by creating a circuit description in electronic form and then transferring this electronic description to the device. The transfer will involve reformatting the electronic description into a suitable format for download to the device.
  • a method of storing digital information in a memory having at least two write ports comprising the steps of: receiving an information bit from a data bus associated with a first write port; adding this information bit to a set of corresponding working bits taken from memories associated with all other ports, the addition being one bit addition; storing the result of the addition in a memory associated with the first write port;
  • Figure 1 illustrates in block diagrammatic form, how a single information bit may be stored as two separate working bits
  • Figure 2 illustrates in block diagrammatic form a practical implementation of the current invention using a Xilinx ® FPGA, showing two read-write ports;
  • Figure 3 illustrates in block diagrammatic form a practical implementation of the current invention using a Xilinx ® FPGA, showing two read-write ports with a third read port
  • Figure 4 illustrates in block diagrammatic form a practical implementation of the current invention using a Xilinx ® FPGA showing three read-write ports.
  • Figure 5 illustrates in block diagrammatic form a practical implementation of the current invention using a Xilinx ® FPGA showing a system acting as a scoreboarding register.
  • Figure 1 shows a logic function having two inputs, A and B, and a single output, Q.
  • two D-type flip-flops 101, 102 each independently capable of storing one bit of information have their outputs coupled together through an Exclusive OR gate 103.
  • the flip-flops 101 , 102 are each configured such that by pulsing an input A, B, the output Q A QB toggles its state.
  • the logic function is designed to store one information bit as a combination of two working bits.
  • the flip-flop QA QB outputs here are the working bits of this system, whereas the Q output is the information bit stored as the function of the two working bits. Note that altering either of the working bits in the flip- flops 101 , 102 will change the Q output. Therefore, before storing a bit in one of the flip-flops, 101 or 102, the state of the other needs to be taken into account, so that the correct value is presented to the output Q. This is done using further logic not shown in this Figure
  • Figure 2 shows a practical implementation of a memory with two independent read and write ports. It is based on the principle demonstrated using Figure 1 , but is shown using higher level functions which are available as primitives in the Xilinx ® "Virtex 2" FPGA device.
  • two memories 1 , 2 known as Look Up Table (LUT) Random Access Memories (RAM) act as the storage elements for the working bits.
  • LUT RAMs 1 , 2 has a single interface, e.g. 3, for writing information to it, but has two interfaces e.g. 3, 4, for reading information from it. It is thus not useful on its own if it is required to have dual write access. However, combining two such devices together in the manner shown allows a true dual port memory to be produced.
  • each LUT RAM " 1 , 2 ⁇ acts effectively as a store for one set of working bits. As each has two read interfaces, it is able to provide as an output simultaneously two different working bits from the same set, one for each port.
  • Each port is arranged such that its address bus, e.g. 7 goes to both LUT RAMs 1 , 2 - on one to the read-write interface, e.g. 3 and on the other to the read only interface, e.g. 6.
  • the extra read port thus provides a mechanism for allowing one set of working bits to be taken into account when writing to another set, ensuring that the correct information bit is stored or retrieved.
  • the working bit stored in the set is therefore the XOR of the information bit and the corresponding working bit of the other set.
  • writing to a LUT RAM as provided on a Xilinx ® Virtex or Virtex2 device is a synchronous operation requiring a clock input, but reading data from it is an asynchronous process not requiring a clock pulse.
  • XOR gate16 provides the input combinatorial logic for the port, and the store for the working bits of Port B are in LUT RAM 2.
  • Reading from address n using, say port B, works as follows. Address n is set up on Addr B 12. This takes a working bit from address n of LUT RAM 1 read-only interface 4, along with a working bit from address n of LUT RAM 2 read-write interface 5. The first of these working bits will be logic 1 due to the write operation described above, and the second will be logic 0 as there has been nothing written to this memory device yet.
  • the two LUT RAM outputs 13, 14 addressed by port B are fed to an XOR gate 15, the output of which is the port B data output. In this case, the output will be a logic 1 , reflecting the logic 1 that was stored at the address using port A as described earlier.
  • XOR gate 17 provides the output combinatorial logic for port A?, and the store for the working bits of Port A are in LUT RAM 1.
  • the dotted region 35 of Figure 2 indicates the logic that is not in the same slice as the other logic devices when implemented using Xilinx ® Virtex or Virtex2 FPGA devices.
  • Each slice in such a device comprises a set of logic primitives that may be configured, according to the architecture of the device, into commonly used functions particularly conveniently. Logic functions may however be used from other slices if desired.
  • Figure 3 shows another embodiment of the current invention, where the implementation has been scaled to provide a third read-only port. Reading and writing to ports A and B are carried out in an identical manner to that described above, but placing a valid address onto port C will result in the data stored at that address appearing at Dout C.
  • the additional logic required over the two port implementation of Figure 2 comprises extra storage LUT RAMs 18, 19 and extra output combinatorial logic 20. The extra storage is necessary to provide additional read ports for two sets of working bits, and this storage provides its read-only outputs to the XOR gate 20.
  • Each LUT RAM 18 and 19 hold data identical to that of their corresponding LUT RAMS 1 and 2 respectively.
  • Figure 4 shows a further embodiment of the current invention, where the implementation shown in Figure 2 has been scaled to provide three read-write ports 104, 105, 106.
  • the three ports 104, 105, 106 require three sets of working bits, and these are provided by the three LUT RAM pairs 21 , 22, 23. Pairs are needed here so that there are a sufficient quantity of independent read ports available to provide, to all ports, copies of the working bits from the corresponding sets of working bits from the other ports. This enables the working bits from all sets to be taken into account when writing new data or reading data using any one of the ports.
  • Additional embodiments may be produced having additional read-only or read- write ports.
  • additional ports may be added by scaling up the basic architecture of the present invention.
  • Each additional write port will need storage for an associated set of working bits and logic to ensure information bits written to the port take due account of the corresponding working bits of all other ports.
  • Figure 5 shows yet another embodiment of the current invention, this being a two port scoreboarding circuit.
  • the circuit is based upon that of the dual read- write port memory shown in Figure 2, with some small but important differences. Firstly, data in lines for ports A and B are not present. This type of circuit is not required to store random data coming in from the ports. It merely has to toggle flag bits according to requests from the ports to do so. Each flag bit in the scoreboard is used to indicate the status of a register, or other logic resource in a system. If the flag bit is active (eg at a logic 1), then the resource is unavailable, whereas if the flag bit is inactive (eg logic 0), then the resource is free to be used.
  • the flag bit is active (eg at a logic 1), then the resource is unavailable, whereas if the flag bit is inactive (eg logic 0), then the resource is free to be used.
  • Each flag bit is stored as (in this case) two working bits, and the flag bit is reproduced by applying the working bits to a combinatorial logic function. The output of this is the desired flag bit.
  • the combinatorial logic comprises a 1 bit addition of the working bits.
  • a scoreboard circuit as described can be implemented efficiently in a Xilinx® Virtex or Virtex2 FPGA, where it can be made using logic functions from two slices.
  • Use of a programmable logic device is particularly convenient for implementing the current invention as the logic primitives supplied in the device are generally arranged to be adaptable to several tasks, so increasing their utility.
  • Programmable logic devices provided by other manufacturers may have different arrangements of logic elements, and the skilled person will understand that the principle of operation shown in the invention and embodiments as described above may be applicable to these other devices. Exact implementation details may not be the same however.
  • Implementing the current invention in a programmable logic device is typically done by first providing a electronic description using a graphical or text based software.
  • Various suppliers provide software suitable for this, including Mentor GraphicsTM, Viewlogic SystemsTM, SynplicityTM and SynopsysTM.
  • Such programs are able to describe the circuit at various levels of abstraction. Some describe the circuit operation in terms of constructs similar to that used typically in many programming languages. These descriptions are then fed into a synthesis tool that generates the actual circuit design netlist from the description. Other methods involve the user entering the circuit design directly as a hardware description, where no synthesis is needed. The user can, with these methods, impose limitations on the way the circuit is laid out on the device.
  • the netlists produced by these methods may then be processed by tools specific to the target device to produce a configuration file, the production of which involves checks to ensure that the electronic description of the circuit is compatible with the capabilities of the particular programmable logic device.
  • the configuration file also contains placement and routing information, either completely synthesised from the netlist information or taken from limitations imposed by the user. The configuration file is then downloaded to the device to produce a working circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

L'invention concerne une mémoire numérique de stockage d'informations sous forme de bits, comprenant une pluralité de bits de service adressables séparément, et dans laquelle est stocké un bit d'information en tant que fonction logique combinatoire des bits de service. Chaque bit associé au bit d'information peut être adressable à partir d'une pluralité de bus d'adresse. L'invention concerne une mémoire à ports d'écriture multiples pouvant être utilisée de manière classique, ou pouvant être adaptée de manière avantageuse pour mettre en application un compteur de tableau d'affichage, qui peut être utilisé pour indiquer l'état d'une ressource logique. L'invention est adaptée, en particulier, pour mettre en application les fonctions mémoire et tableau d'affichage d'un dispositif logique programmable comme, par exemple, un réseau de circuits prédiffusés programmables par l'utilisateur. L'invention concerne également un procédé de mise en application d'une mémoire numérique.
PCT/GB2003/000371 2002-02-09 2003-01-29 Memoire a ports d'ecriture multiples Ceased WO2003067599A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003207002A AU2003207002A1 (en) 2002-02-09 2003-01-29 Multiple write-port memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0203070A GB0203070D0 (en) 2002-02-09 2002-02-09 Multiple write-port memory
GB0203070.8 2002-02-09

Publications (1)

Publication Number Publication Date
WO2003067599A1 true WO2003067599A1 (fr) 2003-08-14

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PCT/GB2003/000371 Ceased WO2003067599A1 (fr) 2002-02-09 2003-01-29 Memoire a ports d'ecriture multiples

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AU (1) AU2003207002A1 (fr)
GB (1) GB0203070D0 (fr)
WO (1) WO2003067599A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313260A (ja) * 1987-06-16 1988-12-21 Fuji Electric Co Ltd デュアルポ−トメモリ調停回路
EP0375194A2 (fr) * 1988-12-19 1990-06-27 Advanced Micro Devices, Inc. RAM à double accès
US5398211A (en) * 1993-10-14 1995-03-14 Integrated Device Technology, Inc. Structure and method for providing prioritized arbitration in a dual port memory
EP1081714A1 (fr) * 1999-08-31 2001-03-07 Fujitsu Limited DRAM de stockage de données dans des paires de cellules

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313260A (ja) * 1987-06-16 1988-12-21 Fuji Electric Co Ltd デュアルポ−トメモリ調停回路
EP0375194A2 (fr) * 1988-12-19 1990-06-27 Advanced Micro Devices, Inc. RAM à double accès
US5398211A (en) * 1993-10-14 1995-03-14 Integrated Device Technology, Inc. Structure and method for providing prioritized arbitration in a dual port memory
EP1081714A1 (fr) * 1999-08-31 2001-03-07 Fujitsu Limited DRAM de stockage de données dans des paires de cellules

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 152 (P - 856) 13 April 1989 (1989-04-13) *

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Publication number Publication date
AU2003207002A1 (en) 2003-09-02
GB0203070D0 (en) 2002-03-27

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