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WO2003065147A3 - Method and program product for creating and maintaining self-contained design environment - Google Patents

Method and program product for creating and maintaining self-contained design environment Download PDF

Info

Publication number
WO2003065147A3
WO2003065147A3 PCT/US2003/001831 US0301831W WO03065147A3 WO 2003065147 A3 WO2003065147 A3 WO 2003065147A3 US 0301831 W US0301831 W US 0301831W WO 03065147 A3 WO03065147 A3 WO 03065147A3
Authority
WO
WIPO (PCT)
Prior art keywords
design
utility
creating
program product
embedded test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/001831
Other languages
French (fr)
Other versions
WO2003065147A2 (en
Inventor
Brian John Pajak
Paul Price
Jean-Francois Cote
Luc Romain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LogicVision Inc
Original Assignee
LogicVision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LogicVision Inc filed Critical LogicVision Inc
Priority to AU2003205269A priority Critical patent/AU2003205269A1/en
Publication of WO2003065147A2 publication Critical patent/WO2003065147A2/en
Publication of WO2003065147A3 publication Critical patent/WO2003065147A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow (70). Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment (212), generates control files (214) for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.
PCT/US2003/001831 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment Ceased WO2003065147A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003205269A AU2003205269A1 (en) 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35097902P 2002-01-25 2002-01-25
US60/350,979 2002-01-25

Publications (2)

Publication Number Publication Date
WO2003065147A2 WO2003065147A2 (en) 2003-08-07
WO2003065147A3 true WO2003065147A3 (en) 2004-01-22

Family

ID=27662987

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/001831 Ceased WO2003065147A2 (en) 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment

Country Status (2)

Country Link
AU (1) AU2003205269A1 (en)
WO (1) WO2003065147A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361122C (en) * 2004-11-29 2008-01-09 华为技术有限公司 An automatic design method for switching PCBs for ICT testing
KR102004852B1 (en) * 2012-11-15 2019-07-29 삼성전자 주식회사 System for designing semiconductor package using computing system and method for the same, device for fabricating semiconductor package comprising the system, semiconductor package designed by the method
CN107729692B (en) * 2017-11-13 2021-07-20 嘉兴倚韦电子科技有限公司 Automatic physical verification method for semi-custom back-end design of integrated circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923675A (en) * 1997-02-20 1999-07-13 Teradyne, Inc. Semiconductor tester for testing devices with embedded memory
US6063132A (en) * 1998-06-26 2000-05-16 International Business Machines Corporation Method for verifying design rule checking software
US6182020B1 (en) * 1992-10-29 2001-01-30 Altera Corporation Design verification method for programmable logic design
US20020138813A1 (en) * 2001-03-20 2002-09-26 Cheehoe Teh System & method for performing design rule check
US6516456B1 (en) * 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182020B1 (en) * 1992-10-29 2001-01-30 Altera Corporation Design verification method for programmable logic design
US6516456B1 (en) * 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool
US5923675A (en) * 1997-02-20 1999-07-13 Teradyne, Inc. Semiconductor tester for testing devices with embedded memory
US6063132A (en) * 1998-06-26 2000-05-16 International Business Machines Corporation Method for verifying design rule checking software
US20020138813A1 (en) * 2001-03-20 2002-09-26 Cheehoe Teh System & method for performing design rule check

Also Published As

Publication number Publication date
AU2003205269A1 (en) 2003-09-02
WO2003065147A2 (en) 2003-08-07

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