WO2003063466A1 - Circuit arrangement and method for generating a control signal of the deflection transistor of a cathode ray tube - Google Patents

Abstract

The invention relates to a circuit arrangement for generating a control signal (HDRV) for the deflection transistor, which drives the resonant circuit of the horizontal deflection of a cathode ray tube (CRT). The inventive circuit arrangement generates a second horizontal reference signal (HREF2), which in temporal terms lies between the horizontal flyback signal (HFB) and the square wave signal of the control signal (HDRV) for the deflection transistor, for all potential horizontal positions (hpos) and horizontal modulations (hmod). A delay block (DB1) is connected between the output of the first phase-locked loop (PLL1) and the input of the second phase-locked loop (PLL2). According to the invention, the phase measurement of the horizontal flyback (HFB) in relation to the second horizontal reference signal (HREF2) is always carried out in a time window equal to 10 % of a period and to position the second horizontal reference signal (HREF2), the conventional circuit arrangement is enhanced by the addition of the first delay block (DB1).

Description

Circuit arrangement and method for generating the control signal of the deflection transistor of a cathode ray tube

The invention relates to a circuit arrangement for generating the control signal (HDRV = horizontal drive) for the deflection transistor, which drives the resonant circuit of the horizontal deflection of a cathode ray tube (CRT = cathode ray tube). The horizontal synchronization signal (HSYNC = horizontal synchronization) and the horizontal return (HFB = horizontal flyback) are used as input signals for the circuit arrangement. The horizontal return is proportional to the resonant circuit voltage. Circuit arrangements of this type can be implemented in analog or digital form.

The invention relates in particular to a circuit arrangement which uses two phase locked loops (PLL = phase-lock-loop). The first of these phase-locked loops generates an internal, low-interference reference. The second of these phase locked loops regulates the phase position of the loop "internal reference drive signal (HDRV) - deflection transistor - resonant circuit and horizontal return (HFB)". In contrast to the first control loop, this second control loop follows dynamic, horizontal modulation, which is visible, for example, through the parallelogram setting on the monitor. The second control circuit has a much smaller time constant Tι ₀₀ p ₂ - Non of the circuit arrangement described for the generation of the control signal of a deflection transistor and other realizations, it is known that ideally firstly the horizontal position (hpos = horizontal position) and secondly the horizontal one Modulation (hmod = horizontal modulation) should each have an adjustment range of up to ± 15%. Another third requirement is that the horizontal utilization time of the deflection transistor should be up to 60% and its storage time up to 30%. For example, at 140 kHz deflection frequency, about 2 msec of storage time corresponds to 30% of the period. Not all three requirements can be met in the known systems. The overall context of the system means that an improvement in the value of one requirement leads to a deterioration in one of the other values. The conventional circuit arrangement for the generation of the control signal for the deflection transistor has proven itself, but the large, required setting ranges for the horizontal position and the horizontal modulation in deflection transistors, which have a large utilization time and storage time, cannot be achieved without the feedback of the second phase locked loop to increase a period. This delay in the response time would lead to a deterioration in the control behavior of the second phase locked loop and is generally not acceptable.

It is therefore an object of the invention to provide a circuit arrangement which achieves the required large setting ranges for the horizontal position and for the horizontal modulation even for a deflection transistor with a large utilization time and a large storage time without increasing the delay in the feedback of the second control loop. This object is achieved in that between the

Output of the first phase locked loop and the input of the second phase locked loop is connected to a first delay block. The input signal of the delay block is the horizontal reference, the output signal is a delayed, second horizontal reference, which in turn is an input signal of the second phase locked loop. The constant part of the first phase locked loop and the constant part of the first

The delay block together is more than 100%. The circuit arrangement according to the invention results in a change in the phase measurement of the second phase locked loop: the phase of the horizontal flyback is now measured against the delayed, second horizontal reference instead of, as in the conventional circuit arrangement, against the simple horizontal reference.

The principle and advantage of the invention is that the delayed, second horizontal reference for all horizontal positions (hpos) and horizontal modulations (hmod) together, ie for the range of hpos + hmod from -30% to + 30%, between the occurrence of the Horizontal return (HFB) and the start of the control signal (HDRV) for the deflection transistor. This means that the phase measurement can flow immediately into the generation of the next control signal (HDRV) after the horizontal ramp-down and thus a minimal delay of the control loop (minimal loop latency) is achieved. It is therefore possible to always measure the phase in the window that remains with a required storage time of 60% and a load time of 30% of 10%. The phase measurement therefore does not limit the setting range of the horizontal modulation (hmod).

Another advantage of the circuit arrangement according to the invention is that the phase position of the signals is always such that the phase detectors in the two phase-locked loops first measure the time of occurrence of the horizontal synchronization signal (HSYNC) and the horizontal return (HFB), then the time of the occurrence Measure the first horizontal reference and the second horizontal reference and then make the difference. This simplifies the phase detectors in particular in digital implementations.

In the following the invention with reference to Figs. explained in more detail, whereby:

1 in the partial figures a) and b) shows a block diagram 1 of the circuit arrangement according to the invention with different control values, FIG. 2 shows the signal curve of the horizontal synchronization signal above the

Represents time

3 shows the signal curve of the horizontal reference over time, FIG. 4 shows the signal curve of the second horizontal reference over time,

5 shows the signal curve of the control signal over time and FIG. 6 shows the signal curve of the horizontal return over time. The waveforms in Fig. 2 to Fig. 6 represent the steady state.

The block diagram 1 shown in FIG. 1 a of a two-PLL system consists of a first phase-locked loop PLL1, a first delay block DB1, a second phase-locked loop PLL2, a second delay block DB2 and an RS flip-flop FF. An output of the first phase locked loop PLL1 is connected to an input of the first delay block DBl. An output of the first delay block DB1 is connected to an input 2 of the second phase locked loop PLL2. An output of the second phase locked loop PLL2 is branched and given to an input S of an RS flip-flop FF and to an input of a second delay block DB2. An output of the second delay block DB2 is with an input R of the RS flip-flop FF connected. The two-PLL system described below is used in particular for the horizontal deflection of a cathode ray tube. Interface signals to the rest of the system are the horizontal synchronization HSYNC, the drive signal HDRV for the deflection transistor and the horizontal return HFB. The drive signal HDRV, which is generated by the circuit arrangement according to the invention, switches the deflection transistor on and off. The horizontal return HFB represents the position of the electronic beam on the screen. Control values for the system shown are:

- For the first phase locked loop PLL1: the target position ZP1 is the horizontal position hpos plus a constant one

Part constant, which is generated in the first phase-locked loop and is 30% in this exemplary embodiment, and the quasi-static horizontal position, which is predetermined by the overall system and is hpos = ± 15%, so that ZP1 = 15% to 45% for the delay block DB1: as the target phase ZP2, the dynamic horizontal modulation hmod plus a constant component const2, which is generated in the first delay block and is 80% in this exemplary embodiment, and the horizontal modulation hmod, which is predetermined by the overall system hmod = ± 15% is such that ZP2 = 65% to 95%,

for the second phase-locked loop PLL2: as the target phase ZP3, a constant component const3, which is generated in the second phase-locked loop and is 10% in this exemplary embodiment, so that ZP3 = 10%, for the second delay block DB2: as the target phase ZP4 the quasi-static horizontal utilization time hduty, which is specified by the overall system, so that ZP4 = hduty = 40% to 60%.

The block diagram 1 shown in Fig. Lb) consists of the same elements as that shown in Fig. La). The difference is in the control values for the delay block DB1 and the second phase locked loop PLL2. Control values for these two are in this exemplary embodiment:

- for delay block DB 1: as the target phase ZP2, the first dynamic horizontal modulation hmodl plus a constant component const2, which is generated in the first delay block and is 80% in this exemplary embodiment), and the first horizontal modulation hmodl, which is predetermined by the overall system, hmodl = ± 14%, so that ZP2 = 66% to 94%, - for the second phase locked loop PLL2: as the target phase ZP3 the second horizontal modulation hmod2 plus a constant component const3, which is generated in the second phase locked loop and is 0% in this exemplary embodiment, and the second horizontal modulation, which is given by the overall system and hmod2 = ± 1%, so that ZP3 = 9% to 11%.

In this embodiment according to FIG. 1b), the horizontal modulation hmod is set in two parts hmodl and hmod2, where hmod = hmodl + hmod2. It is preferred that the major part hmodl of e.g. +/- 14% in the first delay block DB1 and the smaller part hmod2 of e.g. +/- 1% is realized in the second phase locked loop PLL2. The division of the horizontal modulation results in values that are particularly suitable for a digital implementation. Fig. 2 shows the waveform of the horizontal synchronization signal

HSYNC. With the rising edge of a square-wave signal, a period that begins and ends here is specified as 100%. The pulse duration is usually less than 25% and the rising edge or the center of the horizontal synchronization signal HSYNC is usually used as the reference time. Fig. 3 shows the waveform of the internal, low-interference, horizontal

Reference HREF (= horizontal reference). The influence of the target phase ZP1 from 15% to 45% on the output signal HREF of the first phase locked loop PLL1 is shown with a dotted line. The rectangle pulse shown with a solid line illustrates the influence of the constant component const = 30%> for the case hpos = 0%. The square-wave pulses at about 15% and about 45% make it clear that the limits of the setting range of the horizontal position hpos, which should meet the requirements of ± 15% o, are reached, namely that they are shifted by 30% so that they are only positive.

4 shows the signal curve of the delayed second horizontal reference HREF2. In the example shown, the proportion, measured from the input signal, is HREF of the delay block DB1 on, const2 = 80%. This means that in the case of hpos = 0%> and hmod = 0% over a period of 100%, the rising edge of the square wave signal of the second horizontal reference HREF2 appears 10% of a period after the rising edge of the horizontal synchronization signal. This follows from equation 1:

30% {HREF) + 80% {HREF2) - 100% {HSYNC) = 10% {HFB) (1)

The maximum influence of the command variable hpos = ± 15%> is illustrated by the rectangular pulses shown in dashed lines on the right and left of the rectangular pulse shown in solid lines for hpos = 0%. The maximum influence of the reference variable hmod = ± 15% is shown by the rectangular pulses shown in dashed lines on the right and left outside. The requirements for hmod can therefore be met in addition to the requirements for hpos, both requirements are ± 15%.

5 shows the signal curve of the generated drive signal HDRV for the deflection transistor. The maximum pulse duration of 60% is shown with a solid line. The segments drawn with a dotted line represent the control signal

HDRV with a maximum pulse duration of 60% for the cases (hpos + h od) = -30%>, -15%, + 15% and + 30%.

Fig. 6 shows the waveform of the horizontal return HFB. In the example shown with a solid line, the horizontal return is in phase with the horizontal synchronization signal. The horizontal return HFB appears with a delay by the storage time after switching off the deflection transistor (falling edge of the HDRV). Accordingly, the phase position of the horizontal return HFB varies according to that of the control signal HDRV.

In a preferred embodiment of the invention, the target phase ZP3 of the second phase locked loop PLL2 is constant, e.g. 10%, and the horizontal modulation hmod is realized only in the target phase ZP2 of the delay block DB1.

In a variant for operating the circuit arrangement according to the invention, the target phase ZP2 for the first delay block DB1 lies in a range which consists of the first part hmodl and a constant component const2, so that ZP2 = hmodl + 80%. ± 14% is preferably selected for hmodl, which results in a range of 66% to 94% for the target phase ZP 2. In addition, in this variant, the target phase ZP3 for the second phase locked loop PLL2 lies in a range which is formed by the second part and a constant component const3, so that ZP3 = hmod2 + 10%. For hmod 2 it is preferred to choose ± 1%, which results in ZP3 for the target phase Range from 9% to 11. This variant is particularly suitable for digital implementation.

The circuit arrangement according to the invention generates a second horizontal reference signal HREF2, which is temporally between the square wave signal of the horizontal return and the square wave signal of the control signal for the deflection transistor, for all horizontal positions hpos and horizontal modulations hmod together, this means for the range of hpos + hmod = -30% to hpos + hmod = + 30%. For long storage _times , for example T _MEMORY = 30%, of the deflection transistor and for long utilization times, for example hduty = 60%, there remains a time of 10% for the phase measurement and feedback of the second phase locked loop PLL2.

In summary, for the circuit arrangement according to the invention with a delay block DB1 for the positioning of the second horizontal reference signal HREF2 between the horizontal return HFB and the generated drive signal HDRV, a larger range for the horizontal modulation, more utilization time and / or more storage time are acceptable compared to the prior art, without extending the delay of the feedback of the phase locked loops to over a period.

Claims

CLAIMS: 1. Circuit arrangement for generating the control signal of the deflection transistor of a cathode ray tube, which consists of a two-PLL system, characterized in that a delay block (DBl) is connected between the first and the second phase-locked loop (PLL1, PLL2). 2. Circuit arrangement according to claim 1, characterized in that the output (HREF) of the first phase locked loop (PLLl) is connected to the input of the delay block (DBl). 3. Circuit arrangement according to one of claims 1 or 2, characterized in that the output of the first delay block (DBl) is connected to an input of the second phase locked loop (PLL2). 4. A method for operating a circuit arrangement, in particular a circuit arrangement according to claims 1 to 3, characterized in that the horizontal modulation (hmod) is a control value for the delay block (DBl). 5. The method according to claim 4, characterized in that the constant portion (constl) of the target phase (ZP1) of the first control loop (PLLl) and the constant portion (konst2) of the first delay block (DBl) are together greater than 100%. 6. The method according to claim 4 or 5, characterized in that the constant portion (constant) of the first phase locked loop PLLl is 30%. 7. The method according to any one of claims 4 to 6, characterized in that the constant portion (const2) of the first delay block (DBl) is 80%>. 8. Method for operating a circuit arrangement, in particular one Circuit arrangement according to one of claims 1 to 3, characterized in that the target phase (ZP3) of the second phase locked loop (PLL2) is constant. 9. The method according to claim 8, characterized in that the target phase (ZP3) of the second phase locked loop (PLL2) is 10% o. 10. A method for operating a circuit arrangement, in particular a circuit arrangement according to one of claims 1 to 3, characterized in that the dynamic portion of the target phase (ZP3) of the second phase control loop (PLL2) is less than 20%> of the total horizontal modulation (hmod). 11. A method for operating a circuit arrangement, in particular a circuit arrangement according to one of claims 1 to 3, characterized in that the dynamic portion of the target phase (ZP3) of the second phase locked loop (PLL2) is approximately 7% of the total horizontal modulation (hmod). 12. A method for operating a circuit arrangement, in particular a circuit arrangement according to one of claims 1 to 3, characterized in that the setting of the horizontal modulation (hmod) takes place in two parts (hmodl and hmod2), the first part (hmodl) in the first Delay block (DBl) and the second part (hmod2) in the second phase locked loop (PLL2) can be realized. 13. The method according to claim 12, characterized in that the first part (hmodl) realizes the greater part of the setting of the horizontal modulation (hmod) and the second part (hmod2) the smaller. 14. The method according to claim 13, characterized in that the first part (hmodl) is 14% and the second part (hmod2) is 1%>. 15. The method according to any one of claims 4 to 14, characterized in that the horizontal modulation (hmod) is 15%. 16. The method according to any one of claims 12 to 15, characterized in that the target phase (ZP2) for the first delay block (DBl) in a range from 66% to 94% and the target phase (ZP3) for the second phase locked loop (PLL2) in ranges from 9% to 11%. 17. The method according to any one of claims 4 to 16, characterized in that the circuit arrangement is implemented digitally.