WO2002014915A2

WO2002014915A2 - Silicon-on-insulator optical waveguide fabrication by local oxidation of silicon

Info

Publication number: WO2002014915A2
Application number: PCT/CA2001/001159
Authority: WO
Inventors: Paul E. Jessop; Mathew R. T. Pearson
Original assignee: McMaster University
Current assignee: McMaster University
Priority date: 2000-08-17
Filing date: 2001-08-16
Publication date: 2002-02-21
Anticipated expiration: 2003-02-17
Also published as: WO2002014915A3; AU2001281623A1

Abstract

A method of fabricating an optical waveguide (40) using a silicon-on-insulator wafer (40) having a first layer of silicon dioxide (46) positioned between a silicon substrate (44) and a second layer of silicon (42). The method includes the steps of depositing a masking layer on at least a portion of the second layer of silicon, oxidizing unmasked portions of the second layer, and removing the oxidized unmasked portions of the second layer to define a channel waveguide in which optical radiation can propagate.

Description

SILICON-ON-INSULATOR OPTICAL WAVEGUIDE FABRICATION BY LOCAL

OXIDATION OF SILICON

FIELD OF THE INVENTION

The present invention relates to optoelectronics, more particularly it relates to the fabrication of optical waveguides by local oxidation of silicon (LOCOS).

BACKGROUND OF THE INVENTION

One of the biggest challenges faced by the telecommunications industry, particularly, service providers is the ever-increasing need for more bandwidth. Most networks were built using estimates that calculated bandwidth use by employing concentration ratios derived from classical engineering formulas such as Poisson and Reeling. Consequently, forecasts of the amount of bandwidth capacity needed for networks were calculated on the presumption that a given individual would only use network bandwidth six minutes of each hour. However, these formulas did not factor in the amount of traffic generated by Internet traffic, faxes, multiple phone lines, modems, teleconferencing, and data and video transmission. Had these factors been included, a much greater estimate would have emerged.

In addition to this explosion in consumer demand for bandwidth, many service providers are coping with fiber exhaust in their networks, and many carriers are nearing one hundred-percent capacity utilization across significant portions of their networks. Another problem for carriers is the challenge of deploying and integrating diverse technologies in one physical infrastructure. Dense wave division multiplexing (DWDM) provides a solution to service providers. In recent years the demand for DWDM components has escalated to unprecedented heights. Generally, DWDM refers to the technique of transmitting several discrete communication channels over a single optical fiber, where each channel is represented by a slightly different wavelength. At the receiver end these multiple channels must be separated (using a demultiplexer) and detected individually. The optical outputs from a DWDM demultiplexer are typically coupled to separate receiver modules where they are converted to electrical signals. By monolithically integrating detectors onto the same chip as the demultiplexer, the component cost is significantly reduced, optical losses are minimized, and system complexity is also minimized. Traditionally, the telecommunications industry has relied on two distinctly different semiconductor technologies. Optical components that are used in fiber optic systems are fabricated using III-V semiconductors, such as GaAs, AlGaAs, InGaAs and InP, while advanced VLSI circuitry, for switching and the processing of electrical signals, is fabricated using silicon. One of the challenges faced has been the integrating optical components and electrical circuitry on a single chip, that is, an optoelectronic circuit. The potential cost reductions associated with integration make this a very attractive concept, but neither silicon nor III-V substrates can be the optimal choice for both electronics and optics. One approach to solving this problem is described in U.S. Patent 5,917,981 (incorporated herein by reference), to Kovacic et al., which teaches the use of silicon-based systems for optoelectronics, such as silicon germanium (SiGe). More specifically, U.S. Patent 5,917,981 describes a channel waveguide structure which can be incorporated into VLSI integrated circuits using a SiGe alloy core and silicon for top and bottom cladding layers. Instead of a single layer the core may comprise a predetermined series of layers of different materials. The series, for example, may form a superlattice or a multiple quantum well. The channel in the waveguide structure is realized by forming spaced LOCOS (locally oxidized silicon) regions in the top cladding layer to define lateral boundaries of the channel. However, in order to employ the LOCOS process a masking layer of silicon nitride and silicon dioxide is required due to the different thermal expansion properties between the silicon a SiGe alloy. Another drawback of this method is that, due to the lattice mismatch between silicon and germanium, the SiGe alloy core suffers from dislocations, and there is strain in the epitaxial layer, which leads to birefrigence, making the waveguide unsuitable.

It is an object of this invention to mitigate at least one of these disadvantages.

SUMMARY OF THE INVENTION

In one of its aspects, the present invention provides a method of fabricating an optical waveguide using a silicon-on-insulator wafer having a first layer of silicon dioxide positioned between a silicon substrate and a second layer of silicon. The method includes the steps of depositing a masking layer on at least a portion of the second layer of silicon, oxidizing unmasked portions of the second layer, and optionally removing the oxidized unmasked portions of the second layer to define a channel waveguide in which optical radiation can propagate. The channel waveguide is formed of the second layer of silicon during a local oxidation of silicon process in which the unmasked portions of the second layer are oxidized to grow silicon dioxide to result in a channel waveguide. The dimensions of the channel waveguide are dictated by the characteristics of the silicon-on-insulator wafer, and also the dimension of the mask layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the preferred embodiments of the invention will become more apparent in the following detailed description in which reference is made to the appended drawings wherein:

Figure 1 shows a planar optical waveguide of the prior art;

Figure 2 shows a cross-sectional view through a prior art semiconductor optical channel waveguide comprising part of an integrated optoelectronic integrated circuit; Figure 3 shows a local oxidation of silicon (LOCOS) process as applied to a SiGe-based system;

Figure 4 shows an optical waveguide using a silicon-on-insulator wafer, in a preferred embodiment;

Figure 5 shows a layout of an arrayed waveguide grating demultiplexer; Figure 6 shows the effective index difference between the TE and TM modes in an SOI ridge waveguide, for an etch depth of 0.75 μm; and

Figure 7 illustrates the bending losses calculated for 1.5 μm and 4 μm SOI;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A conventional prior art planar optical waveguide 10 is shown in Figure 1. The optical waveguide 10 includes a planar waveguide core 12 having an index of refraction value equal to n₂, disposed between a first layer of top cladding 14 and bottom cladding 16. Preferably, the bottom cladding 16 and the first layer of top cladding 14 both have an index of refraction equal to ni. The materials for the cladding 14 and 16 are chosen such that the index of refraction n₂ is greater than the index of refraction m. Examples of materials typically used in the core/cladding are III-V semiconductor compunds, such as, AlGaAs/GaAs or InGaAsP/InP. Alternately, a layer of silicon dioxide 16 may also be deposited upon the top cladding layer and, in fact, may form part of the top cladding layer. However, waveguides made of these materials are not suitable for conventional VLSI integration, as no lateral confinement of light is possible.

In order to address this drawback, a prior art channel waveguide 20 is provided in Fig. 2, which offers lateral confinement and allows the guiding of light from one specific point in a circuit to another point. In such a waveguide device 20, III-V semiconductor components have been replaced with silicon-based devices. Silicon-based devices can typically be fabricated for about 10% of the cost of comparable III-V components, and can also benefit from the fact that optical devices can be made on the same chip and electronic devices. One silicon-based material system proposed is a silicon wafer on which a SiGe alloy has been deposited, such that the SiGe alloy serves as the optical waveguiding layer. An example of the channel waveguide 20 includes a silicon substrate 22, a core layer 24 made of SiGe, and a top cladding layer 26 made of silicon. The materials of the core layer 24 and the cladding layers 22 and 26 are selected such that the core has a greater index of refraction than the respective cladding layers 22 and 26, for optical confinement.

A common process for the production of virtually all silicon integrated circuits is the local oxidation of silicon (LOCOS) process. Generally, the LOCOS process separates and electrically isolates components from each other by a field oxide region formed by local oxidation of silicon. The LOCOS process for specific to SiGe is shown in Fig. 3a-c

A silicon nitride (Si₃N ) masking layer 28 of roughly 200 nm is deposited by chemical vapor deposition (CVD). Typically a layer 30 of Si0 _; about 30 nm thick, is usually grown before deposition of the Si₃N₄ masking layer 28, to provide strain compensation due to thermal expansion mismatch between silicon and Si₃N₄. This structure 20 is then placed in an oxidizing furnace at a temperature between 800 and 1200°C, with a wet-oxygen atmosphere, for a period of time ranging from 30 minutes to several hours. The silicon in the unmasked regions is oxidized, and silicon is consumed to create Si0₂₎ as shown in Fig. 3b. At the edges of the Si₃N₄ /Si0 layer, the thermal oxide encroaches under the mask, resulting in the "bird's beak" structure 32 that is characteristic of the LOCOS process. Fig. 3c shows the optical waveguide structure 20 with a rib waveguide 34 after the removal of the silicon oxide 30 and the nitride film 28. The rib waveguide 34 confines the light in both the horizontal and vertical directions thus channeling the light by virtue of the different refractive indices ni and n₂, as is well known in the art. However, the SiGe system has a number of persistent problems associated with strain and misfit dislocations in the epitaxial layer and crystal damage induced during high temperature LOCOS processing. These prohibit the fabrication of efficient waveguide devices, and eliminate the possibility of fabricating electronic components on the same substrate. Generally, in SiGe LOCOS waveguides, the SiGe layer 24 is below a critical thickness so that dislocations are not induced during high-temperature integrated circuit processing. However, any single SiGe layer 24 that is sufficiently thick to provide good optical confinement is inevitably above this critical thickness and will relax at these high temperatures. This relaxation of SiGe layers 24 at high temperatures significantly affects the optical loss in the material, thus the wafer can become unsuitable for electronic devices.

A number of processing and design issues have been developed to minimize these defects. Typical SiGe optical waveguide layers are invariably above even a metastable critical thickness for temperatures exceeding about 800°C. Processing at relatively low temperatures, close to this metastable limit does not minimize the induced misfit dislocation density for the following reasons. First, it is known to those of skill in the art that for temperatures above 800°C the interdiffusion of germanium in silicon can become significant. Although a relatively small effect in fully strained layers below the critical thickness, the diffusion becomes significant when dislocations are introduced. Misfit dislocations facilitate the diffusion of germanium into neighboring Si layers. This yields a competing mechanism for interfacial strain relaxation, reducing the amount of relaxation due to dislocation formation. At higher processing temperatures this diffusion is enhanced, making it more likely for layers to relax through interdiffusion than by dislocation formation. Since the diffusion length is quite small compared to a typical waveguiding layer the effect on the optical mode is minimal, but the effect on dislocation formation can be significant. Germanium in silicon at 1200°C has a diffusion coefficient of about 10-2 μm/h, suggesting that under typical LOCOS processing conditions of 1050°C for 3 hours, the germanium will diffuse a distance of around 100 nm. This helps maintain the germanium near the waveguide core and should not have a major effect on the waveguiding properties of a SiGe layer 24 that is 1000 nm thick, typical for optical waveguiding, although it could potentially affect the performance of some photonic devices.

Second, the onset of dislocation formation is quite abrupt, and very rapid to evolve to a more stable state where further temperature cycling has little effect. However, it is important to note that dislocation formation continues in this state, albeit at a much-reduced rate. This fact can potentially be used to help minimize dislocation formation by increasing the oxidation temperature, which minimizes the time required for oxidation. Minimizing the time in the furnace minimizes any further dislocation formation that occurs during thermal oxide growth. Although no further relaxation was observed after an additional 30 minutes of annealing, the oxidation times required for processing at 800°C can often be over twenty hours longer than those required for 1050°C. These significantly longer times can potentially lead to a high number of subsequent dislocations. For a given time, the dislocation density induced by processing at 900°C will not exceed that corresponding to 1100°C. However, for a given oxide thickness, it is possible for the dislocation density induced by processing at 900°C to slightly exceed that corresponding to 1100°C. Although the benefit from this effect is expected to be very small, but when coupled with the interdiffusion as discussed above and the mask layers discussed below, dislocation density may be reduced by more than an order of magnitude.

The dislocations induced during LOCOS processing can be reduced by choosing appropriate temperatures as discussed above, however they cannot be completely eliminated. Therefore, a second means of optimizing the LOCOS process through the use of strain-compensating mask layers 28 is used. The LOCOS process typically involves depositing a masking layer 28 of Si₃N₄, which acts as a barrier for the oxidation process. However, due to the large strain that can be imposed by the different thermal expansion coefficients of Si and Si₃N₄, a thin layer 30 of Si0₂ is generally deposited first, as described above.

The main problem encountered during LOCOS processing of SiGe is that the inherent strain in the SiGe layer 24, which causes the structure to relax through dislocation formation at high temperatures. However, by modifying the thickness and deposition temperatures of the

Si02/Si3N4 masking layers, the resulting strain may be tailored so that it opposes the strain inherent to the SiGe layer 24. This helps reduce the strain in the SiGe layered ring oxidation, and can thereby reduce the induced dislocation formation at high temperatures.

It is generally desirable to have an opposing strain in the mask layer that is larger than the strain of the SiGe layer 24. The reason for this is that the strain field from the mask layer must extend through the top cladding in order to affect the SiGe layer 24. Although the strain field will generally extend several microns, far enough to overlap the SiGe layer 24, the magnitude of he field decreases with distance. The temperature considerations discussed above help to minimize the dislocation formation during LOCOS processing, but do not eliminate it. Likewise, the strain of the SiO₂/Si₃N masking layers can only be used to help lower the strain in the SiGe layer 24 during oxidation, not completely eliminate it. This means that although the damage to the wafer can be minimized, the optical properties will be affected and the constraints on waveguide design can be very restrictive.

Now referring to Fig. 4, which shows an optical waveguide 40, in a preferred embodiment, the waveguide 40 is fabricated using a silicon-on-insulator (SOI) wafer 40. The SOI wafer 40 includes a silicon layer 42 isolated from a silicon substrate 44 by a silicon-dioxide layer 46. The top layer of silicon 42 acts as the waveguide core 43. Such a wafer 40 is commercially available from BOOKHAM TECHNOLOGY Inc., U.K. For optical confinement, index of refraction of the silicon dioxide layer 46 is greater that of layers 42 and 44, and light is channeled via the channel or rib waveguide 48.

Since SOI is not a strained system it is not sensitive to the polarization of the incoming light. Also, since there is no strain present, LOCOS processing in SOI can be done without any risk of dislocation formation. This results in an optical waveguide with substantially low optical loss, and the rest of the wafer 40 is perfectly suitable for electronic circuitry to be fabricated on the same chip. Since these electronics are fabricated using LOCOS as well, it is possible to fabricate both optical and electrical devices in the same processing run. The use of SOI wafers 40 in place of SiGe wafers 20 virtually eliminates all the inherent problems associated with the SiGe system.

Although the fabrication technique presented here is virtually identical to the LOCOS process, and to the process described in U.S. Patent 5,917,981, that patent is very specific to only include SiGe wafers of different alloy compositions, thus there is no mention of SOI wafers 40 or other material systems. The use of SOI wafers 40 is thus a significant improvement over the prior art.

Since the majority of electronic components are fabricated using LOCOS, this means that optical devices may be fabricated with next to no change in the equipment or process. This makes such technology available to a massive market at substantially low costs, something not yet achievable using III-V semiconductors or SiGe-based systems. In the preferred embodiment, the LOCOS process for fabricating waveguides in SOI is used. The SOI substrates are fabricated using a variety of techniques, such as separation by implantation of oxygen (SIMOX-SOI), smart-cut, and bond-and-etchback (BESOI). However, SOI substrates are available commercially from IBIS Technology Inc., U.S.A., and other suppliers. Silicon-on-insulator technology offers tremendous potential for cost-effective photonic components, as the structure allows for the fabrication of electrical devices that operate at higher speeds and lower power levels than traditional silicon devices. Also, SOI is greatly compatible with well-established silicon processing technology, such as the LOCOS process, which will be discussed below.

SOI waveguides 40 are unlike most other photonic systems in that the thick layers, in conjunction with high refractive index steps in the vertical direction, make any single-mode operation seem questionable. However, as is well known in the art for certain rib 48 dimensions a single-mode ridge waveguide exists even if the corresponding slab waveguide is multimode. However, a ridge waveguide supporting only a single mode may be designed by choosing a particular ridge width and height. The design conditions that dictate the rib 48 width/height ratio necessary for single-mode operation, are shown below in equation 1.1, in conjunction with Fig. 4, a single-mode operation requires

— ^w ≤ __- c+ . r 1.1

where r = h/H, and c = 0.3 and c = 0. The condition is only valid for r > 0.5, since at lower values of r for the effective index of the fundamental slab mode becomes lower than the effective index of any higher-order vertical modes in the central rib 48 region.

This behaviour can be understood by considering a rib waveguide 40 of well-defined height (H) and width (w). In order to filter out the higher-order modes, the width and height are chosen so that all high order modes in the rib waveguide have propagation constants lower than the fundamental mode of the slab waveguide regions on either side of the rib. Only the fundamental mode in the rib survives, since only its propagation constant is higher than that of the fundamental mode of the slab waveguide regions. Therefore, even if a higher-order mode is launched by off-axis excitation, the light will evolve to the fundamental mode as it propagates, resulting in a single-mode waveguide. This evolution into die fundamental mode generally occurs over a distance of less than 2000 μm.

The use of SOI for LOCOS optical waveguides eliminates virtually all of the problems inherent to the SiGe material system. Also, the temperature considerations and strain compensating mask layers developed for the SiGe system are not necessary in a SOI system, since SOI does not have a strained epitaxial layer and therefore does not dislocate at high temperatures. The optical loss in the material is therefore unaffected by the LOCOS process. The material itself has no inherent birefringence, so is very well suited for photonic devices. Furthermore, the maximum ridge heights achievable are not limited by the material considerations, but only by the self- limiting nature of the LOCOS process.

With SOI it is not necessary to use the mask layer for strain compensation, and therefore other mask materials such as metals can replace the Si0 /Si₃N₄. Such metals include nickel, titanium, and chromium, which can easily be evaporated onto the surface and patterned as a mask to inhibit oxidation of the underlying silicon. These metals typically have melting points above 1300°C. The LOCOS technique could be a completely thermal process if a thick thermal oxide could be grown and patterned, and act as a mask.

Generally, LOCOS optical waveguides in SOI can in theory exhibit lower loss than conventionally-etched waveguides in the same material. However, since the telecommunications wavelengths are far from the silicon absorption edge, the majority of the optical loss for etched SOI waveguides is due to the sidewall roughness that results from typical reactive ion etches or chemical etches. The LOCOS process, by its very nature, smoothes these sidewalls as the waveguide is created.

Also, the elimination of a strained epilayer means that the SOI wafer can withstand extended periods of time at high temperatures. Thus, the maximum achievable rib height is limited only by the self-limiting LOCOS process, results in feature heights approaching 2 μm. This is in contrast to the results in SiGe where the dislocation formation restricted rib heights to less than 0.6 μm. For example, a LOCOS waveguide 40 with a rib height of 1.2 μm, is achievable and provides good optical confinement in 2.1μm of SOI. Another application of the LOCOS process is the fabrication of optical components intended for WDM/DWDM networks using SOI waveguides. For example, these components include 1.3/1.55 μm duplexers and array waveguide grating (AWG) demultiplexers. By coupling the AWG with SiGe photodetector technology, these represent the necessary components for a monolithically integrated receiver chip suitable for a low cost DWDM. Many principles have been proposed and reported for realization of DWDM demultiplexers. Most commercially available components are based on dielectric filters, but as channel counts increase these devices become restrictively expensive to fabricate. Arrayed waveguide grating demultiplexers (AWGs) are one possible solution. AWG demultiplexers, also referred to as phased array demultiplexers, are realized in conventional waveguide technology and do not require the vertical etching or difficult fabrication steps often needed for other demultiplexer designs. The use of SOI to fabricate these components offers the potential for low cost, small device size, polarization insensitivity, compatibility with standard silicon electronics, and LOCOS processing.

Figure 5 shows an AWG device 50, which includes an input waveguide 52 and a series of output waveguides 54 coupled to a waveguide array 56 through slab waveguide regions. The input includes a plurality of channels centered around 1550 nm. As the light enters the free propagation region (FPR) 58, it is no longer laterally confined and becomes divergent through this slab waveguide section, some times referred to as the splitter. On arriving at the input aperture 60 the beam is coupled into the array waveguides 56. The radius of the input aperture 60 is chosen so that the waveguides in the array 56 will all be excited with the same phase. The length of the array waveguides 56 is chosen such that the optical path length difference between adjacent waveguides equals an integer multiple of the centre channel wavelength. For this wavelength, the fields in each waveguide arrive at the output aperture 62 with dual phase, apart from integer multiples of 211, and the field distribution at the input aperture 60 will be reproduced at the output aperture 62. This now corresponds to a convergent beam, and an image of the beam at the object plane will be formed at the centre of the image plane. This focused beam is coupled into an output waveguide 54 at the image plane, and the light exits.

For other wavelengths, the input into the array waveguides happens identically to that of the centre channel. The separation of the different wavelength channels begins in the array. Since each wavelength has a slightly different propagation constant, each wavelength will experience a slightly different phase shift while traveling through the array. The linearly increasing length of the array waveguides causes the phase change, induced by a change in the wavelength, to vary linearly along the output aperture. The resulting beam will be "steered" to a different point" along the image plane.' The phase front will tilt with varying wavelength, thus sweeping the focal spot across different output waveguides 62. By placing receiver waveguides at proper positions along the image plane, spatial separation of the different wavelength channels can be obtained.

The planar waveguide sections of an AWG 50 are often referred to as the splitter and combiner. In the splitter the input beam diverges to fill all of the array waveguides, and in the combiner the beam from the output aperture gets focused onto the image plane. If the splitter and combiner are not designed properly, then the output beam will not be properly focused on the output waveguides. This can contribute to crosstalk and device loss, since the beam could overlap other output waveguides, and not all of the power will be coupled into the intended waveguide.

The splitter and the combiner are typical examples of Rowland mountings. In its simplest form, the Rowland mounting condition states that the focal line of the mounting follows a circle with radius R, = Ra/2, where Ra is the distance from center of the image plane to the array waveguides. This focal line forms the image plane for the AWG 50, and the receiver waveguides should be positioned on this line.

Also, imperfections in the fabrication process may lead a significant amount of the device crosstalk. The propagation constants of the array waveguide modes can be altered by local variations in film thickness or waveguide width, which can lead to considerable errors in the phase transfer and can thereby increase the crosstalk level. It has also been shown that the standard stepping pattern used for e-beam writing of masks, a common problem encountered when patterning curved waveguides, can contribute to this source of crosstalk. As is known to those of skill in the art, improved crosstalk is feasible by correcting this phase error. However, because of the increased complexity in fabrication involved with this correction it is rarely used in practical devices.

In addition to the design criteria discussed above, the very large index contrast between the Si layer 42 and the oxide cladding 46 in SOI waveguides 40 present some unique challenges, which are overcome as descried below. Referring once again to Figure A, generally waveguides 40 fabricated in SOI are usually multimode, and have an intrinsic polarization birefringence which depends on the silicon overlayer thickness. Polarization birefringence can be removed by an appropriate choice of the SOI ridge waveguide width to height ratio, as described above. However, it is also desirable that the waveguides used in an AWG be single-mode and substantially free of birefringence. Meeting these two requirements is the fundamental challenge in designing AWG devices 50 on SOI. Although requirements for zero birefringence and single mode operation can be met using appropriate ridge design, they cannot always be satisfied simultaneously. A ridge that supports only a single mode is not necessarily birefringence free, and a ridge that is birefringence free may support higher order modes. Furthermore, the combiner/splitter sections of an AWG demultiplexer 50 are essentially slab waveguides and it is not possible to use ridge height and width to control waveguide properties.

Although it is relatively simple to design waveguides with zero birefringence in thick SOI layers 42, 44 and 46 a SOI thickness of 1.5 μm in order to reduce the device 50 size. The waveguides may be modeled using a finite-difference mode solver with semivectorial capability, commercially available from APOLLO PHOTONICS, U.S.A, or any other suitable technique. At these dimensions the etch depth and width are more carefully controlled, once a waveguide width is chosen, it is generally possible to calculate an etch depth that results in zero waveguide birefringence, and vice versa, for a waveguide with vertical sidewalls (e.g. fabricated using a reactive ion etch). This is not true for chemically-etched waveguides with sloped sidewalls. This is illustrated in Fig. 6, which shows the effective index difference between the TE and TM modes in an SOI ridge waveguide, for an etch depth of 0.75 μm. The waveguide birefringence is larger for a wet-etched waveguide, and not as sensitive to etch depth or ridge width. For the wet-etch, the ridge width refers to the width at the top of the waveguide, and the anisotropic etch results in a sidewall angle approximately 55° from horizontal.

Although the waveguide dimensions shown in Fig. 6 predict zero waveguide birefringence they do not assure single-mode operation, which is also necessary for effective demultiplexing using an AWG. In fact, many SOI waveguides with zero birefringence are inherently multi-mode. Also, the design of an AWG demultiplexer 50 requires careful attention to waveguide bending losses. In order to decrease device 50 size it is necessary to design waveguides with low loss through bends of small radii of curvature. By decreasing the thickness of the SOI layer, waveguides can be designed with very small radii of curvature, at the expense of coupling losses with optical fibers. The SOI used for photonics is typically 4 to 5 μm thick, but by reducing this thickness to 1.5 μm, the minimum acceptable bend radius can be reduced by more than an order of magnitude. Fig. 7 illustrates the bending losses calculated for 1.5 μm and 4 μm SOI. These bending losses were calculated using an optical waveguide mode solver from Apollo Photonics. The waveguide dimensions for this plot were chosen so that the waveguides would each support two horizontal modes and one vertical mode.

The calculated bending loss versus radius of curvature demonstrated a sharp threshold. Above a certain radius of curvature effectively no loss was observed, but for tighter bends the loss increased very rapidly, effectively to extinction. It is evident from Fig. 7 that the use of thinner SOI significantly reduces the minimum acceptable bend radius, from 8000 μm in 4 μm SOI, to 400 μm in 1.5 μm SOI. Also illustrated in Fig. 7, the threshold for bending loss is dependent on the waveguide mode. Higher-order horizontal modes leak away at larger radii of curvature, and this fact was used in our AWG design. By designing waveguides with zero birefringence the polarization sensitivity of our AWG is minimized, but typically create multi-mode guides, limiting the performance of the device. However by choosing an appropriate bend radius for the waveguides we can effectively filter out the higher order modes, leaving only the fundamental mode at the output splitter.

For the waveguides represented in Fig. 7, this radius is around 1000 μm. This modeling therefore predicts that the array waveguides can be made multi-mode if necessary to achieve zero birefringence. The modeling presented thus far provides the design criteria for SOI waveguides that are birefringence free and support only a single mode at the output splitter. The birefringence from the slab waveguide section of the output combiner has a minimal effect on device crosstalk. However, in addition to being birefringent, this slab waveguide will also support a high number of modes in the vertical direction. This occurs because the ridge width- to-height ratio used for obtaining single-mode waveguides in SOI is not respected in this slab waveguide section. This effect is specific to SOI and is not encountered in III-V or silica-based systems.

Passive optical components, such as, duplexers may be fabricated to demultiplex 1.3 and 1.55 μm wavelengths using SOI substrates and the LOCOS process, as described above. Wavelength isolation is measured using an infrared camera to obtain an intensity trace across the output facet. The isolation in these preliminary devices is measured to be roughly 10 dB and 8 dB in the 1.3 and 1.55 μm channels respectively. This performance is not acceptable for most telecom applications, however similar devices may be fabricated using chemical etching and exhibited isolation of -19 dB and -15 dB, showing that the change in refractive index due to LOCOS processing can be significant.

This performance is currently limited primarily by the device design, and not the LOCOS process itself. The performance can be significantly improved by incorporating a more complex design based on the modified refractive index values, and with the addition of electrodes to fine tune the wavelength selectivity through plasma dispersion. The benefits to fabrication and assembly costs that result from this can be significant, but may be further enhanced by the use of LOCOS processing for fabrication.

Although, only passive WDM components have been explored, it is also possible to use current injection to actively control SOI waveguide devices. Potential applications include optical switches, add/drop multiplexers, and variable optical attenuators. SOI is also suitable for on- chip integration of electronics, such as amplifier circuitry and control circuits. The technologies presented above permit the monolithic integration of SOI AWGs with SiGe photodetectors. Integrating amplifier circuitry onto the same chip would result in one of the highest levels of integration ever reported in a Si-based system, thus leading to true "systems-on-a-chip", a longstanding goal of Si-based optoelectronics.

The above-described embodiments of the invention are intended to be examples of the present invention and alterations and modifications may be effected thereto, by those of skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method of fabricating an optical waveguide by a local oxidation of silicon process (LOCOS) comprising:

(a) providing a silicon-on-insulator wafer having a first layer of silicon dioxide positioned between a silicon substrate and a second layer of silicon

(b) depositing a masking layer on at least a portion of said second layer of silicon; and (c ) oxidizing unmasked portions of said second layer, said oxidized unmasked portions of said second layer defining a channel waveguide in which optical radiation can propagate.

2. The method of claim 1 , wherein said first layer has a lower refractive index than said second layer.

3. The method of claim 1, wherein said masking layer includes a material capable of withstanding conditions employed using said LOCOS processing.

4. The method of claim 1 , wherein said masking layer comprises a material chosen from aluminum, nickel, titanium, chromium or an alloy thereof.

5. The method of claim 1 , wherein said oxidized unmasked portions of said second layer are removed.

6. An optical waveguide manufactured by a local oxidation of silicon process (LOCOS), said optical waveguide having: a first layer of silicon dioxide positioned between a silicon substrate and a second layer of silicon, said first layer having a refractive index lower than a refractive index of said silicon substrate; and a rib waveguide formed of said second layer of silicon to confine and channel light.

7. The optical waveguide of claim 6, wherein said dimensions of said first layer, said second layer and said silicon substrate are chosen such that said optical waveguide is birefrigence-free.

8. An optical device including said optical waveguide of claim 6, wherein said optical waveguide is an optical switch, an add/drop multiplexer, a variable optical attenuator or an optoelectronic system.

9. The optical waveguide of claim 6, wherein said rib waveguide includes increasing refractive index steps in a direction away from said silicon substrate.