WO2002009157A2

WO2002009157A2 - Alkali earth metal oxide gate insulators

Info

Publication number: WO2002009157A2
Application number: PCT/US2001/022652
Authority: WO
Inventors: Jamal Ramdani; Ravindranath Droopad; Lyndee Hilt
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2000-07-21
Filing date: 2001-07-18
Publication date: 2002-01-31
Anticipated expiration: 2003-01-21
Also published as: TW497209B; WO2002009157A3; AU2001278949A1

Abstract

High quality epitaxial layers of stable oxides can be grown overlying compound semiconductor material substrates. The compound semiconductor substrate (101) may be terminated with an atomic layer of gallium, for example (for a gallium arsenide substrate), forming a terminating layer (102). The oxide layer (105) is a layer of monocrystalline alkali earth oxide spaced apart from the compound semiconductor wafer by an oxide template layer (103) overlying the compound semiconductor substrate via the terminating layer. The oxide template layer (103) dissipates strain and permits the growth of a high quality monocrystalline oxide layer. Any lattice mismatch between the monocrystalline oxide layer and the underlying compound semiconductor substrate is decreased by the oxide template layer. The monocrystalline oxide layers can be used as gate dielectric in insulated gate field effect transistors.

Description

ALKALI EARTH METAL OXIDE ON GATE INSULATORS

Field of the Invention

This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to compound semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a monocrystalline compound semiconductor material.

Background of the Invention

The vast majority of semiconductor discrete devices and integrated circuits are fabricated from silicon, at least in part because of the availability of inexpensive, high quality monocrystalline silicon substrates. Other semiconductor materials, such as the so called compound semiconductor materials, have physical attributes, including wider bandgap and/or higher mobility than silicon, or direct bandgaps that make these materials advantageous for certain types of semiconductor devices. It is often desirable to grow a stable oxide on such compound semiconductor substrates in the electronic and optoelectronic industries. Unfortunately, native oxides, e . g. , arsenic oxide or gallium oxide, are unstable and the interface state density is too high to have complementary metal oxide semiconductor (CMOS) type performance.

Accordingly, a need exists for a semiconductor structure and a process for making such a structure having a high quality monocrystalline compound semiconductor substrate over which a stable oxide may be formed. Brief Description of the Drawings

The present invention is illustrated by way of example and not limited in the accompanying figures, in which like references indicate similar elements, and in which:

FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;

FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch in the context of a host crystal and a grown crystalline overlayer;

FIG. 5 illustrates a device structure including gate, source, and drain regions in accordance with an exemplary embodiment of the present invention; and

FIG. 6 is similar to FIG. 5 and further illustrates a device structure including a gate, a source region, and a drain region formed on a Group IV monocrystalline semiconductor substrate in accordance with an exemplary embodiment of the present invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description of the Drawings FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 100 in accordance with an embodiment of the invention. Semiconductor structure 100 includes a monocrystalline compound semiconductor layer 101, an oxide template layer 103, and a monocrystalline alkali earth metal oxide layer 105. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.

Monocrystalline compound semiconductor layer 101, in accordance with an embodiment of the invention, is a monocrystalline compound semiconductor substrate, such as a gallium arsenide substrate. Typically, any native oxides ( e . g. , gallium oxide) are removed from the surface of the monocrystalline compound semiconductor substrate to form a native oxide free gallium arsenide substrate. Thereafter, by terminating (i.e., stabilizing) the surface of monocrystalline compound semiconductor layer 101 with an atomic layer of gallium, e . g. , for a gallium arsenide substrate, oxide template layer 103 (and subsequently monocrystalline alkali earth metal oxide layer 105) may be grown epitaxially upon monocrystalline compound semiconductor layer 101. In this respect, terminating the surface of monocrystalline compound semiconductor layer

101 with gallium, aluminum, or indium, for example, (depending on the compound semiconductor substrate material selected for monocrystalline compound semiconductor layer 101) allows for a terminating layer

102 to be formed. Terminating layer 102 allows for a stable, high dielectric constant or medium dielectric constant oxide to be grown on monocrystalline compound semiconductor layer 101. In addition, terminating layer 102 helps to initiate the growth of oxide template layer

103 on monocrystalline compound semiconductor layer 101. In this way, terminating layer 102 helps to relieve the strain that might otherwise occur in oxide template layer 103 as a result of differences in the lattice constants of monocrystalline compound semiconductor layer 101 and oxide template layer 103. Relieving the strain in oxide template 103 aids in the growth of a high crystalline quality monocrystalline alkali earth metal oxide layer 105. Terminating layer 102 may form part of oxide template layer 103, but is nevertheless illustrated as a separate layer for purpose of description.

By way of illustration, if monocrystalline compound semiconductor layer 101 is a gallium arsenide substrate, then monocrystalline compound semiconductor layer 101 may be terminated by forming layer 102 comprising gallium, and then exposing layer 102 to strontium and oxygen to form a monolayer of oxide template layer 103 having a thickness in the range of about 4-5 Angstroms (A) . In this manner, terminating layer 102 may be exposed to a strontium (or barium) gallium oxide layer, for example, to aid in the growth of oxide template layer 103. Exposing terminating layer 102 to an alkali earth metal and oxygen forms oxide template 103 having the form alkali earth metal-gallium- oxygen { e . g. , SrGa₂0₄ or BaGa₂0₄) overlying monocrystalline compound semiconductor layer 101. To further illustrate this example, the growth of oxide template layer 103 may include using a monolayer of strontium oxide (e.g., SrO) followed by a layer of titanium oxide (e.g., Ti0₂) . Of course, oxide template layer 103 could be one or more monolayers thick, such as about 1 - 10 monolayers. In this way, oxide template layer 103 will provide a substantially stable oxide for CMOS applications, for example . Once oxide template layer 103 is formed, monocrystalline alkali earth metal oxide layer 105 may be formed overlying oxide template layer 103. Suitable monocrystalline alkali earth metal oxide layer 105 materials chemically bond to the surface of oxide template layer 103 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent monocrystalline alkali earth metal oxide layer 105.

Monocrystalline alkali earth metal oxide layer 105 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying layer. The resulting monocrystalline alkali earth metal oxide layer 105 may have a thickness of about 2-100 nm, such as about 5-10 nm. For example, the material could be an oxide or nitride having a lattice structure substantially matched to the underlying layer and to any subsequently applied overlying material. By way of illustration, monocrystalline alkali earth metal oxide layer 105 may be of the form strontium-barium- titanium-oxygen (Sr_xBa₁__xTi0₃, where x ranges from 0 to 1) , an alkali earth metal tin oxide (e.g., BaSn0₃) , and/or the like.

FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 200 in accordance with a further embodiment of the invention. Structure 200 is similar to the previously described semiconductor structure 100, except that structure 200 also includes an impurity doped layer (or impurity doped region) 207 positioned in monocrystalline compound semiconductor layer 101 and underlying oxide template layer 103. Impurity doped layer 207 is typically a compound semiconductor material (e.g., gallium arsenide) including an n or p type dopent or impurity (e.g., silicon) typically used in CMOS manufacturing . In accordance with one embodiment of the invention, impurity doped layer 207 is formed in monocrystalline compound semiconductor layer 101 at the interface between monocrystalline compound semiconductor layer 101 and oxide template layer 103. Typically, impurity doped layer 207 has a thickness in the range of approximately 5-500 nm and varies from about 1 - 10 monolayers. Impurity doped layer

207 provides an active region for building transistors, for example. A source region 217 and a drain 219 region may be formed, e.g., via doping, diffusion, or ion implantation, in impurity doped layer 207 to form structure 500, illustrated in FIG. 5. Once source 217 and drain 219 regions are formed in impurity doped layer 207, layers 103 and 105 are formed over layer 207, and a conductive electrode 215 (e.g., a gate electrode, a patterned metal electrode, or the like) is formed on monocrystalline alkali earth metal oxide layer 105 in alignment with source 217 and drain 219 regions in order to provide an insulated gate structure of an insulated field effect transistor, for example.

FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 300 in accordance with another exemplary embodiment of the invention. Structure 300 is similar to structures 100 and 200, except that structure 300 includes an oxide template layer 309, a Group IV monocrystalline semiconductor substrate 311, and optionally impurity doped layer 207.

In accordance with one embodiment of the invention, structure 300 also includes an amorphous intermediate layer 315 positioned between Group IV monocrystalline semiconductor substrate 311 and oxide template layer 309. Amorphous intermediate layer 315 is grown on Group IV monocrystalline semiconductor substrate 311, at the interface between Group IV monocrystalline semiconductor substrate 311 and the growing oxide template layer 309, by the oxidation of Group IV monocrystalline semiconductor substrate 311 during the growth of oxide template layer 309. Amorphous intermediate layer 315 helps to relieve the strain in oxide template layer 309 and by doing so, aids in the growth of a high crystalline quality monocrystalline alkali earth metal oxide layer 105. As noted above, amorphous intermediate layer 315 serves to relieve strain that might otherwise occur in the monocrystalline oxide template layer 309 as a result of differences in the lattice constants of Group IV, monocrystalline semiconductor substrate 311 and oxide template layer 309. If such strain is not relieved by amorphous intermediate layer 315, the strain may cause defects in the crystalline structure of oxide template layer 309. Defects in the crystalline structure of oxide template layer 309, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline alkali earth metal oxide layer 105. Amorphous intermediate layer 315 is preferably an oxide formed by the oxidation of the surface of Group IV monocrystalline semiconductor substrate 311, and more preferably is composed of a silicon oxide. The thickness of amorphous intermediate layer 315 is sufficient to relieve strain attributed to mismatches between the lattice constants of Group IV monocrystalline semiconductor substrate 311 and oxide template layer 309. Typically, amorphous intermediate layer 315 has a thickness in the range of approximately 0.5-5 nm. Oxide template layer 309 is similar to oxide template layer 103 in FIGS. 1 and 2, but is positioned between monocrystalline compound semiconductor layer 101 and Group IV monocrystalline semiconductor substrate 311. Oxide template layer 309 is formed overlying Group IV monocrystalline semiconductor substrate 311 (e.g., a silicon substrate) . Oxide template layer 309 helps to initiate the growth of monocrystalline compound semiconductor layer 101 on oxide template layer 309. Oxide template layer 309 is preferably a substantially stable monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material. For example, the material of oxide template layer 309 could be an oxide or nitride having a lattice structure substantially matched to the substrate and to the subsequently applied semiconductor material. Oxide template layer 309 is preferably grown on the underlying substrate. Once oxide template layer 309 is formed, monocrystalline compound semiconductor layer 101 may be epitaxially grown overlying oxide template layer 309. Oxide template layer 309 could be one or more monolayers thick, such as having a thickness of about 1 - 10 monolayers . Structure 300 may also include a terminating layer 313 between oxide template layer 309 and monocrystalline compound semiconductor layer 101. By terminating (i.e., stabilizing) the surface of oxide template layer 309 with a monolayer of strontium (or barium) oxide (e.g., SrO or BaO) or a titanium oxide (e.g., Ti0₂) to form terminating layer 313, monocrystalline compound semiconductor layer 101 may be grown epitaxially upon oxide template layer 309. In this respect, terminating the surface of oxide template layer 309 allows for a terminating layer 313 to be formed. Terminating layer 313 facilitates the growth of monocrystalline compound semiconductor layer 101 overlying oxide template layer 309. Terminating layer 313 may form part of oxide template layer 309; however, layer 313 is conveniently illustrated as a separate layer for purpose of description. As discussed above in connection with FIGS. 1 and 2, subsequent layers may be formed on monocrystalline compound semiconductor layer 101 as discussed above in connection with FIGS. 1 and 2. In addition, FIG. 6 illustrates an exemplary embodiment of the present invention, which is similar to structure 500, except structure 600 further includes a gate 221, a source

223, and a drain 225 formed on or within Group IV monocrystalline semiconductor substrate 311. In addition to structural characteristics illustrated in FIGS. 1-3, FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 401 illustrates the boundary of high crystalline quality material . The area to the right of curve 401 represents layers that has a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm may have defects .

In accordance with one embodiment of the invention, monocrystalline compound semiconductor layer 101 is a (100) oriented monocrystalline gallium arsenide wafer and oxide template layer 103 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate (e.g., strontium titanate, barium titanate, or the like) material by 45° with respect to the crystal orientation of the gallium arsenide substrate wafer.

The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In a similar manner, oxide template layer 103 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of oxide template layer 103 and the monocrystalline substrate must be substantially matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer . To achieve high crystalline quality in epitaxially grown monocrystalline alkali earth metal oxide layer 105, oxide template layer 103 must be of high crystalline quality. In addition, in order to achieve high crystalline quality in monocrystalline alkali earth metal oxide layer 105, substantial matching between the crystal lattice constant of the host crystal (i.e., monocrystalline compound semiconductor layer 101) and the grown crystal (i.e., monocrystalline alkali earth metal oxide layer 105) is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. If the host crystal is' gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and oxide template layer

103 is monocrystalline Sr^a^JTiO. , substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of oxide template layer 103.

Similarly, if oxide template layer 103 material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and monocrystalline alkali earth metal oxide layer 105 is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer (i.e., monocrystalline alkali earth metal oxide layer 105) by 45° with respect to the host crystal layer. In some instances, a crystalline semiconductor buffer (or oxide) layer between the host crystal and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline alkali earth metal oxide layer 105 that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline alkali earth metal oxide layer 105 can thereby be achieved.

Referring to FIGS. 1 - 6, monocrystalline compound semiconductor layer 101 is a monocrystalline substrate such as a monocrystalline gallium arsenide substrate. A compound semiconductor material of monocrystalline compound semiconductor layer 101 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds) , and/or mixed II-VI compounds. For example, monocrystalline compound semiconductor layer 101 includes materials from Group ill and V of the periodic table. Examples of Group III materials include aluminum, gallium, indium, and the like.

Examples of Group V materials include phosphorous, arsenic, tin, and the like. Further examples of suitable compound semiconductor materials include gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , gallium indium phosphide (GalnP) , aluminum indium arsenide

(AlInAs) , indium phosphide (InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like. Although not illustrated, in accordance with the present invention, monocrystalline compound semiconductor layer 101 may include one or more layers, e.g., GalnAs and/or AlInAs overlying a layer of InP. Monocrystalline compound semiconductor layer 101 (e.g., when formed above layer 313) may be prepared by Molecular Beam Epitaxy (MBE) , chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.

Terminating layer 102 is typically a thin film of gallium, aluminum, or another material used in monocrystalline compound semiconductor layer 101. For example, terminating layer 102 may be a monolayer of gallium in a gallium arsenide monocrystalline compound semiconductor layer 101 (or a monolayer of aluminum in a gallium aluminum arsenide monocrystalline compound semiconductor layer 101) deposited by way of MBE, MOCVD, ALE, or MEE.

Oxide template layer 103 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying layer and with the overlying material. For example, the material of oxide template layer 103 could be an oxide or nitride having a lattice structure substantially matched to the underlying layer and to the subsequently applied overlying material . Materials that are suitable for oxide template layer 103 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for oxide template layer 103. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements and have a perovskite crystalline structure. In some specific applications, the metal oxides or nitride may include three or more different metallic elements. For example, oxide template layer 103 may include an element from monocrystalline compound semiconductor layer 101 and oxygen. By way of further illustration, oxide template layer 103 may be of the form A-gallium-oxygen (A-Ga-O) and/or A-aluminum- oxygen (A-Al-0) for a gallium arsenide substrate, or A- indium-oxygen (A-In-O) for an indium phosphide substrate, where A is an alkali earth metal. As such, oxide template layer 103 may be a thin layer of A-Ga-O (e.g., one monolayer) . Still further examples of oxide template layer 103 include strontium gallium oxide (e.g., SrGa₂0₄) , barium gallium oxide (e.g., BaGa₂0₃) , a thin layer of gallium and a thin layer of strontium-oxygen (Sr-0) , a thin layer of gallium and a thin layer of barium-oxygen

(Ba-O) , a thin layer of indium-tin-oxygen (In-Sn-0) , a thin layer of tin-indium-oxygen (e.g., Snln₂0₄) , and/or a thin layer of indium and a thin layer of tin-oxygen (Sn-O)

(where a "thin layer" implies about one monolayer) . Oxide template layer 103 may be epitaxially grown on the underlying layer. For example, using any of the methods discussed above with forming layer 101. Materials that are suitable for monocrystalline alkali earth metal oxide layer 105 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for monocrystalline alkali earth metal oxide layer 105. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements. Monocrystalline alkali earth metal oxide layer 105 may be epitaxially grown overlying oxide template layer 103 using MBE, MOCVD, ALE, or MEE, among other processes.

Group IV monocrystalline semiconductor substrate 311, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group

IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably Group IV monocrystalline semiconductor substrate 311 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.

Materials that are suitable for oxide template layer 309 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for oxide template layer 309. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements. Suitable oxide template materials chemically bond to the surface of oxide template layer 309 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent monocrystalline compound semiconductor layer 101. Examples of oxide template layer 309 include strontium titanium oxide (SrTi0₃) , barium titanium oxide (BaTi0₃) , or the like.

Appropriate materials for terminating layer 313 for a gallium arsenide substrate include an atomic layer of strontium-oxygen (SrO) , titanium-oxygen (TiO) , gallium- strontium-oxygen (Ga-Sr-O) , arsenic-strontium-oxygen (As- Sr-O) , titanium-arsenic-oxygen (Ti-As-O) , titanium- gallium-oxygen (Ti-Ga-O) , or the like. Another example includes terminating monocrystalline compound semiconductor layer 101 with indium by depositing a monolayer of indium and exposing the indium layer of monocrystalline compound semiconductor layer 101 to tin and oxygen to form an indium-tin-oxygen (InSnO) oxide having one or more monolayers.. Appropriate materials for terminating layer 313 for an indium phosphide substrate include an atomic layer of barium-titanium-oxygen (Ba-Ti- 0) , indium-tin-oxygen (In-Sn-0) , indium-tin-phosphorous (In-Sn-P) , or the like.

The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1, 2, and 5. The process starts by providing a monocrystalline compound semiconductor substrate comprising gallium arsenide or indium phosphide, for example. In accordance with an exemplary embodiment of the invention, the compound semiconductor substrate is a gallium arsenide wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 2°-6° off axis. At least a portion of the compound semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare gallium arsenide is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline compound semiconductor substrate, the native oxide layer must first be substantially removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by thermal desorption, where the substrate is heated to about 600-650 °C under a flow of arsenic to obtain a substantially arsenic stable surface. At this time, the arsenic flow is typically turned off, whereby a gallium stable surface results (e.g., the terminating layer) . The resultant surface is a gallium, oxide-free surface. Reflection of High Energy Electron Deflection (RHEED) may be used to monitor the shift from an arsenic stable surface to a gallium stable surface, for example. The resultant surface exhibits an ordered 4x2 gallium stabilized structure having a terminating layer (e.g., one atomic layer) of gallium in this example. A stochiometric surface is desired to maintain the stability of the surface.

At this time, the terminating layer may be exposed to strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 400-650 °C . The resultant surface, which exhibits an ordered 4x2 structure, includes strontium, oxygen, and gallium. The ordered 4x2 structure forms an oxide template (e.g., one monolayer) for the ordered growth of an overlying layer of a monocrystalline oxide. The oxide template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.

In accordance with an alternate embodiment of the invention, the native oxide can be removed and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 400-650 °C. At this temperature, a solid state reaction takes place between the strontium oxide and the native oxide causing the reduction of the native oxide and leaving an ordered 4x2 structure with strontium, oxygen, and gallium remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.

Following the removal of the native oxide (e.g., gallium oxide) from the surface of the substrate and termination of the surface of the substrate (e.g., with gallium) , in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 300-650 °C and a layer of strontium titanate is grown on the template layer by MBE. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 4x2 crystalline structure of the underlying substrate. As noted above, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm may have defects . Optionally, following the removal of the gallium oxide from the surface of the substrate, in accordance with one embodiment of the invention, an impurity doped layer may be formed to provide an active region. The active region allows for subsequent formation of a source region and a drain region, for example. Alternatively, such regions may be formed prior to removing the gallium oxide, for example, by doping a portion of the substrate.

Each of the variations of compound semiconductor ■ materials and monocrystalline oxide layers uses an appropriate template for initiating the growth of the subsequent layer. For example, if the compound semiconductor material is indium gallium arsenide, indium aluminum, arsenide, or indium phosphide, for example, the terminating layer and/or template oxide may include a thin layer of gallium, aluminum, or indium, respectively, as a precursor to depositing an alkaline earth metal oxide. Each of these depositions helps to form a template for the deposition of a monocrystalline alkali earth metal oxide layer . An alternate embodiment of the present invention illustrates a process for fabricating a semiconductor structure such as the structures depicted in FIGS. 3 and 6. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 0.5-6° off axis. At 5. least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any 0 oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor 5 substrate, although such a grown oxide is not essential to the process in accordance with the invention.

In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the 0 crystalline structure of the underlying substrate. The following process is preferably carried out by MBE, although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer 5 of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750 C° to cause the strontium to 0 react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer. In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750 °C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer. Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800 °C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer. After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material. For the subsequent growth of a layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this terminating (or capping) layer, arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O- As . Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form a gallium arsenide substrate. Once a gallium arenside layer is formed, the subsequent layers described in connection with FIGS. 1, 2, and 5 may be formed in accordance with the process described above. The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 100, 200, and 300 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.

Example 1 In accordance with one embodiment of the invention, monocrystalline compound semiconductor layer 101 is a gallium arsenide substrate oriented in the (100) direction. The gallium arsenide substrate can be, for example, a substrate as is commonly used in making CMOS integrated circuits and other compound semiconductor devices. In accordance with this embodiment of the invention, terminating layer 102 is an atomic layer of gallium, which is exposed to strontium and oxygen to form oxide template layer 103 . As such, oxide template layer 103 is a monocrystalline layer of gallium-strontium-oxygen (e.g., SrGa,0₄) . Alternatively, if terminating layer 102 is exposed to strontium (or barium) , titanium, and oxygen, the resulting oxide template layer 103 is Sr^a^TiO_j where z ranges from 0 to 1. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of monocrystalline compound semiconductor layer 101.

In accordance with this embodiment of the invention, monocrystalline compound semiconductor layer 101 (as illustrated in FIG. 3) is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μ ) and preferably a thickness of about 0.5 μ to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the monocrystalline oxide . on the gallium arsenide or aluminum gallium arsenide, oxide template layer 103 is formed by capping (i.e., terminating or stabilizing) monocrystalline compound semiconductor layer 101. In this exemplary embodiment of the invention, oxide template layer 103 is preferably 1 - 10 monolayers of strontium gallium oxide (e.g., SrGa₂0₄) .

In accordance with this embodiment of the invention, once oxide template layer 103 is formed, monocrystalline alkali earth metal oxide layer 105 is formed overlying oxide template layer 103. In this exemplary embodiment, monocrystalline alkali earth metal oxide layer 105 is strontium-titanium-oxygen (SrTi0₃) .

Example 2 In accordance with a further embodiment of the invention of Example 1, impurity doped layer 207 is formed within or overlying monocrystalline compound semiconductor layer 101, and in any event underlying oxide template layer 309. In accordance with this exemplary embodiment, impurity doped layer 207 is a layer of gallium arsenide doped in order to provide source and drain regions for a transistor.

Example 3 In accordance with one embodiment of the invention, monocrystalline compound semiconductor layer 101 is an indium phosphide substrate oriented in the (100) direction. The indium phosphide substrate can be, for example, a substrate as is commonly used in making CMOS integrated circuits. In accordance with this embodiment of the invention, terminating layer 102 is an atomic layer of indium formed using MBE, MOCVD, ALE, or MEE, which is exposed to tin and oxygen to form oxide template layer 103 . As such, oxide template layer 103 is a monocrystalline layer of indium-tin-oxygen (e.g., In-Sn-O) .

Alternatively, if terminating layer 102 is exposed to strontium (or barium) , titanium, and oxygen, the resulting oxide template layer 103 is Sr_zBa₁__zTi0₃ where z ranges from 0 to 1. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of monocrystalline compound semiconductor layer 101.

In accordance with this embodiment of the invention and as illustrated in FIG. 3, monocrystalline compound semiconductor layer 101 is a layer of indium phosphide having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μ to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the monocrystalline oxide on the indium phosphide substrate, oxide template layer 103 is formed by capping (i.e., terminating or stabilizing) monocrystalline compound semiconductor layer 101. In this exemplary embodiment of the invention, oxide template layer 103 is preferably 1 - 10 monolayers (e.g, 1-2 monolayers) of tin indium oxide.

In accordance with this embodiment of the invention, once oxide template layer 103 is formed, monocrystalline alkali earth metal oxide layer 105 is formed overlying oxide template layer 103 by way of MBE, MOCVD, ALE, or MEE. In this exemplary embodiment, monocrystalline alkali earth metal oxide layer 105 is an alkali earth metal tin oxide having a thickness of about 8-11 nm. Example 4 In accordance with a further embodiment of the invention of Example 3, impurity doped layer 207 is formed within or overlying monocrystalline compound semiconductor layer 101, and in any event, underlying oxide template layer 309. In accordance with this exemplary embodiment, impurity doped layer 207 is a layer of gallium indium arsenide (or aluminum indium arsenide) overlying the indium phosphide substrate and doped in order to provide source and drain regions for a transistor. In addition, a patterned metal electrode may be formed overlying monocrystalline alkali earth metal oxide layer 105.

In the foregoing specification, the invention has been described with reference to specific embodiments.

However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element (s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms "comprises," "comprising, " or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

CLAIMSWhat is claimed is:

1. A monocrystalline oxide structure comprising:

a monocrystalline compound semiconductor layer;

an oxide template layer comprising oxygen and an element from the monocrystalline compound semiconductor layer formed on the monocrystalline compound semiconductor layer ,- and

a monocrystalline alkali earth metal oxide formed on the template layer.

2. The monocrystalline oxide structure of claim 1 further comprising an impurity doped layer formed in the monocrystalline compound semiconductor layer underlying the oxide template layer.

3. The monocrystalline oxide structure of claim 2 wherein the monocrystalline alkali earth metal oxide forms a gate dielectric of an insulated gate field effect transistor.

4. The monocrystalline oxide structure of claim 1 further comprising:

a Group IV monocrystalline semiconductor substrate; and

a second monocrystalline oxide epitaxially grown overlying the substrate and underlying the monocrystalline compound semiconductor layer and upon which the monocrystalline compound semiconductor layer was epitaxially grown.

5. The monocrystalline oxide structure of claim 1 wherein the monocrystalline compound semiconductor layer comprises a material selected from the group consisting of GalnAs and AlInAs and further comprising a monocrystalline layer of InP underlying the monocrystalline compound semiconductor layer.

6. The monocrystalline oxide structure of claim 5 wherein the oxide template layer comprises a layer selected from the group consisting of A-Ga-O, A-As-O, and A-Al-0 where A comprises an alkali earth metal.

. The monocrystalline oxide structure of claim 1 wherein the monocrystalline compound semiconductor layer comprises a material selected from the group consisting of GaAs, AlGaAs and GalnP.

8. The monocrystalline oxide structure of claim 7 wherein the template comprises a layer selected from the group consisting of A-Ga-O, A-As-O, and A-Al-0 where A comprises an alkali earth metal.

9. The monocrystalline oxide structure of claim 8 wherein the alkali earth metal oxide comprises an oxide selected from the group consisting of alkali earth metal titanates, haf ates, zirconates, niobates, and ruthenates .

10. The monocrystalline oxide structure of claim 7 wherein the template comprises SrGa₂0₄

11. The monocrystalline oxide structure of claim 7 wherein the template comprises BaGa₂0₄.

12. The monocrystalline oxide structure of claim 7 wherein the template comprises a thin layer of gallium and a thin layer selected from the group consisting of Sr-0 and Ba-0.

13. The monocrystalline oxide structure of claim 12 wherein the alkali earth metal oxide comprises Sr_xBa _lxTi0₃ where x ranges from 0 to 1.

14. The monocrystalline oxide structure of claim 1 wherein the monocrystalline semiconductor layer comprises InP.

15. The monocrystalline oxide structure of claim 14 wherein the template layer comprises a thin layer comprising In-Sn-0.

16. The monocrystalline oxide structure of claim 15 wherein the template layer comprises a thin layer of Snln₂0₄.

17. The monocrystalline oxide structure of claim 14 wherein the template layer comprises:

a thin layer of indium; and

a thin layer of Sn-0.

18. The monocrystalline oxide structure of claim 17 wherein the alkali earth metal oxide comprises an alkali ^' earth metal tin oxide.

19. The monocrystalline oxide structure of claim 18 wherein the alkali earth metal oxide comprises BaSn0₃.

20. A process for fabricating a monocrystalline oxide structure comprising the steps of:

providing a monocrystalline substrate comprising silicon;

forming an oxide layer overlying the substrate;

epitaxially growing a monocrystalline compound semiconductor layer overlying the oxide layer;

forming an impurity doped region in the monocrystalline compound semiconductor layer;

forming a template layer overlying the compound semiconductor layer, the template layer comprising an element from the compound semiconductor layer and oxygen;

epitaxially growing a monocrystalline alkali earth metal oxide overlying the template layer; and

forming a conductive electrode overlying the monocrystalline alkali earth metal oxide.

21. The process of claim 20 wherein the step of forming an impurity doped region comprises the step of forming source and drain regions .

22. The process of claim 21 wherein the step of forming a conductive electrode comprises the step of forming a gate electrode in alignment with the source and drain regions.

23. A process for fabricating a monocrystalline oxide structure comprising the steps of:

providing a monocrystalline compound semiconductor layer comprising a material selected from the group consisting of GaAs, GalnAs, AlGaAs, AlInAs, and GalnP;

terminating the surface of the monocrystalline layer with a layer comprising a terminating layer selected from the group consisting of gallium and aluminum;

exposing the terminating layer to an alkali earth metal and oxygen to form a template comprising alkali earth metal - gallium - oxygen or alkali earth metal - aluminum -oxygen overlying the monocrystalline compound semiconductor layer; and

epitaxially growing a layer of monocrystalline oxide overlying the template, the monocrystalline oxide comprising an oxide selected from the group consisting of alkali earth metal titanates, hafnates, zirconates, niobates, and ruthenates .

24. The process of claim 23 wherein the step of terminating comprises the step of depositing a monolayer of gallium by a process selected from the group consisting of MBE, MOCVD, ALE, and MEE.

25. The process of claim 23 wherein the step of terminating comprises the step of depositing a monolayer of aluminum by a process selected from the group consisting of MBE, MOCVD, ALE, and MEE.

26. The process of claim 23 wherein the step of exposing comprises the step of forming a template having a thickness of about 1 - 10 monolayers.

27. The process of claim 23 wherein the step of epitaxially growing comprises the step of growing a layer of monocrystalline oxide having a thickness of about 5 - lOnm by a process selected from the group consisting of MBE, MOCVD, ALE, and MEE.

28. The process of claim 23 further comprising the step of forming an impurity doped region in the monocrystalline compound semiconductor layer.

29. The process of claim 28 further comprising the step of forming a patterned metal electrode overlying the layer of monocrystalline oxide.

30. The process of claim 23 wherein the step of providing a monocrystalline compound semiconductor layer comprises the steps of:

providing a monocrystalline layer of InP;

forming a monocrystalline layer selected from the group consisting of GalnAs and AlInAs overlying the layer of InP.

31. A process for fabricating a monocrystalline oxide structure comprising the steps of:

providing a monocrystalline compound semiconductor layer comprising InP;

terminating the surface of the monocrystalline compound semiconductor layer with a layer of indium;

exposing the layer of indium to tin and oxygen to form an In-Sn-0 template; and

epitaxially growing an alkali earth metal tin oxide overlying the template .

32. The process of claim 31 wherein the step of terminating comprises the step of depositing a monolayer of indium by a process selected from the group consisting of MBE, MOCVD, ALE, and MEE.

33. The process of claim 31 wherein the step of exposing comprises the step of forming a template having a thickness of about 1 - 2 monolayers.

34. The process of claim 31 wherein the step of epitaxially growing comprises the step of growing a layer of monocrystalline oxide having a thickness of about 8 - lln by a process selected from the group consisting of MBE, MOCVD, ALE, and MEE.

35. The process of claim 31 further comprising the step of forming an impurity doped region in the monocrystalline compound semiconductor layer.

36. The process of claim 35 further comprising the step of forming a patterned metal electrode overlying the layer of monocrystalline oxide.