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WO2002006979A3 - Configurable hardware system - Google Patents

Configurable hardware system Download PDF

Info

Publication number
WO2002006979A3
WO2002006979A3 PCT/IL2001/000513 IL0100513W WO0206979A3 WO 2002006979 A3 WO2002006979 A3 WO 2002006979A3 IL 0100513 W IL0100513 W IL 0100513W WO 0206979 A3 WO0206979 A3 WO 0206979A3
Authority
WO
WIPO (PCT)
Prior art keywords
hardware device
configurable hardware
configurable
communication network
user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IL2001/000513
Other languages
French (fr)
Other versions
WO2002006979A2 (en
Inventor
Doron Handelman
Shlomo Kipnis
Gershon Bar-On
Daniel Ratner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synamedia Ltd
Original Assignee
NDS Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IL137296A external-priority patent/IL137296A/en
Application filed by NDS Ltd filed Critical NDS Ltd
Priority to AU2001264205A priority Critical patent/AU2001264205A1/en
Priority to GB0300114A priority patent/GB2382445B/en
Priority to US10/332,868 priority patent/US20040016002A1/en
Publication of WO2002006979A2 publication Critical patent/WO2002006979A2/en
Publication of WO2002006979A3 publication Critical patent/WO2002006979A3/en
Anticipated expiration legal-status Critical
Priority to US12/586,154 priority patent/US20100121748A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

A method for reconfiguring a circuit configuration of a configurable hardware device via a communication network. The method includes transmitting via the communication network from a hardware configuration provider unit to the configurable hardware device a circuit reconfiguration of the configurable hardware device in response to a request from a user of the configurable hardware device to reconfigure the configurable hardware device, implementing the circuit reconfiguration of the configurable hardware device thereby reconfiguring the configurable hardware device and providing a reconfigured hardware device and billing the user in response to a determination of correct operation of the reconfigured hardware device. A user unit in a communication network is also disclosed.
PCT/IL2001/000513 2000-07-13 2001-06-03 Configurable hardware system Ceased WO2002006979A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2001264205A AU2001264205A1 (en) 2000-07-13 2001-06-03 Configurable hardware system
GB0300114A GB2382445B (en) 2000-07-13 2001-06-03 Configurable hardware system
US10/332,868 US20040016002A1 (en) 2000-07-13 2001-06-03 Configurable hardware system
US12/586,154 US20100121748A1 (en) 2000-07-13 2009-09-16 Configuring field programmable devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IL137296A IL137296A (en) 2000-07-13 2000-07-13 Configurable hardware system
IL137296 2000-07-13
US27553301P 2001-03-12 2001-03-12
US60/275,533 2001-03-12

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/586,154 Continuation US20100121748A1 (en) 2000-07-13 2009-09-16 Configuring field programmable devices

Publications (2)

Publication Number Publication Date
WO2002006979A2 WO2002006979A2 (en) 2002-01-24
WO2002006979A3 true WO2002006979A3 (en) 2002-12-12

Family

ID=26323960

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2001/000513 Ceased WO2002006979A2 (en) 2000-07-13 2001-06-03 Configurable hardware system

Country Status (3)

Country Link
AU (1) AU2001264205A1 (en)
GB (1) GB2382445B (en)
WO (1) WO2002006979A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2381709A (en) * 2001-10-30 2003-05-07 Graeme Roy Smith Programmable set-top box and home gateway
US7786996B2 (en) 2006-10-24 2010-08-31 Sony Corporation System and method for object oriented hardware including cross-point switch interconnecting modules with I/O
GB2484931B (en) 2010-10-26 2014-04-30 Nds Ltd Efficient delivery of structured data items

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0275510A2 (en) * 1987-01-20 1988-07-27 International Business Machines Corporation Smart card having external programming capability and method of making same
US5181107A (en) * 1989-10-19 1993-01-19 Interactive Television Systems, Inc. Telephone access information service distribution system
US5666293A (en) * 1994-05-27 1997-09-09 Bell Atlantic Network Services, Inc. Downloading operating system software through a broadcast channel
EP0806737A2 (en) * 1996-05-08 1997-11-12 Lattice Semiconductor Corporation In-system programming with two wire interface
EP0813133A2 (en) * 1996-06-11 1997-12-17 International Business Machines Corporation A uniform mechanism for using signed content
US5995744A (en) * 1997-11-24 1999-11-30 Xilinx, Inc. Network configuration of programmable circuits
US6023570A (en) * 1998-02-13 2000-02-08 Lattice Semiconductor Corp. Sequential and simultaneous manufacturing programming of multiple in-system programmable systems through a data network

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0275510A2 (en) * 1987-01-20 1988-07-27 International Business Machines Corporation Smart card having external programming capability and method of making same
US5181107A (en) * 1989-10-19 1993-01-19 Interactive Television Systems, Inc. Telephone access information service distribution system
US5666293A (en) * 1994-05-27 1997-09-09 Bell Atlantic Network Services, Inc. Downloading operating system software through a broadcast channel
EP0806737A2 (en) * 1996-05-08 1997-11-12 Lattice Semiconductor Corporation In-system programming with two wire interface
EP0813133A2 (en) * 1996-06-11 1997-12-17 International Business Machines Corporation A uniform mechanism for using signed content
US5995744A (en) * 1997-11-24 1999-11-30 Xilinx, Inc. Network configuration of programmable circuits
US6023570A (en) * 1998-02-13 2000-02-08 Lattice Semiconductor Corp. Sequential and simultaneous manufacturing programming of multiple in-system programmable systems through a data network

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BROWN S ET AL: "FPGA AND CPLD ARCHITECTURES: A TUTORIAL", IEEE DESIGN & TEST OF COMPUTERS, IEEE COMPUTERS SOCIETY. LOS ALAMITOS, US, vol. 13, no. 2, 1 June 1996 (1996-06-01), pages 42 - 57, XP000596695, ISSN: 0740-7475 *

Also Published As

Publication number Publication date
GB2382445B (en) 2004-10-27
GB0300114D0 (en) 2003-02-05
WO2002006979A2 (en) 2002-01-24
AU2001264205A1 (en) 2002-01-30
GB2382445A (en) 2003-05-28

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