[go: up one dir, main page]

WO2002003266A2 - Procede de conception et d'implantation de circuits integres - Google Patents

Procede de conception et d'implantation de circuits integres Download PDF

Info

Publication number
WO2002003266A2
WO2002003266A2 PCT/US2001/021162 US0121162W WO0203266A2 WO 2002003266 A2 WO2002003266 A2 WO 2002003266A2 US 0121162 W US0121162 W US 0121162W WO 0203266 A2 WO0203266 A2 WO 0203266A2
Authority
WO
WIPO (PCT)
Prior art keywords
parasitic
design
extractions
layout
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/021162
Other languages
English (en)
Other versions
WO2002003266A3 (fr
Inventor
Gerd Frankowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Priority to EP01952407A priority Critical patent/EP1307835A2/fr
Publication of WO2002003266A2 publication Critical patent/WO2002003266A2/fr
Anticipated expiration legal-status Critical
Publication of WO2002003266A3 publication Critical patent/WO2002003266A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • FIG. 3A there is shown a schematic circuit 56, which is closely similar to the circuit 40 (FIG. 2A) .
  • the circuit 56 however has an upper wire 58 reconfigured from the wire 50 (FIG. 2A) to lower the parasitic resistance of the wire 50 by making the wire 58 substantially wider.
  • the parasitic capacitance here between the wires 46 and 58 is substantially higher than the parasitic capacitance between the wires 46 and 50 as indicated by the small circle 52 in FIG. 2A.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Procédé servant à améliorer la conception, l'implantation et la capacité d'un circuit intégré à très grande échelle (VLSI) possédant une pluralité de blocs et comportant des éléments parasites, ce qui consiste initialement à concevoir chacun des blocs de façon séparée et parallèle, à simuler chaque conception de bloc et à extraire des éléments parasites identifiés dans chaque bloc, puis à mémoriser les informations obtenues dans une base de données commune à la totalité des blocs. Ce procédé consiste, de plus, à reporter la notation des extractions parasites sur une base continue pour chacun des blocs afin de tirer avantage de la conception initiale, de la simulation et des étapes suivantes, à élaborer une implantation comportant des extractions parasites pour chaque conception de bloc après la simulation réussie de ce dernier, à réaliser une implantation totale de puce avec extraction parasite et à simuler au moyen de l'annotation des éléments parasites, l'implantation totale de la puce afin d'en optimiser la conception.
PCT/US2001/021162 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres Ceased WO2002003266A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01952407A EP1307835A2 (fr) 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60854200A 2000-06-30 2000-06-30
US09/608,542 2000-06-30

Publications (2)

Publication Number Publication Date
WO2002003266A2 true WO2002003266A2 (fr) 2002-01-10
WO2002003266A3 WO2002003266A3 (fr) 2003-02-27

Family

ID=24436957

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/021162 Ceased WO2002003266A2 (fr) 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres

Country Status (3)

Country Link
EP (1) EP1307835A2 (fr)
TW (1) TW518488B (fr)
WO (1) WO2002003266A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137088B2 (en) 2004-05-04 2006-11-14 Hewlett-Packard Development Company, L.P. System and method for determining signal coupling coefficients for lines

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8001514B2 (en) * 2008-04-23 2011-08-16 Synopsys, Inc. Method and apparatus for computing a detailed routability estimation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629860A (en) * 1994-05-16 1997-05-13 Motorola, Inc. Method for determining timing delays associated with placement and routing of an integrated circuit
CA2345648A1 (fr) * 1998-09-30 2000-04-06 Cadence Design Systems, Inc. Methodologie de construction fondee sur des blocs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137088B2 (en) 2004-05-04 2006-11-14 Hewlett-Packard Development Company, L.P. System and method for determining signal coupling coefficients for lines

Also Published As

Publication number Publication date
EP1307835A2 (fr) 2003-05-07
WO2002003266A3 (fr) 2003-02-27
TW518488B (en) 2003-01-21

Similar Documents

Publication Publication Date Title
US5764533A (en) Apparatus and methods for generating cell layouts
US8020121B2 (en) Layout method and layout apparatus for semiconductor integrated circuit
EP3584724A1 (fr) Conception d'un circuit en 3d comprenant des macros
US6028991A (en) Layout parameter extraction device
US5247456A (en) Method and apparatus for forming layout pattern of semiconductor integrated circuit
JP2002231815A (ja) 半導体集積回路
CN114730353A (zh) 使用具有金属线的单元进行电路设计
US6077308A (en) Creating layout for integrated circuit structures
JP2001357090A (ja) 論理合成方法及び論理合成装置
US6442740B1 (en) Clock signal analysis device and clock signal analysis method
JP3938220B2 (ja) 大規模集積回路装置の製造方法及び大規模集積回路装置
Cho et al. FLOSS: An approach to automated layout for high-volume designs
JP2002110797A (ja) クロック配線の設計方法
CN114077274A (zh) 引导式电网增强的系统和方法
JP2010257164A (ja) 半導体集積回路装置の設計方法およびプログラム
US7032207B2 (en) Method of designing semiconductor integrated circuit with accurate capacitance extraction
US6496968B1 (en) Hierarchical wiring method for a semiconductor integrated circuit
US6184711B1 (en) Low impact signal buffering in integrated circuits
EP1307835A2 (fr) Procede de conception et d'implantation de circuits integres
US6629300B1 (en) CAD system for an ASIC
JP2004054522A (ja) 半導体装置の同時スイッチングノイズ評価方法
US7380231B2 (en) Wire spreading through geotopological layout
JP4668974B2 (ja) 半導体装置の設計方法、半導体装置設計システム及びコンピュータプログラム
CN114662446A (zh) 一种用以减小动态功耗的布线优化方法
JP3107207B2 (ja) 論理回路改善方法および論理回路改善方式

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2001952407

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2001952407

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Ref document number: 2001952407

Country of ref document: EP