[go: up one dir, main page]

WO2002001638A3 - Microelectronic packages including reactive components, and methods of fabricating the same - Google Patents

Microelectronic packages including reactive components, and methods of fabricating the same Download PDF

Info

Publication number
WO2002001638A3
WO2002001638A3 PCT/IB2001/001157 IB0101157W WO0201638A3 WO 2002001638 A3 WO2002001638 A3 WO 2002001638A3 IB 0101157 W IB0101157 W IB 0101157W WO 0201638 A3 WO0201638 A3 WO 0201638A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
fabricating
methods
same
microelectronic packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2001/001157
Other languages
French (fr)
Other versions
WO2002001638A2 (en
Inventor
Ramaswamy Mahadevan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Viavi Solutions Inc
Original Assignee
JDS Uniphase Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JDS Uniphase Corp filed Critical JDS Uniphase Corp
Priority to AU2001274414A priority Critical patent/AU2001274414A1/en
Publication of WO2002001638A2 publication Critical patent/WO2002001638A2/en
Anticipated expiration legal-status Critical
Publication of WO2002001638A3 publication Critical patent/WO2002001638A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/99—Microstructural systems or auxiliary parts thereof not provided for in B81B2207/01 - B81B2207/115
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Microelectronic packages include at least one reactive component, such as a capacitor, inductor and/or mutual inductor that may be of fixed or variable value. At least one reactive component is fabricated on a first face of a first substrate. The first face of the first substrate is placed adjacent a second face of a second substrate, with at least one solder bump between the at least one reactive component and the second face. The at least one solder bump is reflowed, to join the at least one reactive component to the second substrate. The reflowing may be followed by releasing the first substrate from the at least one reactive component.
PCT/IB2001/001157 2000-06-30 2001-06-21 Microelectronic packages including reactive components, and methods of fabricating the same Ceased WO2002001638A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001274414A AU2001274414A1 (en) 2000-06-30 2001-06-21 Microelectronic packages including reactive components, and methods of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21555300P 2000-06-30 2000-06-30
US60/215,553 2000-06-30

Publications (2)

Publication Number Publication Date
WO2002001638A2 WO2002001638A2 (en) 2002-01-03
WO2002001638A3 true WO2002001638A3 (en) 2004-05-13

Family

ID=22803424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2001/001157 Ceased WO2002001638A2 (en) 2000-06-30 2001-06-21 Microelectronic packages including reactive components, and methods of fabricating the same

Country Status (2)

Country Link
AU (1) AU2001274414A1 (en)
WO (1) WO2002001638A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8539666B2 (en) 2011-11-10 2013-09-24 Harris Corporation Method for making an electrical inductor and related inductor devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070317A (en) * 1989-01-17 1991-12-03 Bhagat Jayant K Miniature inductor for integrated circuits and devices
EP0551735A1 (en) * 1991-12-27 1993-07-21 Avx Corporation High accuracy surface mount inductor
JPH0714876A (en) * 1993-06-17 1995-01-17 Matsushita Electron Corp Integrated circuit device and manufacturing method thereof
EP0694932A1 (en) * 1994-07-29 1996-01-31 Plessey Semiconductors Limited Inductor device
US5541135A (en) * 1995-05-30 1996-07-30 Motorola, Inc. Method of fabricating a flip chip semiconductor device having an inductor
EP0809289A2 (en) * 1996-05-20 1997-11-26 Harris Corporation Lid air bridge for integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070317A (en) * 1989-01-17 1991-12-03 Bhagat Jayant K Miniature inductor for integrated circuits and devices
EP0551735A1 (en) * 1991-12-27 1993-07-21 Avx Corporation High accuracy surface mount inductor
JPH0714876A (en) * 1993-06-17 1995-01-17 Matsushita Electron Corp Integrated circuit device and manufacturing method thereof
EP0694932A1 (en) * 1994-07-29 1996-01-31 Plessey Semiconductors Limited Inductor device
US5541135A (en) * 1995-05-30 1996-07-30 Motorola, Inc. Method of fabricating a flip chip semiconductor device having an inductor
EP0809289A2 (en) * 1996-05-20 1997-11-26 Harris Corporation Lid air bridge for integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 04 31 May 1995 (1995-05-31) *

Also Published As

Publication number Publication date
AU2001274414A1 (en) 2002-01-08
WO2002001638A2 (en) 2002-01-03

Similar Documents

Publication Publication Date Title
WO2000054322A8 (en) Flip chip with integrated flux and underfill
WO2004112095A3 (en) Thermoplastic fluxing underfill composition and method
WO2004038769A3 (en) Flip-chip system and method of making same
WO2003009379A3 (en) Semiconductive device and method of formation
EP0568995A3 (en) Semiconductor device with bumps
WO2007053383A3 (en) Methods and apparatus for flip-chip-on-lead semiconductor package
EP1351297A3 (en) Semiconductor device, method of manufacturing the same, and phase shift mask
EP1233446A3 (en) Thermosetting resin composition and semiconductor device using the same
WO2002047162A3 (en) Microelectronic package having an integrated heat sink and build-up layers
AU2001241425A1 (en) Precision electroplated solder bumps and method for manufacturing thereof
WO2004034428A3 (en) Semiconductor device package
WO2002041398A3 (en) Microelectronic packages and packaging methods in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles
WO2003056934A3 (en) Encapsulation by coating with a mixture of lipids and hydrophobic, high melting point compounds
WO2007078717A3 (en) Solder foams, nano-porous solders, foamed-solder bumps in chip packages, methods of assembling same, and systems containing same
WO2013032956A3 (en) Methods of fabricating semiconductor chip solder structures by reflowing a first and a second metallic layer and corresponding device
TW200614395A (en) Bumping process and structure thereof
AU2002367203A1 (en) Connection substrate, multilayer wiring board using the connection substrate, substrate for semiconductor package, semiconductor package, and methods for manufacturing them
TW200507712A (en) Method of manufacturing mounting boards
WO2002054447A3 (en) System and method for prototyping and fabricating complex microwave circuits
TW200746359A (en) Capacitor attachment method
WO2002001638A3 (en) Microelectronic packages including reactive components, and methods of fabricating the same
EP1488880A3 (en) Solder joint structure, soldering method, and electronic-component manufacturing apparatus using the same structure and the method
WO2004039886A3 (en) Flip-chip system and method of making same
KR20060130107A (en) Various structure / height bumps for wafer level-chip scale packages
TW200725768A (en) Method for forming multi-layer bumps on a substrate

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP