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WO2001038970A3 - Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks - Google Patents

Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks Download PDF

Info

Publication number
WO2001038970A3
WO2001038970A3 PCT/US2000/026669 US0026669W WO0138970A3 WO 2001038970 A3 WO2001038970 A3 WO 2001038970A3 US 0026669 W US0026669 W US 0026669W WO 0138970 A3 WO0138970 A3 WO 0138970A3
Authority
WO
WIPO (PCT)
Prior art keywords
task
buffer
processor
buffer memories
methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/026669
Other languages
French (fr)
Other versions
WO2001038970A2 (en
Inventor
Paul W Dent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ericsson Inc
Original Assignee
Ericsson Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Inc filed Critical Ericsson Inc
Priority to AU77283/00A priority Critical patent/AU7728300A/en
Publication of WO2001038970A2 publication Critical patent/WO2001038970A2/en
Publication of WO2001038970A3 publication Critical patent/WO2001038970A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Methods, systems and buffer memories are provided that include one buffer per task rather than a single buffer, (the contents of which may be discarded or overwritten when switching tasks in a multi-tasking environment). The rate of cache misses is, therefore, dependent solely on a single task. Furthermore, the present invention provides systems and methods for transferring execution of instructions from one task to another task which may provide reduced overhead and improved utilization of processor cycles concurrently with access operations to a slower ROM to update a buffer memory responsive to a cache miss. The buffer memories are coupled to the ROM by a first, preferably wider, bus and to the processor by a second bus allowing buffer updates to one of the task's buffers while another task is executed from its buffer by the processor. An activity register is coupled to a task selection circuit to identify the highest priority task and select the corresponding buffer as the source of instructions for execution by the processor when the activity state of the various tasks in the multi-tasking environment changes. The activity state of a task is set responsive to the need for instruction execution for the particular task and also by the status of the associated buffer so that a task is set to inactive while buffer updates are performed, thereby allowing a different task to be designated as the highest priority task and executed from its own associated buffer during the buffer update.
PCT/US2000/026669 1999-11-22 2000-09-28 Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks Ceased WO2001038970A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU77283/00A AU7728300A (en) 1999-11-22 2000-09-28 Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44708199A 1999-11-22 1999-11-22
US09/447,081 1999-11-22

Publications (2)

Publication Number Publication Date
WO2001038970A2 WO2001038970A2 (en) 2001-05-31
WO2001038970A3 true WO2001038970A3 (en) 2002-03-07

Family

ID=23774937

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/026669 Ceased WO2001038970A2 (en) 1999-11-22 2000-09-28 Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks

Country Status (2)

Country Link
AU (1) AU7728300A (en)
WO (1) WO2001038970A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8694652B2 (en) 2003-10-15 2014-04-08 Qualcomm Incorporated Method, system and computer program for adding a field to a client capability packet sent from a client to a host

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* Cited by examiner, † Cited by third party
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US8812706B1 (en) 2001-09-06 2014-08-19 Qualcomm Incorporated Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system
US7062606B2 (en) * 2002-11-01 2006-06-13 Infineon Technologies Ag Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events
GB2401748B (en) * 2003-05-14 2005-04-13 Motorola Inc Apparatus and method of memory allocation therefor
KR101105175B1 (en) 2003-06-02 2012-01-12 퀄컴 인코포레이티드 Generating and implementing a signal protocol and interface for higher data rates
CN101194482B (en) 2003-08-13 2015-11-25 高通股份有限公司 A method and system for reading and writing at least one register between a host computer and a client computer in a communication system
KR100973103B1 (en) 2003-09-10 2010-08-02 콸콤 인코포레이티드 High-speed data interface
RU2337497C2 (en) 2004-03-10 2008-10-27 Квэлкомм Инкорпорейтед Device and method for implementing interface at high data transfer speed
US8650304B2 (en) 2004-06-04 2014-02-11 Qualcomm Incorporated Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system
EP1776632B1 (en) * 2004-08-03 2012-03-21 Nxp B.V. System, controller and method of controlling the communication between a processor and an external peripheral device
US8873584B2 (en) 2004-11-24 2014-10-28 Qualcomm Incorporated Digital data interface device
US8667363B2 (en) 2004-11-24 2014-03-04 Qualcomm Incorporated Systems and methods for implementing cyclic redundancy checks
US8539119B2 (en) 2004-11-24 2013-09-17 Qualcomm Incorporated Methods and apparatus for exchanging messages having a digital data interface device message format
US8692838B2 (en) 2004-11-24 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer
US8699330B2 (en) 2004-11-24 2014-04-15 Qualcomm Incorporated Systems and methods for digital data transmission rate control
US8692839B2 (en) 2005-11-23 2014-04-08 Qualcomm Incorporated Methods and systems for updating a buffer

Citations (8)

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EP0395835A2 (en) * 1989-05-03 1990-11-07 Intergraph Corporation Improved cache accessing method and apparatus
WO1993009497A2 (en) * 1991-11-04 1993-05-13 Unisys Corporation Memory unit including a multiple write cache
US5442747A (en) * 1993-09-27 1995-08-15 Auravision Corporation Flexible multiport multiformat burst buffer
EP0768608A2 (en) * 1995-10-13 1997-04-16 Sun Microsystems, Inc. Maximal concurrent lookup cache for computing systems having a multi-threaded environment
EP0856797A1 (en) * 1997-01-30 1998-08-05 STMicroelectronics Limited A cache system for concurrent processes
US5822757A (en) * 1991-01-15 1998-10-13 Philips Electronics North America Corporation Computer system with multi-buffer data cache for prefetching data having different temporal and spatial localities
WO1999034295A1 (en) * 1997-12-30 1999-07-08 Mcmz Technology Innovations Llc Computer cache memory windowing
US5930821A (en) * 1997-05-12 1999-07-27 Integrated Device Technology, Inc. Method and apparatus for shared cache lines in split data/code caches

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0395835A2 (en) * 1989-05-03 1990-11-07 Intergraph Corporation Improved cache accessing method and apparatus
US5822757A (en) * 1991-01-15 1998-10-13 Philips Electronics North America Corporation Computer system with multi-buffer data cache for prefetching data having different temporal and spatial localities
WO1993009497A2 (en) * 1991-11-04 1993-05-13 Unisys Corporation Memory unit including a multiple write cache
US5442747A (en) * 1993-09-27 1995-08-15 Auravision Corporation Flexible multiport multiformat burst buffer
EP0768608A2 (en) * 1995-10-13 1997-04-16 Sun Microsystems, Inc. Maximal concurrent lookup cache for computing systems having a multi-threaded environment
EP0856797A1 (en) * 1997-01-30 1998-08-05 STMicroelectronics Limited A cache system for concurrent processes
US5930821A (en) * 1997-05-12 1999-07-27 Integrated Device Technology, Inc. Method and apparatus for shared cache lines in split data/code caches
WO1999034295A1 (en) * 1997-12-30 1999-07-08 Mcmz Technology Innovations Llc Computer cache memory windowing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DONGWOOK K ET AL: "A PARTITIONED ON-CHIP VIRTUAL CACHE FOR FAST PROCESSORS", JOURNAL OF SYSTEMS ARCHITECTURE,NL,ELSEVIER SCIENCE PUBLISHERS BV., AMSTERDAM, vol. 43, no. 8, 1 May 1997 (1997-05-01), pages 519 - 531, XP000685730, ISSN: 1383-7621 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8694652B2 (en) 2003-10-15 2014-04-08 Qualcomm Incorporated Method, system and computer program for adding a field to a client capability packet sent from a client to a host

Also Published As

Publication number Publication date
WO2001038970A2 (en) 2001-05-31
AU7728300A (en) 2001-06-04

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