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WO2001024236A1 - Structures de semi-conducteur et leurs procedes de fabrication - Google Patents

Structures de semi-conducteur et leurs procedes de fabrication Download PDF

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Publication number
WO2001024236A1
WO2001024236A1 PCT/US2000/023098 US0023098W WO0124236A1 WO 2001024236 A1 WO2001024236 A1 WO 2001024236A1 US 0023098 W US0023098 W US 0023098W WO 0124236 A1 WO0124236 A1 WO 0124236A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
dielectric
capacitor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/023098
Other languages
English (en)
Inventor
Chenting Lin
Andreas Knorr
Yun Yu Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Infineon Technologies North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Publication of WO2001024236A1 publication Critical patent/WO2001024236A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10P14/418—
    • H10W20/0698—

Definitions

  • This invention relates generally to semiconductor structures and manufacturing methods and more particularly to the formation of capacitors formed on semiconductor bodies.
  • DRAMs Dynamic Random Access Memories
  • One type of such DRAMs includes an array of memory cells, each cell having a capacitor connected to a transistor.
  • the capacitor is formed as a stack over the surface of a semiconductor substrate.
  • the transistor is typically a MOSFET having a source, or drain region (i.e., source/drain region) thereof in contact with one plate, or electrode, of the capacitor through a conductive via, or "plug" passing through a dielectric formed over the semiconductor substrate.
  • the conductive via may be, for example, doped polycrystalline silicon.
  • a barrier metal is formed on the conductive via and then the first electrode of the capacitor is formed on the barrier metal.
  • the dielectric for the capacitor is formed on the first electrode.
  • the dielectric constant of the capacitor '; s dielectric must have a relatively high dielectric constant because the capacitance of the capacitor, for electrodes of fixed area, is directly proportional to the dielectric constant, Therefore, in order to reduce the size of the capacitor, more particularly the opposing surface areas of the electrode, for a required capacitance, the dielectric constant is increased proportionally.
  • the dielectric material used for the capacitor is formed using high temperature (e.g., 650 degrees Centigrade) in an oxidizing environment.
  • the barrier metal is used to protect the doped polycrystalline conductive via from diffusions between the first electrode and the conductive via and to prevent oxygen from diffusing to the conductive via.
  • a method for forming a capacitor having a first electrode electrically connected to a region in a semiconductor body.
  • the method includes forming an electrical conductor with an upper end terminating at an upper surface of the first dielectric layer and a lower end in contact with the region.
  • a barrier metal is formed on the upper end of the electrical conductor.
  • a bottom electrode of the capacitor is formed on the barrier layer.
  • a protective, dielectric material is formed on sidewalls of the barrier metal.
  • a dielectric layer is deposited over the protective material in a heated and oxidizing environment to form a dielectric for the capacitor.
  • An upper electrode for the capacitor is formed on the dielectric material.
  • the portions of the protective dielectric layer disposed on the sidewalls of the barrier layer protects the barrier from oxidation during the formation of the dielectric of the capacitor.
  • a method is provided for forming a capacitor.
  • the method includes forming a first electrode of the capacitor electrically connected to a region in a semiconductor body.
  • a first dielectric layer is deposited over the body with a via passing through such first dielectric layer to expose an underlying portion of the semiconductor body.
  • An electrical conductor is formed over the first dielectric layer with a portion of the first conductor passing through the via onto the region of the body and with such portion of the conductive layer having an upper end terminating at an upper surface of the first dielectric layer.
  • a barrier layer is formed over both the upper surface of the first dielectric layer and over the upper end of the electrical conductor.
  • An electrically conductive electrode layer is formed on the barrier layer.
  • the electrode layer is patterned, such patterning comprising removing selected portions of the electrode layer with a remaining portion of such electrode layer providing the first electrode for the capacitor. Portions of the barrier layer disposed under the removed portions of the electrode layer are removed while portions of the barrier layer remain disposed under the provided first electrode.
  • a second dielectric is formed over the first dielectric layer and over the first electrode, such second dielectric layer being deposited on sidewalls of the electrode and the remaining portions of the barrier layer. Upper portions of the second dielectric layer are removed while portions of such second dielectric layer remain disposed on both lower portions of the sidewalls of the first electrode and the sidewalls of the remaining portion of the barrier layer.
  • a third dielectric layer is formed over the first electrode to provide a dielectric for the capacitor.
  • the formation of the third dielectric layer includes heating in an oxidizing environment.
  • a second electrode for the capacitor is formed on the third dielectric layer.
  • a semiconductor structure having a capacitor thereon is provided. Such structure includes a first electrode of the capacitor electrically connected to a region in a semiconductor body. A first dielectric layer is disposed over the body. A conductive via is disposed through such first dielectric layer onto an underlying portion of the semiconductor body. A barrier layer is disposed on an upper end of the conductive via. A first electrode of the capacitor is disposed on the barrier layer. A second dielectric is disposed on sidewalls of the barrier layer. A third dielectric layer is disposed over the first electrode to provide a dielectric for the capacitor. A second electrode for the capacitor is formed on the third dielectric layer.
  • FIGS. 1 through 10 are diagrammatical, cross- sectional sketches of a semiconductor structure having a capacitor electrically connected to a substrate of such body at various stages in the fabrication thereof.
  • a semiconductor body 10 here a single crystal silicon substrate having a doped region 12, here the source or drain (source/drain) region of a field effect transistor, here a MOSFET, is provided.
  • a via 16 (FIG. 2) is formed through the first dielectric layer 14 using conventional photolithographic- etching techniques to expose an underlying portion of the semiconductor body 12, more particularly to expose the source/drain region 12 of such body 10.
  • An electrical conductive layer 18 is deposited over the body 10, as shown in FIG. 3.
  • the electrically conductive layer 18 is doped polycrystalline, or tungsten. Portions of the conductive layer 18 pass through the via 16 onto the source/drain region 12, as shown, and portions are disposed on the silicon dioxide layer 18, as shown.
  • the upper surface of the structure shown in FIG. 3 is planarized to remove the portions of the conductive layer 18 on the upper surface 19 of the silicon dioxide layer 14 and thereby provide the structure shown in FIG. 4.
  • the planarization may be of any conventional process such as, for example, chemical mechanical polishing or a reactive ion etch. It is noted that the conductive layer 18 appears as a plug having a lower end in electrical contact with the source/drain region 12 and an upper end
  • the barrier metal layer 30 is deposited over both the upper surface 19 (FIG. 4) of the first dielectric layer 14 and over the upper end 29 (FIG. 4) of the electrical conductive layer 18.
  • the barrier metal layer 30 is an electrically conductive material such as, for example, titanium nitride or tantalum silicon nitride.
  • an electrically conductive layer 32 is deposited on the barrier metal layer 30.
  • the electrically conductive layer 30 will, as will be described, provide the bottom electrode of a capacitor.
  • the electrically conductive layer 32 is platinum.
  • a layer of photoresist 36 is deposited on the electrically conductive layer 32 and is patterned, as shown, into a mask used to form the bottom electrode of a stack capacitor in a manner to be described. More particularly, the patterned photoresist layer 36 masks the region where the bottom electrode of the capacitor is to be formed. Using such photoresist 36 mask, the exposed portions of the conductive layer 32 are removed using any conventional etching process. The removed portions of the conductive layer 32 expose underlying portions of the barrier layer 30. The exposed portions of the barrier layer 30 are removed using any conventional etching processes. After the photoresist 30 mask is removed, the resulting structure is shown in FIG. 6.
  • a dielectric layer 38 here silicon dioxide or silicon nitride is chemically vapor deposited (CVD) over the surface of the structure shown in FIG. 6.
  • the CVD is at a low temperature.
  • the upper portions of the dielectric layer 38 are selectively etched back, as shown, to a desired thickness with, or without, chemical mechanical polishing. It is noted that the sidewalls 39 of the patterned barrier metal layer 30 are covered (i.e., protected by) portions of the dielectric layer 38.
  • a dielectric layer 40 having a high dielectric constant, is deposited over the surface of the structure shown in FIG. 8.
  • the dielectric layer 40 is, for example, BSTO or other high dielectric constant material, is deposited using CVD of PVD at a high temperature, for example at a temperature of about 650 degrees centigrade in an oxidizing atmosphere.
  • the patterned barrier metal layer 30 is protected against oxidation because of the dielectric protective layer 38 which is disposed on the sidewalls 39 of the barrier metal layer 30.
  • the silicon dioxide or silicon nitride layer 38 protects the patterned barrier metal layer 30 against oxidization during the heating/oxidation process.
  • a conductive layer here 42, is deposited over the dielectric layer 40, as shown in FIG. 9, to produce the structure shown; i.e., a capacitor 50 having a bottom electrode 32 electrically connected to the source/drain region 12 through the barrier metal layer 30 and the conductive plug (i.e., the doped material 18; an upper electrode 42; and, a high dielectric constant material 40 disposed between the two electrodes 32, 42 of the capacitor 50.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé permettant d'obtenir un condensateur ayant une première électrode électriquement connectée à une zone d'un corps de semi-conducteur. Ce procédé consiste à former un conducteur électrique dont l'extrémité supérieure enduite d'un métal servant de barrière aboutit sur une surface supérieure de la première couche diélectrique et dont l'extrémité inférieure est en contact avec ladite zone. Une électrode inférieure du condensateur est formée sur la couche barrière. Une matière protectrice et diélectrique est formée sur les parois latérales du métal de barrière. Une couche diélectrique est déposée sur la matière protectrice et soumise à la chaleur et à un environnement oxydant pour obtenir une matière diélectrique pour le condensateur. Une électrode supérieure pour le condensateur repose sur la matière diélectrique. Grâce à ce procédé, les parties de la couche diélectrique protectrice disposées sur les parois latérales de la couche barrière protège la barrière contre l'oxydation pendant la formation de l'isolant du condensateur.
PCT/US2000/023098 1999-09-27 2000-08-24 Structures de semi-conducteur et leurs procedes de fabrication Ceased WO2001024236A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40686299A 1999-09-27 1999-09-27
US09/406,862 1999-09-27

Publications (1)

Publication Number Publication Date
WO2001024236A1 true WO2001024236A1 (fr) 2001-04-05

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Application Number Title Priority Date Filing Date
PCT/US2000/023098 Ceased WO2001024236A1 (fr) 1999-09-27 2000-08-24 Structures de semi-conducteur et leurs procedes de fabrication

Country Status (1)

Country Link
WO (1) WO2001024236A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7504509B2 (en) 2003-12-19 2009-03-17 Plexxikon, Inc. Compounds and methods for development of Ret modulators
US8865735B2 (en) 2011-02-21 2014-10-21 Hoffman-La Roche Inc. Solid forms of a pharmaceutically active substance
US9096593B2 (en) 2009-11-06 2015-08-04 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US9150570B2 (en) 2012-05-31 2015-10-06 Plexxikon Inc. Synthesis of heterocyclic compounds
US9169250B2 (en) 2006-11-22 2015-10-27 Plexxikon Inc. Compounds modulating c-fms and/or c-kit activity and uses therefor
US9447089B2 (en) 2009-04-03 2016-09-20 Plexxikon Inc. Compositions and uses thereof
US9469640B2 (en) 2007-07-17 2016-10-18 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US9624213B2 (en) 2011-02-07 2017-04-18 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5335138A (en) * 1993-02-12 1994-08-02 Micron Semiconductor, Inc. High dielectric constant capacitor and method of manufacture
JPH1079481A (ja) * 1996-09-05 1998-03-24 Mitsubishi Electric Corp 導電層接続構造およびその製造方法
US5834348A (en) * 1993-01-27 1998-11-10 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor device having a ferroelectric capacitor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834348A (en) * 1993-01-27 1998-11-10 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor device having a ferroelectric capacitor
US5335138A (en) * 1993-02-12 1994-08-02 Micron Semiconductor, Inc. High dielectric constant capacitor and method of manufacture
JPH1079481A (ja) * 1996-09-05 1998-03-24 Mitsubishi Electric Corp 導電層接続構造およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 08 30 June 1998 (1998-06-30) *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7504509B2 (en) 2003-12-19 2009-03-17 Plexxikon, Inc. Compounds and methods for development of Ret modulators
US9169250B2 (en) 2006-11-22 2015-10-27 Plexxikon Inc. Compounds modulating c-fms and/or c-kit activity and uses therefor
US9487515B2 (en) 2006-11-22 2016-11-08 Plexxikon Inc. Compounds modulating c-fms and/or c-kit activity and uses therefor
US9469640B2 (en) 2007-07-17 2016-10-18 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US10426760B2 (en) 2007-07-17 2019-10-01 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US9844539B2 (en) 2007-07-17 2017-12-19 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US9663517B2 (en) 2009-04-03 2017-05-30 Plexxikon Inc. Compositions and uses thereof
US9447089B2 (en) 2009-04-03 2016-09-20 Plexxikon Inc. Compositions and uses thereof
US9096593B2 (en) 2009-11-06 2015-08-04 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US9624213B2 (en) 2011-02-07 2017-04-18 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US11337976B2 (en) 2011-02-07 2022-05-24 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US12076322B2 (en) 2011-02-07 2024-09-03 Plexxikon Inc. Compounds and methods for kinase modulation, and indications therefor
US8865735B2 (en) 2011-02-21 2014-10-21 Hoffman-La Roche Inc. Solid forms of a pharmaceutically active substance
US9150570B2 (en) 2012-05-31 2015-10-06 Plexxikon Inc. Synthesis of heterocyclic compounds
US9695169B2 (en) 2012-05-31 2017-07-04 Plexxikon Inc. Synthesis of heterocyclic compounds

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