WO2001015389A1 - Clock setting method, communication device using the method, and communication system - Google Patents

Abstract

A communication device comprising means for comparing first clock predominance level preset in a clock master device with a second predominance level preset in clock slave devices at predetermined intervals and switch means for switching the clock master device and clock slave devices when it is judged according to the results of the comparison that the second clock predominance level more suitable for the clock master device than the first clock predominance level is.

Description

 Specification

 Clock setting method and communication device and communication system using the method

 The present invention relates to a clock setting method and a communication device and a communication system using the method, and more particularly to a clock setting method for performing clock synchronization between functional units using dependent synchronization and a method thereof. To a communication device and a communication system. Background art

 For example, when transmitting and receiving data, it is necessary to prevent a malfunction caused by a difference between a clock transmitted from a transmission source and a clock transmitted from a reception source. For this reason, clock synchronization between devices that transmit and receive data includes independent synchronization, slave synchronization, and mutual synchronization.

 Independent synchronization means that each device uses an independent clock individually. Dependent synchronization is when a certain device is on the master side and transmits a clock along with data. Mutual synchronization involves arranging a variable clock generator in each device and exchanging clocks with each other for synchronization.

 In particular, the slave synchronization is based on various devices configured with multiple panels such as base station modems and ATM switches using ATM (Asynchronous Transfer Mode) technology, which is a recent high-speed data transfer technology. It is used for clock synchronization between each functional unit in.

 Conventionally, in an ATM switch, a function unit such as an ATM switch, which collects line power, is on the master side, and other function units connected to the function unit are on the clock slave side. Each functional unit has a function that can be used on either the clock master side or the clock slave side as a single unit, and the switching was performed by hardware.

However, mistakes in switching between the clock master side and clock slave side when incorporating a functional unit could cause bit slips and data errors. Also, if the stability of the master clock generated by the clock master deteriorates, There was a problem that data errors occurred. Disclosure of the invention

 The present invention has been made in view of the above points, and is a power function to automatically set a clock master side and a clock slave side. If the master clock generated by the clock master side deteriorates, the clock master side It is an object to provide a clock setting method capable of automatically switching between a slave side and a clock slave side, a communication device and a communication system using the method.

 In order to achieve this object, the clock setting method of the present invention includes the steps of comparing a first clock dominance level set in the own device with a second clock dominance level set in another device; Determining, based on the result of the comparison, whether the own device or another device is suitable for the clock device, and, according to the result of the determination, the own device is used as a clock master device or a clock slave device. And a setting step.

 In such a clock setting method, the clock superiority level of each device is compared, and the clock master device and the clock slave device can be appropriately set by determining one device corresponding to the clock master device. In particular, when the clock master device does not exist at startup such as when the power is turned on, the device most suitable for the clock master device can be set as the clock master device based on the clock superiority level of each device.

 For example, the clock superiority level is set in advance so as to be appropriate for the clock master device and to be low as appropriate for the clock slave device. In this case, the device with the largest clock superiority level among the devices is set as the clock master device.

 Also, in the clock setting method of the present invention, the step of performing the self-comparison may include transmitting the first clock superiority level to the other device by using a cell; transmitting the second clock superiority level to the own device using a cell.

In this way, the clock superiority level of each device can be easily transmitted and received. is there.

 Also, the clock setting method of the present invention includes a step of comparing the first clock superiority level set in the clock master device and the second clock superiority level set in the clock slave device at predetermined intervals. And if the self-comparison results in that the second clock superiority level power is determined to be more suitable for the clock master device than the first clock superiority level, the tin switches between the clock master device and the clock slave device. It is configured to comprise.

 In such a clock setting method, the first clock superiority level set in the clock master device during operation and the second clock superiority level set in the mouse slave device are compared at predetermined time intervals. Therefore, when the first clock dominance level decreases and the clock slave device becomes more suitable for the clock master device, the clock master device and the clock slave device are automatically switched.

 Therefore, even if the master clock of the clock master device is deteriorated during operation, it is possible to avoid deterioration in quality or stop operation and continue operation.

 The present invention also provides the clock setting method, wherein the first clock supplied from the ri clock master device is compared with a second clock generated by the it clock slave device. As a result, when an abnormality is detected in the relationship between the first clock and the second clock, the abnormality is notified to the self-serving clock master device. Reducing the first clock dominance level of the device.

 Thus, by comparing the first clock supplied from the clock master device with the second clock generated by the clock slave device, it is possible to detect the deterioration of the first clock or the second clock. If the deterioration of the first clock or the second clock is notified to the clock master device more than once, it can be regarded as the deterioration of the first clock supplied from the clock cell based on the rule of majority rule.

Then, if the first clock is considered to be degraded, the clock master device is automatically switched between the clock master device and the clock slave device by lowering the first clock superiority level of the clock master device. Avoid operations stoppage and operate It is possible to continue.

 The present invention also provides the above clock setting method, wherein the self-comparing step comprises: transmitting the first clock superiority level to the cell slave device using a cell; Transmitting the second clock dominance level to the clock device using a cell. In this way, the ability to easily transmit and receive the clock superiority level of each device is determined by the power.

 Further, in the clock setting method according to the present invention, the step of switching between the clock master device and the clock slave device includes: nn switching a self-clock slave device to a new clock master device; After the own clock slave device is switched to the new clock master device, a step of switching the current clock master device to the clock slave device may be provided.

 In this way, after switching the clock slave device to the new clock master device, by switching the existing clock master device to the clock slave device, it is possible to avoid a state where there is no clock master device. is there.

 Further, the present invention may be configured such that, in the clock setting method described above, the step of notifying the abnormality includes transmitting the if self abnormality to the il master master device using a cell.

 Thus, the deterioration of the first clock or the second clock can be easily transmitted to and received from the clock master device.

 Further, the communication device of the present invention includes: a superiority level comparing unit that compares the first clock superiority level set in the own device and the second clock superiority level set in another device; Based on the result of the above, the own device determines which of the other devices is suitable for the clock master device, and, based on the result of the determination, determines the own device as the clock master device or the clock slave device. And setting means for setting in the device.

In such a communication device, the clock master device and the clock slave device can be appropriately set by comparing the clock superiority level of each device and determining one device suitable for the clock master device. Especially when starting up when turning on the power. If a clock master device does not exist, the device most suitable for the clock master device can be set as the clock master device based on the clock superiority level of each device.

 The present invention also provides the communication device as described above, wherein the superiority level comparing means transmits the first clock superiority level to another device using a cell, and the other device. And a detecting means for detecting the second clock dominance level transmitted by using the cell.

 As described above, it is possible to easily transmit and receive the clock superiority level of each device, and the communication device of the present invention sets the first clock superiority level set in the clock master device and the clock superiority level set in the slave device. Superiority level comparing means for comparing the second clock superiority level for each predetermined period, and as a result of the self-comparison, the second clock superiority level is higher than the first clock superiority level by the clock controller. If it is determined that the clock master device and the clock slave device are determined to be suitable, a switching means for switching between the clock master device and the clock slave device is provided.

 In such a communication device, the first clock superiority level set in the clock master device during operation and the second clock superiority level set in the clock slave device are compared at predetermined time intervals. Therefore, when the first clock superiority level decreases and the clock slave device becomes more suitable for the clock master device, the clock master device and the clock slave device are automatically switched.

 Therefore, even if the master clock power of the clock master device deteriorates during operation, it is possible to continue operation while avoiding quality deterioration and operation stop.

 Also, the present invention provides a communication device as described above, wherein receiving means for receiving a comparison result of a first clock supplied from the self-clock master device and a second clock generated by the self-clock slave device; When the self-comparison result indicates that an abnormality has been detected in the relationship between the first clock and the second clock, the superiority level changing means for lowering the superiority level of the first clock of the clock device. May be further provided.

Thus, the first clock supplied from the clock device and the clock By comparing the first clock or the second clock with the second clock generated by the slave device, the deterioration of the first clock or the second clock can be detected. If more than one notification is received, it can be regarded as a deterioration of the first clock supplied from the master by the rule of majority. Then, if it is deemed that the first clock is degraded, the clock master device is automatically switched to the clock master device and the clock slave device by lowering the first clock superiority level of the clock master device, resulting in quality deterioration and operation stop. It is Rikikawano to continue operation while avoiding the problem.

 Further, in the communication device according to the present invention, in the communication device, the switching unit switches the clock slave device to a new clock master device, and the first switching device switches the clock slave device to a new clock master device. It may be configured to have a second switching means for switching the clock master device to the clock slave device later.

 As described above, after switching the clock slave device to the new clock master device and then switching the clock master device to the clock slave device, it is possible to avoid a state where there is no clock master device.

 Further, the present invention may be configured such that in the communication device described above, the self-editing means is supplied with the ri self-comparison result using a cell.

 Thus, the comparison result can be easily transmitted to and received from the clock master device.

Further, the communication system of the present invention has an advantage of comparing the first clock superiority level set in the clock master device and the second clock superiority levels respectively set in the plurality of clock slave devices at predetermined time intervals. A level comparing means; and, as a result of the comparison, when it is determined that the second clock dominance level is more suitable for the clock mass unit than the first clock dominance level, one clock slave with the clock mass unit is determined. Switching means for switching between the device and the device. In such a communication system, the clock master device and the clock slave device can be appropriately set by comparing the clock superiority level of each device and determining one device suitable for the clock master device. Especially when power is turned on If the clock master device does not exist at the time of resetting, the device most suitable for the clock master device can be set as the clock master device based on the clock superiority level of each device.

 Also, the present invention provides the communication system as described above, wherein a comparing means for comparing the first clock supplied from the clock master device with the second clock generated by the self-clock slave device; When detecting an abnormality in the relationship between the first clock and the second clock, a notifying means for notifying the master device of the abnormality when the abnormality is detected from a plurality of clock slave devices; A superiority level changing means for lowering the superiority level of the clock may be further provided.

 Thus, by comparing the first clock supplied from the clock master device with the second clock generated by the clock slave device, it is possible to detect the deterioration of the first clock or the second clock, If the clock master device is notified of the deterioration of the first clock or the second clock more than once, it can be regarded as the deterioration of the first clock supplied from the clock master based on the principle of majority rule.

 Then, if it is considered that the first clock is degraded, the first clock dominance level of the clock device is reduced, and the clock device is automatically switched to the clock slave device. It is possible to continue operation while avoiding outages.

 The present invention also provides the communication system as described above, wherein the self-switching means includes: first switching means for switching the clock slave device to a new clock master device; and after switching the clock slave device to a new clock master device. It may be configured to include second switching means for switching the clock master device to the clock slave device.

In this way, by switching the clock slave device to the new clock master device and then switching the clock master device to the clock slave device, it is possible to avoid a state in which there is no clock master device. . BRIEF DESCRIPTION OF THE FIGURES

 The features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

 FIG. 1 is a diagram illustrating the principle of an example of a clock setting method according to the present invention.

 FIG. 2 is a configuration diagram of an embodiment of an apparatus using the clock setting method of the present invention. FIG. 3 is a flowchart of an embodiment of the processing at the time of startup.

 FIG. 4 is a format diagram of an example of an ATM cell for realizing the processing of the present invention. FIG. 5 is a flowchart of an embodiment of processing on the clock slave side at the time of startup.

 FIG. 6 is a flowchart of an example of a process during operation.

 FIG. 7 is a flowchart of an example of the process in S250.

 FIG. 8 is a flowchart of an example of the process in S260. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that a case where the present invention is applied to an ATM device will be described as an embodiment of the present invention, but the present invention is not limited to this.

 FIG. 1 is a diagram illustrating the principle of U of the clock setting method of the present invention. The configuration shown in FIG. 1 includes a functional unit A 1000 on the clock master side, and functional units B 110, C 120, and n 130 on the clock slave side. The functional unit A100 is connected to each of the functional units B110, C120, and n130 on the clock slave side.

 Hereinafter, the principle of the present invention will be described in more detail with reference to FIG. FIG. 2 shows a configuration diagram of an embodiment of an apparatus using the clock setting method of the present invention. Note that FIG. 2 is an excerpt of iLh for convenience of explanation, and the functional unit A 100, functional unit B 110, and functional unit C 120 of FIG. 1 are extracted.

The functional unit A 1000 on the clock master side is connected to the functional units B 110 and C 120 on the plurality of clock slave sides. In FIG. 2, the number of functional units on the mouth slave side is two, and the number is basically unlimited. The functional unit A 100 on the clock master side includes transmitting units 6 and 8 for transmitting ATM cells, receiving units 7 and 9 for receiving ATM cells, and control for performing clock control and setting described later. The configuration includes a unit 5, clock switching units 3 and 4 for switching output clocks, an oscillator 2 for generating a clock, and a clock monitoring unit 1 for monitoring the clock.

 The functional units B 110 and C 120 on the clock slave side include transmitting units 15 and 21 for transmitting ATM cells, receiving units 14 and 20 for receiving ATM cells, and a clock control unit to be described later. Control units 13 and 19 for setting clocks, clock switching units 12 and 18 for switching output clocks, oscillators 11 and 17 for generating clocks, and clock viewing unit 1 for watching clocks 0, 16 are included.

 The functional unit A100 on the clock master side and the functional unit B110 on the clock slave side transmit and receive ATM cells via the transmission units 6, 15 and the reception units 7, 14. The functional unit A 100 on the clock master side and the functional unit C 120 on the clock slave side transmit and receive ATM cells via the transmission units 8 and 21 and the reception units 9 and 20. Note that the transmitters 6 and 8 operate on the same reference clock.

 The clock sections 1, 10, and 16 compare the clock cycles of the oscillators 2, 11, and 17 with the clock cycles β extracted from the receivers 7, 9, 14, and 20, respectively. In the functional unit Β 110 and the functional unit C 120 on the clock slave side, the clock frequency extracted from the receiving units 14 and 20 is compared with the clock frequency of the oscillators 11 and 17 for stability. The degree is always set to i, and when the stability is deteriorated, the control units 13 and 19 are notified to that effect.

The control units 13 and 19 notify the control unit 5 of the functional unit A 100 on the clock master side, using a cell described later, that the clock stability has deteriorated. If the deterioration of the clock stability is detected in both the functional unit B 110 and the functional unit C 120 on the clock slave side, the control unit 5 determines the functional unit A on the clock master side based on the principle of majority voting. It can be considered that a malfunction has occurred in the oscillator 2 of 100. It is considered that a failure has occurred in the oscillator 2 of the functional unit A 100 on the clock master side. In this case, the function unit B 110 or the machine unit C 120 currently on the clock slave side is switched to the clock master side based on the processing described later, and then the function unit A 10 on the clock mass side Switch 0 to clock slave side. In addition, each functional unit is set in advance in terms of the superiority level power in accordance with the degree of the clock master.

 Next, processing at the time of starting up the apparatus of the present invention will be described with reference to FIG. FIG. 3 shows a flowchart of one embodiment of the processing at the time of startup.

 In FIG. 3, in step S10, the power is turned on to the functional unit A100 or the ATM transmission path is connected, so that the initial state is established, and idle cells are flown on the transmission path. At this time, the operation is performed by the independent clock. It is assumed that the power of the functional unit Bl10 has already been turned on.

 Proceeding to step S20 following step S10, it is determined whether or not cell synchronization of the transmission line is established by the idle cell, and loss of LOS (Loss Of Signal), in other words, signal detection has been performed. If it is determined that a signal has been detected (Y E S in S 20), the process proceeds to step S 40. If it is determined that no signal is detected (NO in S20), the process proceeds to step S30, and the operation is performed by an independent clock. For example, in the case of the functional unit A 100 in FIG. 2, the operation is performed not by the clock extracted from the receiving unit 7 but by the clock of the oscillator 2.

 In step S40, with the link of the transmission path established, the functional unit A100 sends out a cell including its own clock superiority level and a transmission ID indicating the first cell. . For example, FIG. 4 shows an example of a cell transmitted in step S40.

 FIG. 4 shows a format diagram of an example of an ATM cell for realizing the processing of the present invention. The format shown in Fig. 4 consists of a 5-octet header section and a 48-octet payload section. The clock mode is set, the clock switching request is set at the 9th octet, and the clock comparison result is set at the 10th octet.

In Figure 4, the clock dominance level is set to 7 ("1 1 1" in binary), The transmission ID is set to "1". For this clock superiority level, for example, using 3 bits, a larger number is more suitable for the clock master side, and a smaller number is more suitable for the clock slave side. In this description, the clock superiority level of the functional unit A100 is assumed to be 3.

 When receiving the cell as shown in FIG. 4, the functional unit B 110 performs the processing of the flowchart shown in FIG. In step S100, the functional unit B110 receives from the functional unit A100 a cell including the clock dominance level and the transmission ID indicating the first cell.

 Proceeding to step S110 following step S100, the functional unit B110 includes the clock superiority level of the functional unit B110 and a transmission ID indicating that the cell is a response cell. The cell is sent to the functional unit A100. In this description, it is assumed that the clock superiority level of the functional unit B110 is 7.

 Returning to the flowchart of FIG. 3 and continuing the description, in step S 50, it is determined whether or not a response cell has been received from the function unit A 100 ヾ function unit B 110. If it is determined that a response cell has been received (Y E S in S 50), the process proceeds to step S 70. If the response cell is not received within the predetermined time (NO in S50), there may be an obstacle such as whether the functional unit B110 is not turned on or not connected to the road. Proceeding to step S60, the operation proceeds with the independent clock.In step S70, the control unit 5 of the functional unit A100 is included in the cell of its own clock superiority level and response. Functional unit Β Compare with 110 clock superiority level. When the clock superiority level of the functional unit A100 is equal to the clock superiority level of the functional unit B110, or the clock superiority level of the functional unit A1000 is higher (YES in S700). ), The process proceeds to step S800, and the control unit A1000 is on the clock cell side. If the clock dominance level of the functional unit A100 is smaller (NO in S70), the process proceeds to step S90, and the control unit A100 becomes a clock reef.

For example, when the clock superiority level of the functional unit A100 is 3 and the clock superiority level of the functional unit B110 is 7, the clock superiority level of the functional unit A100 itself is Since the level is smaller than the clock dominance level of the functional unit B110, the process proceeds to step S900, and the control unit A100 becomes the clock slave side.

 If the clock superiority level of the functional unit A100 is equal to the clock superiority level of the functional unit B110, the process proceeds to step S800 in this embodiment, and the control unit A100 Is configured to be on the clock master side. \ Not limited to this, it can be configured on the clock slave side.

 Next, the processing during operation of the apparatus of the present invention will be described with reference to FIG. FIG. 6 shows a flowchart of an embodiment of a process during operation.

 In FIG. 6, in step S200, each functional unit (for example, processing unit A100, processing unit B110, etc.) sends out a cell including its own clock superiority level at predetermined time intervals. I do. After step S200, the process proceeds to step S210, where each functional unit determines whether a response cell has been received. If it is determined that a response cell has been received (Y E S in S 210), the flow advances to step S 220. If it is determined that the response cell has not been received (NO in S210), the process proceeds to step S280.

 In step S220, it is determined whether the result of comparing the own clock superiority level with the clock superiority level included in the response cell is the same as the result of the previous comparison. If it is determined that the result of the comparison is the same as the result of the previous comparison, it can be determined that the master clock is stable, so the flow proceeds to step S280. If it is determined that the result of the comparison is not the same as the result of the previous comparison, the process proceeds to step S230 to change the functional unit on the clock master side, in other words, whether or not to perform the clock pad switching process. Is determined.

For example, in the case of Fig. 2, the clock comfort part 10 of the function part B110 and the clock comfort part 16 of the function part C120 are composed of the clocks of the oscillators 11 and 17 and the functions of the clock master. The clock supplied from the section A1000 is compared. At this time, if an abnormality is detected in the comparison result, the control unit 13 or 19 notifies the clock comparison result notification portion (for example, the format 10 in FIG. 4) included in the cell transmitted at predetermined time intervals. The abnormality is notified to the functional unit A1000 on the master clock side by using (cect.). When the control unit 5 of the functional unit A 100 is notified of an abnormality from both the functional unit B 110 and the functional unit C 120 using the notification part of the clock comparison result, the control unit 5 follows the principle of majority voting. Yo It determines that the oscillator 2 has deteriorated, and lowers its own clock superiority level by a predetermined level. The number of functional units on the clock slave side is not limited to two, and the greater the number, the higher the reliability.

 When the clock superiority level of the functional unit A 100 on the clock mass side becomes lower than the clock superiority level of the functional units B 110 and C 120 on the clock slave side, the clock mode is set. Is performed. When it is determined that the oscillator 2 has deteriorated based on the principle of majority decision, it is also possible to perform the switching process of the quick mode regardless of the clock superiority level. If there is more than one clock slave side, the clock superiority level of the clock slave side is compared to determine one clock slave side to switch to the clock master side.

 In step S230, the control unit 5 determines whether or not to perform the clock mode switching process, and determines that the clock mode switching process is to be performed (YES in step S230). Proceed to 240. If it is determined that the switching process of the clock mode is not performed (NO in S230), the process proceeds to step S280.

 In step S240, it is determined whether or not the current time is the clock master side. If it is determined that the current clock is on the clock master side (Y E S in S 240), the process proceeds to step S 260, where clock master switching processing described later is performed. If it is determined that the current time is not the clock master side (NO in S240), the process proceeds to step S250, and a clock slave switching process described later is performed. Following step S250, the process proceeds to step S270, and a request for switching the clock master to the clock slave is made.

 In the clock mass switching process of step S260, a request for switching to the clock slave side is made in step S270 after the clock slave switching process of step S250 is completed. Not done until This is to prevent the clock master side from being lost. After the clock slave side is switched to the clock master, the previous clock master side is switched to the clock slave side.

Then, the process proceeds to step S280 following steps S260 and S270, waits for a predetermined time, and proceeds to step S200 to continue the process. Next, the processing of S250 in FIG. 6 will be described in more detail. FIG. 7 shows a flowchart of an embodiment of the processing in S250.

 In step S251, a notification portion of a clock switching request included in a cell that is transmitted and re-transmitted at predetermined time intervals to a clock slave that switches from the current clock master to the clock master (for example, FIG. A request to switch the clock mode is made using the 9th octet in the format of 4).

 After step S251, the process proceeds to step S252, and it is determined whether or not the switching request has been received. If it is determined that the switching request has been received (Y E S in S 252), the process proceeds to step S 254. If it is determined that the switching request has not been received (NO in S252), the process proceeds to step S253 and waits until it is received.

 In step S254, when the clock mode switching request is received, for example, in the case of the functional unit B110, the clock switching unit 12 is controlled so that the clock supplied to the transmitting unit 15 is received by the receiving unit 144. Is switched to the clock of the oscillator 11 from the clock extracted in. After step S255, the process proceeds to step S255, and when the switching power to the clock master is finished, the control unit 13 sends the signal to the clock master (for example, the functional unit A100) that switches to the clock slave. A response cell indicating the end of switching is transmitted. Next, the processing of S260 in FIG. 6 will be described in more detail. FIG. 8 shows a flowchart of an embodiment of the processing in S260.

 In step S2661, the clock slave switching to the clock master is requested to switch the clock mode using the clock switching request notification portion included in the cell transmitted at predetermined time intervals.

 Proceeding to step S262 following step S266, the control unit 5 determines whether a response cell has been received, and repeats the processing of S266 to S266 until reception of the response cell ( NO in S262). When the cell of the response is received (YES in S262), the process proceeds to step S263, and, for example, in the case of the functional unit A100, the clock switching units 3 and 4 are controlled and supplied to the transmitting unit 6. The clock is switched from the clock of the oscillator 2 to the clock extracted by the receiver 7.

By the way, the clock dominance level on the clock master side drops, When the clock dominance level on the slave side becomes the same, it seems better to switch the clock mode. This is because if the level becomes lower and the clock becomes the same, the mask clock has a high possibility of failure, and the reliability can be improved by switching the clock mode before the failure.

 In addition, in order to increase reliability, the cells shown in FIG. 4 used in the processing of the present invention are provided with protection of CRC (Cyclic Redundancy Check) 10 in the payload, and only normal cells are used in the CRC check. Thereby, the reliability can be improved. As described above, the clock master side and the master slave side can be automatically set, and when the master clock generated by the clock master deteriorates, the clock master side and the clock slave side can be automatically switched. It is possible. Therefore, it is possible to avoid incorrect settings on the clock master side or clock slave side, which are expected to occur at the time of debugging, etc. Even in a wide area or ATM network, quality due to clock stability deterioration can be reduced. Operation can be continued while avoiding deterioration and operation suspension.

The present invention is not limited to the above embodiments, and various modifications and changes can be made within the scope of the present invention.

The scope of the claims

 1. Comparing a first clock dominance level set for its own device with a second clock dominance level set for another device;

 determining, based on the result of the self-comparison, whether said own device or another device is suitable for a clock master device;

 Setting a self-device as a clock master device or a clock slave device according to the result of the determination.

2. The self-comparison step includes: transmitting the first clock superiority level to the other device using a cell;

 2. The clock setting method according to claim 1, further comprising the step of: transmitting the second clock dominance level to the own device by using a cell.

3. comparing the first clock dominance level set in the clock master device and the second clock dominance level set in the clock slave device every predetermined period;

 If it is determined that the second clock superiority level is more suitable for the clock master device than the first clock superiority level as a result of the self-comparison, the clock comprising the step of switching between the clock master device and the clock slave device Setting method.

4. comparing a first clock supplied from the clock master device with a second clock generated by the clock slave device itself;

 ji As a result of the self-comparison, when an abnormality is detected in the relationship between the m1 clock and the second clock, the abnormality is notified to the master device, and

 4. The clock setting method according to claim 3, further comprising, when the abnormality is notified from a plurality of clock slave devices, lowering a first clock superiority level of the own clock master device.

5. In the comparing, the first clock dominance level is previously determined using a cell. Transmitting to the clock slave device;

 4. The clock setting method according to claim 3, further comprising: transmitting the second clock superiority level to the master device using a cell by the clock slave device.

6. Switching between the clock master device and the clock slave device includes switching the clock slave device to a new clock master device, and switching the clock slave device to a new clock master device. The clock method according to claim 3, further comprising a step of switching the clock master device to a clock slave device.

7. The clock method according to claim 5, wherein, in the step of notifying the abnormality, the abnormality is transmitted to an ItJf self-clocking device using a cell.

8. superiority level comparing means for comparing the first clock superiority level set for the own device and the second clock superiority level set for other devices;

 Judging means based on the result of the comparison to judge whether the own device or another device is suitable for the clock master device;

 A communication device comprising: setting means for setting the own device as a clock master device or a clock slave device according to a result of the determination.

9. The superiority level comparing means includes: transmitting means for transmitting the first clock superiority level to the other device using a cell;

 9. The communication device according to claim 8, further comprising: detection means for detecting the second clock superiority level transmitted by the other device using a cell.

10. A superiority level comparing means for comparing the first clock superiority level set in the clock master device and the second clock superiority level set in the clock slave device at predetermined intervals, As a result of the comparison, when it is determined that the second clock dominance level is more suitable for the clock master device than the first clock dominance level, a communication device comprising switching means for switching between the clock master device and the clock slave device. apparatus.

11. A receiving means for receiving a comparison result between the first clock supplied from the clock master device and a second clock generated by the self-clock slave device, and a self-clock π for comparing the comparison result with the self-clock slave device. 10. The clock master device according to claim 10, further comprising: a superiority level changing unit configured to decrease the superiority level of the first clock of the clock master device when an abnormality is detected in a relationship between the clock and the second clock. Communication device.

1 2. the switching means, the first switching means for switching the clock slave device to a new clock mass device,

 10. The communication device according to claim 10, further comprising: a second switching means for switching the clock master device to a clock slave device after switching the clock slave device to a new clock master device.

1 3. The claim self-receiving means is provided by using the self-comparison result using a cell.

1 4. superiority level comparing means for comparing the first clock superiority level set in the clock master device and the second clock superiority levels respectively set in the plurality of clock slave devices at predetermined time intervals;

 As a result of the comparison, if it is determined that the second clock dominance level is more suitable for the clock master device than the first clock dominance level, the switching means for switching between the master clock device and one clock slave device A communication system comprising:

1 5. comparing means for comparing a first clock supplied from the clock master device with a second clock generated by the clock slave device;

As a result of the comparison, an abnormality is detected in the relationship between the first clock and the second clock. Notification means for notifying the clock mass setting device of an abnormality,

 15. The communication system according to claim 14, further comprising: a superiority level changing unit that reduces a first superiority level of the clock master device when the abnormality is notified from a plurality of clock slave devices. 16.

1 6. The switching means, if the first switching means for switching the own clock slave device to a new clock mass device,

 15. The communication system according to claim 14, further comprising a second switching unit that switches the clock master device to the clock slave device after switching the clock slave device to the new clock master device.