[go: up one dir, main page]

WO2001004770A3 - Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list - Google Patents

Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list Download PDF

Info

Publication number
WO2001004770A3
WO2001004770A3 PCT/US2000/018939 US0018939W WO0104770A3 WO 2001004770 A3 WO2001004770 A3 WO 2001004770A3 US 0018939 W US0018939 W US 0018939W WO 0104770 A3 WO0104770 A3 WO 0104770A3
Authority
WO
WIPO (PCT)
Prior art keywords
linked list
ram
index fifo
architecture
data throughput
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/018939
Other languages
French (fr)
Other versions
WO2001004770A2 (en
Inventor
Keith Lee
Dean Schmaltz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Altsystems Inc
Original Assignee
Alteon Websystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alteon Websystems Inc filed Critical Alteon Websystems Inc
Priority to AU59297/00A priority Critical patent/AU5929700A/en
Publication of WO2001004770A2 publication Critical patent/WO2001004770A2/en
Publication of WO2001004770A3 publication Critical patent/WO2001004770A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

A method and architecture for optimizing data throughput in a multiprocessor environment makes use of a RAM-based, shared index FIFO linked list, in which data to be processed is written to a central buffer and the index FIFO, constituting a linked list of indexes to the buffered data is passed between processing units within the system, providing a substantial reduction in the gate count required for processing the data. Messages are written to a central buffer; a linked list of indexes to the messages is created, and then pipelined to a processing unit as an index FIFO, so that the processor reads the entries of the linked list in sequence; as the entries are read, a message indicated by the entry is processed. Entries are enqueued and dequeued in an index FIFO RAM, so that enqueuing and dequeuing are performed in a single cycle with a single write operation.
PCT/US2000/018939 1999-07-13 2000-07-11 Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list Ceased WO2001004770A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU59297/00A AU5929700A (en) 1999-07-13 2000-07-11 Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14344599P 1999-07-13 1999-07-13
US60/143,445 1999-07-13

Publications (2)

Publication Number Publication Date
WO2001004770A2 WO2001004770A2 (en) 2001-01-18
WO2001004770A3 true WO2001004770A3 (en) 2001-08-30

Family

ID=22504112

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/018939 Ceased WO2001004770A2 (en) 1999-07-13 2000-07-11 Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list

Country Status (2)

Country Link
AU (1) AU5929700A (en)
WO (1) WO2001004770A2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6941386B2 (en) 1997-10-14 2005-09-06 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6996070B2 (en) 2003-12-05 2006-02-07 Alacritech, Inc. TCP/IP offload device with reduced sequential processing
US7185266B2 (en) 2003-02-12 2007-02-27 Alacritech, Inc. Network interface device for error detection using partial CRCS of variable length message portions
US7461160B2 (en) 1997-10-14 2008-12-02 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US7627684B2 (en) 1997-10-14 2009-12-01 Alacritech, Inc. Network interface device that can offload data transfer processing for a TCP connection from a host CPU

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6658480B2 (en) 1997-10-14 2003-12-02 Alacritech, Inc. Intelligent network interface system and method for accelerated protocol processing
US6687758B2 (en) 2001-03-07 2004-02-03 Alacritech, Inc. Port aggregation for network connections that are offloaded to network interface devices
US6427171B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6427173B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Intelligent network interfaced device and system for accelerated communication
US7133940B2 (en) 1997-10-14 2006-11-07 Alacritech, Inc. Network interface device employing a DMA command queue
US7237036B2 (en) 1997-10-14 2007-06-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding a TCP connection
US7076568B2 (en) 1997-10-14 2006-07-11 Alacritech, Inc. Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket
US8782199B2 (en) 1997-10-14 2014-07-15 A-Tech Llc Parsing a packet header
US7042898B2 (en) 1997-10-14 2006-05-09 Alacritech, Inc. Reducing delays associated with inserting a checksum into a network message
US6389479B1 (en) 1997-10-14 2002-05-14 Alacritech, Inc. Intelligent network interface device and system for accelerated communication
US7284070B2 (en) 1997-10-14 2007-10-16 Alacritech, Inc. TCP offload network interface device
US7174393B2 (en) 2000-12-26 2007-02-06 Alacritech, Inc. TCP/IP offload network interface device
US6807581B1 (en) 2000-09-29 2004-10-19 Alacritech, Inc. Intelligent network storage interface system
US6226680B1 (en) 1997-10-14 2001-05-01 Alacritech, Inc. Intelligent network interface system method for protocol processing
US7089326B2 (en) 1997-10-14 2006-08-08 Alacritech, Inc. Fast-path processing for receiving data on TCP connection offload devices
US7167927B2 (en) 1997-10-14 2007-01-23 Alacritech, Inc. TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism
US8019901B2 (en) 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
US7496689B2 (en) 2002-04-22 2009-02-24 Alacritech, Inc. TCP/IP offload device
US7543087B2 (en) 2002-04-22 2009-06-02 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device
US7337241B2 (en) 2002-09-27 2008-02-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US7191241B2 (en) 2002-09-27 2007-03-13 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
DE10360637B4 (en) * 2003-12-19 2010-10-07 Infineon Technologies Ag Program controlled unit
US8539513B1 (en) 2008-04-01 2013-09-17 Alacritech, Inc. Accelerating data transfer in a virtual computer system with tightly coupled TCP connections
US8341286B1 (en) 2008-07-31 2012-12-25 Alacritech, Inc. TCP offload send optimization
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies
EP2282264A1 (en) * 2009-07-24 2011-02-09 ProximusDA GmbH Scheduling and communication in computing systems
CN109558107B (en) * 2018-12-04 2023-06-30 中国航空工业集团公司西安航空计算技术研究所 FC message receiving management method for shared buffer area

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551242A2 (en) * 1992-01-10 1993-07-14 Digital Equipment Corporation Multiprocessor buffer system
US5339418A (en) * 1989-06-29 1994-08-16 Digital Equipment Corporation Message passing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339418A (en) * 1989-06-29 1994-08-16 Digital Equipment Corporation Message passing method
EP0551242A2 (en) * 1992-01-10 1993-07-14 Digital Equipment Corporation Multiprocessor buffer system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IAN M. LESLIE, DEREK MCAULEY, RICHARD BLACK, TIMOTHY ROSCOE, PAUL BARHAM, DAVID EVERS, ROBIN FAIRBAIRNS, EOIN HYDEN: "The Design and Implementation of an Operating System to Support Distributed Multimedia Applications", IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, vol. 14, no. 7, September 1996 (1996-09-01), pages 1280 - 1296, XP000626277 *
PHILIP BUONADONNA <PHILIPB@CS.BERKELEY.EDU>, ADREW GEWKE <GEWEKE@CS.BERKELEY.EDU>, DAVID CULLER <CULLER@CS.BERKELEY.EDU>: "An Implementation and Analysis of the Virtual Interface Architecture", INTERNET DOCUMENT, November 1998 (1998-11-01), XP002156218, Retrieved from the Internet <URL:http://www.cs.berkeley.edu/~philipb/papers/SC98/sc98_html/index.htm> [retrieved on 20001219] *
THORSTEN VON EICKEN, ANINDYA BASU, VINEET BUCH, WERNER VOGELS: "U-NET: A USER-LEVEL NETWORK INTERFACE FOR PARALLEL AND DISTRIBUTED COMPUTING", OPERATING SYSTEMS REVIEW (SIGOPS),US,ACM HEADQUARTER. NEW YORK, vol. 29, no. 5, 1 December 1995 (1995-12-01), pages 40 - 53, XP000584816 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6941386B2 (en) 1997-10-14 2005-09-06 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US7461160B2 (en) 1997-10-14 2008-12-02 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US7584260B2 (en) 1997-10-14 2009-09-01 Alacritech, Inc. Method to synchronize and upload an offloaded network stack connection with a network stack
US7620726B2 (en) 1997-10-14 2009-11-17 Alacritech, Inc. Zero copy method for receiving data by a network interface
US7627001B2 (en) 1997-10-14 2009-12-01 Alacritech, Inc. Protocol stack that offloads a TCP connection from a host computer to a network interface device
US7627684B2 (en) 1997-10-14 2009-12-01 Alacritech, Inc. Network interface device that can offload data transfer processing for a TCP connection from a host CPU
US7185266B2 (en) 2003-02-12 2007-02-27 Alacritech, Inc. Network interface device for error detection using partial CRCS of variable length message portions
US6996070B2 (en) 2003-12-05 2006-02-07 Alacritech, Inc. TCP/IP offload device with reduced sequential processing

Also Published As

Publication number Publication date
WO2001004770A2 (en) 2001-01-18
AU5929700A (en) 2001-01-30

Similar Documents

Publication Publication Date Title
WO2001004770A3 (en) Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list
US8230180B2 (en) Shared memory burst communications
US11392529B2 (en) Systems and method for mapping FIFOs to processor address space
TW200610341A (en) Network interface with security association data prefetch for high speed offloaded security processing
US20030159078A1 (en) Techniques for facilitating conversion between asynchronous and synchronous domains
CA2414438A1 (en) System and method for semaphore and atomic operation management in a multiprocessor
EP0792081A3 (en) A system and method for an efficient ATM adapter/device driver interface
WO2003003256A3 (en) System, method and computer program product for storing data in a databa using a multi-thread shared memory message queue buffer
DE602004011638D1 (en) Reduce buffering requirements in a messaging system
US20210303346A1 (en) System and method for queuing commands in a deep learning processor
CN113821457B (en) High-performance read-write linked list caching device and method
RU2007108065A (en) METHOD AND DEVICE FOR READING MEMORY OF COMMUNICATION MODULE MESSAGES
CN116483441B (en) Output time sequence optimizing system, method and related equipment based on shift buffering
CN111274171B (en) Data transmission device and method
CA2585295A1 (en) System and method for synchronous processing of media data on an asynchronous processor
TR200003134T2 (en) Method of processing receiver / decoder and video data
US20140195746A1 (en) Dma channels
Kaufman et al. A 3-D cellular frame buffer
US8125489B1 (en) Processing pipeline with latency bypass
CN109840241A (en) A kind of internuclear communicating circuit of heterogeneous dual-core processor
CN106911715B (en) A kind of communication control unit and communication control method separating Read-write Catrol
EP2696280B1 (en) Method and device for data transmission between register files
CN114399034B (en) Data handling method for direct memory access device
CN120179576B (en) A low-power FIFO module
CN118839097B (en) Matrix transposition unit, computing device, matrix transposition method and medium

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP