WO2001099175A1 - Connector surface for sublithographic semiconductor structures and method for production thereof - Google Patents

Abstract

The invention relates to a connector surface for sublithographic semiconductor structures (ST) and a method for production thereof. The connector surface (AF) essentially comprises a contact-surface section (KR) for producing an electrical contact with the sublithographic semiconductor structure (ST) and at least one insulating protective-surface section (SF) which borders the contact-surface section (KF). By increasing the size of the connector surface (AF) a protection from the layers (3) lying underneath can also be reliably guaranteed in the case of a maladjustment of the photo-lithographic process.

Description

description

Connection surface for sub-lithographic .Semiconductor structures and method for their production

The invention relates to a connection area for sub-lithographic semiconductor structures and a method for their production, and in particular to a connection area for sub-lithographic vertical field effect transistors.

Since a minimum structure size of highly integrated circuits is limited in particular by the photolithographic processes and predetermined etching techniques used, sublithographic methods for the production of semiconductor structures are increasingly used which enable a structure size below that of photolithographic minimal structures.

FIG. 2 shows a simplified sectional view of such a sublithographic semiconductor structure according to the prior art, in which a so-called “SGT field effect transistor” is formed on a step in a p-doped semiconductor substrate 10, for example. A n ⁺ -doped source region S is located in an upper section of the semiconductor substrate 10 to the left of the

Level, while an, for example, n ⁺ -doped drain region D is to the right of it. A channel length K _{L of} a channel region K formed at the step or between the source region S and the drain region D is essentially determined by a step depth in the semiconductor substrate 10 and a

Layer thickness of a gate connection G is defined, which gives structure sizes below photolithographically realizable structure sizes. The conventional sublithographic field effect transistor shown in FIG. 2 is usually also referred to as an implantation FET. Figure 3 shows another conventional sublithographic field effect transistor or so-called "epi" FET wherein the channel length K _is determined essentially by an epitaxially grown layer for the channel region K. The illustrated in Figure 3 "epi" field effect transistor, for example, by be surrounded by two gate connections G, which results in a vertical double field effect transistor. The source region S is located on an upper section of a semiconductor fin exposed from the epitaxially grown layer, while a drain region D is located in the lower region of the semiconductor fin in the semiconductor substrate 10. Using sublithographic methods, the width B _{LP of} the semiconductor land (“landing pads”) can be reduced significantly below the minimum structure size of a lithographic method, which results in a particularly high integration density. In addition, since the channel length K _L only depends on the Depending on the epitaxially grown layer thickness, field effect transistors with further reduced structure sizes and improved characteristic properties are obtained. However, the disadvantage of such sublithographic semiconductor structures is in particular the realization of a connection pad (“landing pad”), in particular for the upper part of the semiconductor bridge. Since contacting is usually carried out using conventional photographic methods and exact placement of a contact is very difficult due to adjustment and manufacturing tolerances, a major problem with sublithographic semiconductor structures is the implementation of a reliable connection area.

FIG. 4 shows a simplified sectional view of a connection area for sublithographic semiconductor structures according to the prior art, as described, for example, from the reference “JM Hergenrother et al. , Bell Labs, "The vertical replacement-gate (VRG) MOSFET: a 50-nm vertical MOSFET with litography-independent gatelength", IEDM, 1999 ". According to FIG. 4, a semiconductor substrate 10 consists of a multiplicity of different semiconductor and insulation layers, into which a trench is made. A plurality of semiconductor layers are epitaxially grown to form a drain region D, a channel region K and a source region S. A further large number of layers are then applied and structured using a photolithographic process as a connection area with a width B _LP . A part of the middle layers is removed up to the sublithographic semiconductor structure consisting of the drain region D, the channel region K and the source region S and filled up again with gate connections G. In this way, a connection area AF is obtained for sublithographic semiconductor structures with a structure width B _{P that is} sufficiently large for photolithographic processes. Adjustment and manufacturing tolerances in both the lithography and the etching process can be compensated for, which results in a reliably functioning sublithographic semiconductor structure. However, the disadvantage of such a conventional connection area is the extraordinarily high production outlay and the complex substrate structure, which are reflected in increased costs.

The invention is therefore based on the object of providing a connection area for sublithographic semiconductor structures and a method for their production which enables simplified contacting with reduced costs and with increased reliability of the semiconductor structure.

According to the invention, this object is achieved with regard to the connection area by the features of patent claim 1 and with regard to the method by the measures of patent claim 5. In particular, by using at least one insulating protective surface section, which adjoins a contact surface section of the sublithographic semiconductor structure, a sufficient enlargement of the connection area is obtained to compensate for adjustment errors as well as adequate protection of layers underneath for subsequent etching processes, in particular for forming contact holes. In this way, both the etching process window and the adjustment tolerances in the methods used can be defused, which reduces the manufacturing costs and improves the yield.

Particularly when a vertical field effect transistor is implemented as a sublithographic semiconductor structure, an extraordinarily high integration density is obtained for the associated integrated circuits. To separate the source, channel and drain regions, the substrate can in this case have at least one barrier layer for realizing a potential barrier, a diffusion, tunnel and / or a hetero barrier being realized. In this way, vertical field effect transistors with particularly low leakage currents are obtained, which can also be dimensioned particularly simply and precisely using the barrier layers as etch stop layers.

In particular, by forming a first insulation layer on the surface of the remaining substrate using an insulation mask, improved high-frequency display shafts are obtained for the sublithographic semiconductor structure, since a connection to the semiconductor structure guided in the semiconductor substrate better moves from a connection formed on the semiconductor substrate to Can decouple semiconductor structure. When a vertical field effect transistor, for example, is implemented, a gate connection can be capacitively decoupled from a drain connection. By forming at least one insulating protective layer that at least partially fills up an exposed electrically conductive layer used for the gate connection, a particularly simple and extremely reliable method for producing a connection area for a vertical field effect transistor with a sublithographic structure size is obtained. Both the etching tolerance for the etching back of the electrically conductive layer serving as the gate connection and the adjustment tolerances for the connection surfaces can thereby be significantly improved.

Further advantageous refinements of the invention are characterized in the further subclaims.

The invention is described below with reference to an exemplary embodiment with reference to the drawing.

Show it:

FIGS. 1A to 1P simplified sectional views for illustrating method steps according to the invention for producing a connecting layer for sublithographic semiconductor structures;

Figure 2 is a simplified sectional view of a conventional sublithographic semiconductor structure;

FIG. 3 shows a simplified sectional view of a further sublithographic semiconductor structure; and

FIG. 4 shows a simplified sectional view of a conventional sublithographic semiconductor structure with an improved connection area.

FIGS. 1A to 1P show simplified sectional views to illustrate the respective steps in the production of a connection area for a sublithographic tical field effect transistor according to the present invention. The representation of the figures is not to scale here.

According to FIG. 1A, a semiconductor substrate 1 is first coated with a mask layer (not shown), and active areas are structured by, for example, shallow trench isolation (STI). According to FIGS. 1A to 1P, the substrate 1 consists of a sequence of epitaxially deposited layers, such as e.g. a doped silicon layer, a first barrier layer B, an undoped silicon layer, a second barrier layer B and a further doped silicon layer. However, the substrate 1 can also consist of another material and in particular have no barrier layers B. For example, only a PNP or NPN layer sequence can be formed.

The barrier layers B shown in FIG. 1A essentially serve to separate source, channel and drain regions of a vertical field effect transistor to be formed. With such a vertical field effect transistor, they can serve as potential barriers or as etch stop layers and act as diffusion and / or hetero barriers. The barrier layers B can consist of SiGe or SiC, for example. To produce a tunnel transistor, the barrier layers B could also act as tunnel barriers and, for example, consist of Si0 ₂ or Si ₃ N ₄ . However, all other materials for the barrier layers B are also conceivable.

The outer silicon layers of the substrate 1 represent inner source / drain electrodes or regions. The inner or middle silicon layer essentially serves to implement an actual channel region and can also be undoped, for example, since the threshold voltage of the transistor is later determined by the Work function of the gate material can be put. Subsequently, a first mask layer is Ml formed on the semiconductor substrate 1, the esentlichen in _W is used as an auxiliary layer for making a subsequent sub-lithographic mask. The first mask layer M1 consists, for example, of a deposited TEOS layer, but can also have any further mask layer.

According to FIG. 1B, a step is etched into the substrate 1 using the first mask layer M1 and then a second mask layer M2 with a small thickness is formed. The second mask layer M2 consists, for example, of a nitride layer and, by virtue of its thickness, defines the width of a later substrate web or the sublithographic semiconductor structure.

According to FIG. IC, the second mask layer M2 is etched back, for example by means of an anisotropic etching process, as a result of which a “nitride spacer” or a structural mask M2 remains on the first mask layer Ml. An anisotropic dry etching is preferably carried out here. The first mask layer or TEOS layer Ml subsequently preferably etched back by wet chemistry, so that only the “nitride spacer” shown in FIG. IC or the structure mask M2 remains.

According to FIG. 1D, this free-standing “nitride spacer” or this remaining part of the second mask layer M2 now serves as an etching mask in order to structure the entire substrate layer stack or the substrate 1. The lower barrier layer B is used, for example, as an etching stop layer, which means 1D, the upper part of the substrate web ST forms a source region S, a central part a channel region K and a region lying in the remaining substrate 1 a drain region D of the vertical sublithographic field effect transistor. ω t t- μ »μ- cπ σ LΠ o LΠ σ l-π

rr φ

P

Ω

Mr.

Φ

P

2 cn o er d ω cn

N d

Φ ι- (

3

O:

⁽ Q

I--

H- n ^*

Φ

P

H

P cn er

Φ

cfl

0

P o.

Φ

Φ

H-

Φ

K o

0 ⁴

Hl tl φ

1

The overall characteristics of a vertical transistor are thereby significantly improved. The “nitride spacers” or protective masks M3 and structure mask M2 are then completely removed, so that the substrate web or the sub-lithographic semiconductor structure ST is again free.

According to FIG. 1H, a second insulation layer 2 is then formed. This second insulation layer 2 is preferably grown as a high-quality gate dielectric, silicon dioxide preferably being used as the gate dielectric.

In a subsequent step, as shown in FIG. II, a first electrically conductive layer 3 is formed over the entire surface of the remaining substrate 1 or the second insulation layer 2. This electrically conductive layer 3 preferably consists of gate material made of polysilicon or SiGe and is formed in a deposition process.

According to FIG. IJ, a first insulating protective layer 4 is deposited over the entire area on the first electrically conductive layer 3 or on the sublithographic semiconductor structure. The first insulating protective layer 4 consists, for example, of a nitride layer, but can also consist of any further insulating layer which, together with the substrate 1, can serve as an etching stop layer for a later etching process.

First, however, in a further method step according to FIG. 1C, the first insulating protective layer 4 is etched back to a spacer, so that the first electrically conductive layer 3 or the gate material is partially exposed. The resulting spacer 4 also protects the vertical side walls of the electrically conductive layer 3 or the gate material, which is necessary for the subsequent step of

Meaning is. ÜJ U) tt μ> H- ¹ cn o in o t-π O ι-π

X

P

H he

H-"

Φ μ- rr

Φ

H cn rr

Φ Q er

N

≤

•

di

P cn to

O d

H

Ω

Φ

IQ °

Μ he μ-

Φ rr cn

N d

<

Φ

P- cn cn μ- tQ -

O

Mr.

P

1

tiert without short-circuiting the underlying electrically conductive layer 3 or the gate.

To complete the connection area, a contact hole insulation layer 6 is then formed according to FIG. IN, which consists, for example, of a thick TEOS layer. The contact hole insulation layer 6 is then planarized by means of a chemical mechanical polishing method (CMP, chemical mechanical polishing). Typically, the height of the contact hole insulation layer 6 made from TEOS is approximately 500 nm to 1 micrometer, while the ridge height of the sublithographic semiconductor structure ST is only approximately 300 nm.

In a subsequent step according to FIG. 10, the contact hole insulation layer 6 is structured by means of a conventional photolithographic method, as a result of which the connection areas AF are defined for the sublithographic semiconductor structure ST. A so-called contact hole etching then takes place, which selectively stops both on the substrate material of the source region S and on the first and second insulating protective layers 4 and 5. As a result, contact holes for the source region S, the gate layer 3 and the drain region D are exposed in a self-adjusting manner up to different contact planes.

In this way, in the case of the sublithographic semiconductor structure ST, a contact surface section KF and adjoining insulating protective surface sections SF are also exposed, which is why there is no risk of a short circuit with layers underneath even in the event of severe misalignment in the photolithographic process.

Finally, according to FIG. 1P, a second electrically conductive layer 7 is formed in the exposed contact holes, as a result of which the source region S, the first electrically conductive gate layer 3 and the drain region D are electrically conductive. getting closed. On the basis of the first insulation layer 10 optionally produced according to FIGS. 1E to IG, a capacitive coupling between the gate or first electrically conductive layer 3 and the drain region D or drain connection in the substrate 1 can accordingly be reduced.

The invention has been described above using a sublithographic vertical field effect transistor. However, it is not restricted to this and rather relates to all sublithographic semiconductor structures which have to be contacted at least on an upper side. According to the present invention, first and second insulating protective layers have been formed around the semiconductor structure. However, several insulating protective layers or only one protective layer can also be used. In the same way, different materials can be used for the insulating protective layers, provided that they have essentially the same selective etch stop property for contact hole etching.

Claims

claims 1. Connection surface for sublithographic semiconductor structures with a contact surface section (KF) for realizing an electrical contact with the sublithographic semiconductor structure (ST) and at least one insulating protective surface section (SF) which adjoins the contact surface section (KF) for implementation an enlargement of the connection area (AF) and an etching protection of layers (3) underneath. 2. Connection area according to claim 1, so that the sublithographic semiconductor structure (ST) represents a vertical field effect transistor with a source region (S), a channel region (K) and a drain region (D). 3. Connection surface according to claim 1 or 2, so that the contact surface section (KF) and the insulating protective surface section (SF) essentially represent a common etching stop layer for a selected etchant. 4. Pad according to one of the claims 1 to 3, characterized in that the contact surface section (KF) Si and the protective surface section (SF) Si ₃ N ₄ . 5. A method for producing a connection area for sublithographic semiconductor structures, comprising the steps: a) forming the sublithographic semiconductor structures (ST) with a contact surface section (KF) to be contacted from a substrate (1); b) forming at least one insulating protective layer (4, 5); c) removing the insulating protective layer (4, 5) essentially up to a level of the contact surface section (KF) to form at least one adjacent protective surface section (SF); d) forming a contact hole insulation layer (6); e) photolithographic structuring of the contact hole insulation layer (6) for fixing the connection area (AF); and f) etching the contact hole insulation layer (6) to expose the connection area (AF) for the sublithographic Semiconductor structures (ST). 6. The method as claimed in claim 5, so that the substrate (1) has at least one barrier layer (B) for realizing a potential barrier. 7. The method as claimed in claim 6, so that the barrier layer (B) represents a diffusion, tunnel and / or a hetero barrier. 8. The method as claimed in one of claims 5 to 7, that the formation of the sublithographic semiconductor structure (ST) in step a) al) forms a step in the substrate (1); a2) forming a structure mask (M2), the thickness of which defines the width of the sublithographic semiconductor structure (ST); and a3) removing at least a part of the substrate (1) using the structure mask (M2). 9. The method according to any one of claims 5 to 8, d a d u r c h g e k e n n z e i c h n e t that after Step a) the steps: aal) forming a protective mask (M3) on the semiconductor structure (ST), aa2) forming a first insulation layer (10) on the surface of the substrate (1) using the protective mask (M3); and aa3) removing the protective mask (M3); be performed. 10. The method according to any one of claims 5 to 9, that the sublithographic semiconductor structures (ST) represent vertical field effect transistors and before step b) the step Forming an electrically conductive layer (3) is carried out as a gate layer. 11. The method according to claim 10, d a d u r c h g e k e n n z e i c h n e t that in the Steps b) and c) bl) forming a first insulating protective layer (4); cl) a partial removal of the first insulating protective layer (4) to partially expose the electrically conductive Layer (3); zl) a partial removal of the electrically conductive Layer (3) for exposing at least the contact surface section (KF); b2) forming a second insulating protective layer (5); and c2) partial removal of the second insulating Protective layer (5) is carried out.