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WO2001099169A3 - Etch stop layer system for sige devices - Google Patents

Etch stop layer system for sige devices Download PDF

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Publication number
WO2001099169A3
WO2001099169A3 PCT/US2001/019613 US0119613W WO0199169A3 WO 2001099169 A3 WO2001099169 A3 WO 2001099169A3 US 0119613 W US0119613 W US 0119613W WO 0199169 A3 WO0199169 A3 WO 0199169A3
Authority
WO
WIPO (PCT)
Prior art keywords
etch
stop layer
etch stop
layer system
sige
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/019613
Other languages
French (fr)
Other versions
WO2001099169A2 (en
Inventor
Kenneth C Wu
Eugene A Fitzgerald
Jeffrey T Borenstein
Gianna Taraschi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Massachusetts Institute of Technology
Original Assignee
Massachusetts Institute of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/599,260 external-priority patent/US6689211B1/en
Application filed by Massachusetts Institute of Technology filed Critical Massachusetts Institute of Technology
Priority to JP2002503924A priority Critical patent/JP2003536273A/en
Priority to EP01946546A priority patent/EP1295319A2/en
Priority to AU2001268577A priority patent/AU2001268577A1/en
Publication of WO2001099169A2 publication Critical patent/WO2001099169A2/en
Publication of WO2001099169A3 publication Critical patent/WO2001099169A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10P50/644—
    • H10P90/1922—
    • H10W10/181—

Landscapes

  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1-xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material.
PCT/US2001/019613 2000-06-22 2001-06-20 Etch stop layer system for sige devices Ceased WO2001099169A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002503924A JP2003536273A (en) 2000-06-22 2001-06-20 Etch stop layer system
EP01946546A EP1295319A2 (en) 2000-06-22 2001-06-20 Etch stop layer system for sige devices
AU2001268577A AU2001268577A1 (en) 2000-06-22 2001-06-20 Etch stop layer system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/599,260 2000-06-22
US09/599,260 US6689211B1 (en) 1999-04-09 2000-06-22 Etch stop layer system

Publications (2)

Publication Number Publication Date
WO2001099169A2 WO2001099169A2 (en) 2001-12-27
WO2001099169A3 true WO2001099169A3 (en) 2002-04-25

Family

ID=24398918

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/019613 Ceased WO2001099169A2 (en) 2000-06-22 2001-06-20 Etch stop layer system for sige devices

Country Status (4)

Country Link
EP (1) EP1295319A2 (en)
JP (1) JP2003536273A (en)
AU (1) AU2001268577A1 (en)
WO (1) WO2001099169A2 (en)

Cited By (14)

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US6864115B2 (en) 2000-01-20 2005-03-08 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7259108B2 (en) 2002-03-14 2007-08-21 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7348259B2 (en) 2001-04-04 2008-03-25 Massachusetts Institute Of Technology Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy

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US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
WO2001093338A1 (en) 2000-05-26 2001-12-06 Amberwave Systems Corporation Buried channel strained silicon fet using an ion implanted doped layer
JP2004507084A (en) 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー Manufacturing process of semiconductor products using graded epitaxial growth
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
EP1364411A1 (en) * 2001-03-02 2003-11-26 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
WO2002103760A2 (en) 2001-06-14 2002-12-27 Amberware Systems Corporation Method of selective removal of sige alloys
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
WO2003001671A2 (en) 2001-06-21 2003-01-03 Amberwave Systems Corporation Improved enhancement of p-type metal-oxide-semiconductor field-effect transistors
JP2004538634A (en) 2001-08-06 2004-12-24 マサチューセッツ　インスティテュート　オブ　テクノロジー Semiconductor substrate having strained layer and method for forming the same
US7138649B2 (en) 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7138310B2 (en) 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
WO2003105206A1 (en) 2002-06-10 2003-12-18 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
FR2842349B1 (en) 2002-07-09 2005-02-18 TRANSFERRING A THIN LAYER FROM A PLATE COMPRISING A BUFFER LAYER
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
FR2842350B1 (en) * 2002-07-09 2005-05-13 METHOD FOR TRANSFERRING A LAYER OF CONCEALED SEMICONDUCTOR MATERIAL
US7018910B2 (en) 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US7781850B2 (en) * 2002-09-20 2010-08-24 Qualcomm Mems Technologies, Inc. Controlling electromechanical behavior of structures within a microelectromechanical systems device
DE10260860B4 (en) * 2002-12-23 2008-07-10 Robert Bosch Gmbh Layer of Si1-xGex, process for their preparation and micromechanical device with it
US6808953B2 (en) * 2002-12-31 2004-10-26 Robert Bosch Gmbh Gap tuning for surface micromachined structures in an epitaxial reactor
JP4585510B2 (en) 2003-03-07 2010-11-24 台湾積體電路製造股▲ふん▼有限公司 Shallow trench isolation process
US7176041B2 (en) * 2003-07-01 2007-02-13 Samsung Electronics Co., Ltd. PAA-based etchant, methods of using same, and resultant structures
US7495266B2 (en) 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
TWI283442B (en) * 2004-09-09 2007-07-01 Sez Ag Method for selective etching
FR2892733B1 (en) * 2005-10-28 2008-02-01 Soitec Silicon On Insulator RELAXATION OF LAYERS
KR101316947B1 (en) 2005-11-01 2013-10-15 메사추세츠 인스티튜트 오브 테크놀로지 Monolithically integrated semiconductor materials and devices
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
DE102010042570B4 (en) 2010-10-18 2012-07-26 Jörg Funke Folding and partially dismountable bicycle
US9093478B1 (en) 2014-04-11 2015-07-28 International Business Machines Corporation Integrated circuit structure with bulk silicon FinFET and methods of forming
US9842913B1 (en) 2016-05-18 2017-12-12 Globalfoundries Inc. Integrated circuit fabrication with boron etch-stop layer
FR3064398B1 (en) * 2017-03-21 2019-06-07 Soitec SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, ESPECIALLY FOR A FRONT-SIDE TYPE IMAGE SENSOR, AND METHOD FOR MANUFACTURING SUCH STRUCTURE
JP7668626B2 (en) * 2019-10-04 2025-04-25 東京応化工業株式会社 Etching solution and method for manufacturing semiconductor device
FR3125631B1 (en) * 2021-07-23 2025-01-31 Commissariat Energie Atomique METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE OF THE SOI OR SIGEOI TYPE BY NEED AND STRUCTURE FOR MANUFACTURING SUCH A SUBSTRATE
JP2024160726A (en) * 2023-05-02 2024-11-15 株式会社Ｓｃｒｅｅｎホールディングス Substrate processing method

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WO1999053539A1 (en) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Silicon-germanium etch stop layer system
US6059895A (en) * 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator

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US6059895A (en) * 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator
WO1999053539A1 (en) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Silicon-germanium etch stop layer system

Non-Patent Citations (3)

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Title
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6864115B2 (en) 2000-01-20 2005-03-08 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
US7501351B2 (en) 2001-03-02 2009-03-10 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7348259B2 (en) 2001-04-04 2008-03-25 Massachusetts Institute Of Technology Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US7259108B2 (en) 2002-03-14 2007-08-21 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7375385B2 (en) 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups
US7368308B2 (en) 2002-08-23 2008-05-06 Amberwave Systems Corporation Methods of fabricating semiconductor heterostructures
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures

Also Published As

Publication number Publication date
AU2001268577A1 (en) 2002-01-02
JP2003536273A (en) 2003-12-02
WO2001099169A2 (en) 2001-12-27
EP1295319A2 (en) 2003-03-26

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