WO2001097380A1

WO2001097380A1 - Apparatus and circuit having reduced leakage current and method therefor

Info

Publication number: WO2001097380A1
Application number: PCT/US2001/017839
Authority: WO
Inventors: Kimberley Velarde; Lawrence Clark
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2000-06-12
Filing date: 2001-06-01
Publication date: 2001-12-20
Anticipated expiration: 2002-12-12
Also published as: CN1236560C; JP2009207178A; KR20030022816A; TW501278B; KR100551143B1; AU2001265321A1; CN1446403A; JP2004503948A

Abstract

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor.

Description

APPARATUS AND CIRCUIT HAVING REDUCED LEAKAGE CURRENT AND

METHOD THEREFOR BACKGROUND

Advances in manufacturing techniques have allowed transistors to be made with ever ever smaller geometries. For example, photolithographic and etch techniques have improved to the point where transistors with a gate length of 0.25 microns ((m) may be made. Decreasing the size of transistors is generally perceived to be beneficial because this may allow more transistors to be made within the same amount of area on a semiconductor die.

However, as the gate length of a transistor is reduced, the distance between the current carrying electrodes (e.g., source and drain terminals) may also be proportionately reduced. Consequently, the amount of semiconductor material between these terminals and beneath the gate of the transistor, often referred to as a channel or body region, may be reduced. As the length of the channel region of a transistor is reduced, the electric field of the drain terminal may have a greater effect upon the flow of current in the channel region. Thus, reductions in channel length, may make it more difficult to control the flow of current across the channel region between the source and drain terminals and lead to an increase in the amount of source-to-drain leakage (e.g., off-state current).

Techniques to address this leakage current may involve the use of halo implants around the current carrying electrodes. However, such techniques often involve additional manufacturing steps that increase the complexity and cost of the manufacturing process. Thus, there is a continuing need to reduce the leakage current between the current carrying electrodes of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 is a schematic representation of two transistors and a circuit in accordance with an embodiment the present invention;

FIG. 2 is a schematic representation illustrating circuits that may be used in accordance with various embodiments of the present invention; FIG. 3 is a schematic representation of voltage generators in accordance with various embodiments of the present invention; and

FIG. 4 is a schematic representation of a voltage generator in accordance with an alternative embodiment of the present invention.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. Note, in this description a "#" symbol is used to indicate the logical complement of a signal. For example, if BL is a logic "1," then BL# is a logic "0," although this invention is not limited to any particular signaling scheme.

Turning to FIG. 1, an embodiment 100 in accordance with the present invention is described. Embodiment 100 may comprise a portable device such as a mobile communication device (e.g., cell phone), a portable computer, or the like. Although it should be understood that the scope of the present invention is in no way limited to these applications.

Embodiment 100 includes an integrated circuit 10 that may comprise, for example, a microprocessor, a digital signal processor, a microcontroller, a memory array, such as static random access memory (SRAM), or the like. However, it should be understood that the scope of the present invention is not limited to these examples. Integrated circuit 10 may comprise transistors 20 and 30 fabricated in a substrate 15, such as silicon, although the scope of the present invention is not limited in this respect. Transistors 20 and 30 may include a gate electrode 23 and 33 that may be used to modulate a current flow across channel regions 24 and 34, respectively, while transistors 20 and 30 are in operation. Although not intended as a limitation of the scope of the present invention, channel region 24 may include the portion of substrate 15 where current flows between the current carrying electrodes 21-22 of transistor 20. Additionally, channel region 34 may comprise N-type well 35 where current flows between current carrying electrodes 31-32 of transistor 30. Generally stated, channel regions 24 and 34 are the portions of transistors 20 and 30 under gates 23 and 33 between current carrying electrodes 21-22 and 31-32, respectively. Channel regions 24 and 34 may also be referred to as body regions by those skilled in the art. In one embodiment, transistor 30 may comprise a p-channel transistor formed in an N-well region 35 while transistor 20 may comprise a n-channel transistor formed in a p-type substrate 15. This arrangement may be desirable if integrated circuit 10 may comprise a complementary metal-oxide semiconductor (CMOS) circuit. However, it should be understood that the scope of the present invention is not limited by the electrical characteristics of transistors 20 and 30 or by the type of material in which transistors 20 and 30 may be formed. For example, in alternative embodiments, the use of well region 35 may be optional and substrate 15 may comprise a variety of materials such as epitaxial layers, field oxide regions, etc. For example, transistors 20 and 30 may be fabricated with twin-wells, or a P-well in an N-type substrate. Furthermore, substrate 15 need not comprise silicon as other semiconductor materials may be used, such as semiconductor- on-insulator (SOI), etc.

Transistors 20 and 30 illustrate one example of how embodiments of the present invention may be used to reduce the leakage current of integrated circuit 10 when all or some of the transistors of integrated circuit 10 are in a non-conducting mode (e.g., at least some of the transistors are in an inactive mode and do not have a substantial voltage potential driven onto their gate terminals). Two transistors are shown in FIG. 1 so as not to obscure the present invention. It should be understood that integrated circuit 10 may comprise any number of transistors or sub-circuits. In the following description, a circuit or sub-circuit generally refers to a plurality of transistors, for example two or more.

However, it should be understood that a single transistor may be a circuit or sub-circuit. In addition, in some embodiments, a circuit may refer to the voltage level or logic signal provided by a node of another circuit or bonding pad.

In this particular embodiment, three voltage potentials, such as Vsssup voltage potential 40, Veep voltage potential 41, and Vcc voltage potential 42 may be selectively applied to portions of transistors 20 and 30 to reduce the leakage across channel regions 24 and 34. As shown in FIG. 1, voltage potentials 40-42 may be provided by pads that may be connected to power supplies that are external to integrated circuit 10. However, this is not intended as a limitation of the scope of the present invention as voltage potentials 40-42 may be provided from power supplies located within integrated circuit 10 (e.g. from charge pumps or voltage dividers). Furthermore, in other embodiments, voltage potentials 40-42 may represent the voltage potential provided by the nodes of another circuit (not shown) or from other portions of integrated circuit 10.

As indicated in FIG. 1, a voltage potential (e.g., Vsssup 40) may be applied to channel region 24 that is lower in magnitude than a voltage potential (e.g., a Vss potential) on the source region 21 of transistor 20. By reverse biasing channel region 24 with respect to source region 21, the leakage current across channel region 24 of transistor 20 may be reduced. As explained in more detail below, a Vss Generator 60 may be used to provide the Vss voltage potential to source region 21 by raising the Vsssup voltage potential 40. Additionally, a Vccsup generator 50 may be used to provide a voltage potential

(e.g., Vccsup) to channel region 34 that is greater than the voltage potential applied to source region 31 of transistor 30. This may reduce the amount of leakage across channel region 34. It should be understood that the scope of the present invention is not limited to integrated circuits that have both Vccsup generator 50 and Vss generator 60. In alternative embodiments, only one of the two circuits may be used.

Referring now to FIG. 2, two techniques for implementing Vccsup generator 50 are provided. FIG. 2 illustrates two circuits that may be used either individually or in combination to provide Vccsup generator 50. However, it should be understood that the scope of the present invention is not limited to these particular techniques as alternative embodiments may use other techniques, such as a charge pump, a dc-to-dc converter, etc. In one technique, a transistor 82 is used as Vccsup generator 50 to provide Veep voltage potential 41 as Vccsup. An enable signal, labeled E2 in FIG. 2, may be used to enable and control the operation of transistor 82 so that Vccsup generator 50 may selectively provide a voltage potential, labeled Vccsup. In this particular embodiment, the voltage potential provided by Vccsup generator 50 may be substantially equal to the Veep voltage potential 41, although this is not intended a limitation of the scope of the present invention.

Enable signal E2 may be activated when integrated circuit 10 has entered an inactive or stand-by mode. When portions of integrated circuit 10 are in a stand-by mode (e.g., logic transistors 20 and 30), it may be desirable to apply a voltage potential to channel region 34 (see FIG. 1) to reduce the amount of leakage current. In alternative embodiments, it may be desirable to manufacture transistor 82 so that it has a higher voltage tolerance than the transistors of integrated circuit 10. This may be accomplished, for example, by increasing the gate oxide thickness of transistor 82 as compared to the gate oxide of the transistors of integrated circuit 10. In alternative embodiments, an n- channel transistor (not shown) may be used in place of transistor 82.

Alternatively, Vccsup generator 50 may comprise a voltage reference circuit 65 connected to the gate of a transistor 81 (see FIG. 2). FIG. 3 is provided to demonstrate an example for implementing voltage reference circuit 65, although the scope of the present invention is not limited to this particular implementation. As shown, transistors 91, 94, and 99 may operate as a reference resistor element connected to a bootstrapped reference circuit. For example, a bootstrapped circuit comprising transistors 92, 93, 95, and 96 may provide an output voltage potential that may be applied to the gate of transistor 81. The voltage potential applied to the gate terminal of transistor 81 determines, at least in part, the voltage potential provided by Vccsup generator 50. In alternative embodiments, it may be desirable to manufacture transistors 92, 93, 95, and 96 as thick gate oxide transistors to reduce the risk of damage in the event of a voltage spike or if Veep voltage potential 41 is significantly greater than Vcc; for example, such as during a power up sequence. As shown in FIG. 2, Vccsup generator 50 may also include an enable transistor 80 to selectively connect the voltage potential provided by transistor 81 as the output voltage potential of Vccsup generator 50, namely, the Vccsup voltage potential. An enable signal, labeled El, may be used to determine when transistor 81 provides the Vccsup voltage potential. During operation of embodiment 100 (see FIG. 1), a signal, labeled ACTIVE# in

FIG. 2, may be used to indicate when all or portions of integrated circuit 10 may enter a stand-by or inactive mode, although the scope of the present invention is not limited in this respect. Consequently, enable signal El may be generated by inverting the ACTIVE# signal so that transistor 80 is on when transistor 89 is off. In contrast, when integrated circuit 10 is not in a stand-by or low-leakage mode, enable signals El and E2 may be disabled and the ACTIVE# signal may be enabled so that the Vccsup voltage potential may be driven to Vcc by transistor 89, thus allowing transistors 20 and 30 to operate normally.

When the ACTIVE# signal is disabled and enable signal El is enabled (e.g., to indicate that integrated circuit is in an inactive mode), voltage reference circuit 65 may raise the Vccsup voltage potential so that the voltage applied to channel region 34 (see FIG. 1) is greater than the voltage potential on source region 31. In this particular embodiment, the Vccsup voltage potential is at least 0.4 volts greater than the Veep voltage potential 42. However, it should be understood that the scope of the present invention is not limited in this respect as the voltage differential may be increased or reduced as desired.

Optionally, voltage reference circuit 65 may also include transistors 97 and 98 connected to a RESET#.ACTIVE signal. When the RESET#.ACTIVE signal is activated (e.g., indicating the core transistors 20 and 30 are active), transistors 91 and 98 may pull up the voltage potential on the drain of transistor 96 to reduce the risk that the bootstrapped circuit comprising transistors 92, 93, 95, and 96 does not resolve to the zero- current state solution.

One advantage of this particular embodiment of Vccsup generator 50 is that transistor 81 may provide a substantially constant voltage potential for Vccsup even if Veep voltage potential 41 should vary. Alternatively, the use of transistor 82 to implement Vccsup generator 50 may be advantageous because it may be less complex and formed in a smaller surface area than the particular embodiment shown in FIG. 3. Again, it may also be desirable to use both embodiments in the same integrated circuit. As shown in FIG. 1, embodiment 100 may also optionally include a Vss generator 60.

Two particular techniques to implement Vss generator 60 are shown in FIG. 2; however, it should be understood that the scope of the present invention is not limited to these particular implementations. For example, in one technique, Vss generator 60 may comprise transistors 83 and 84 that "float-up" Vsssup voltage potential 40. As shown, Vss generator 60 may also include an enable transistor 85 that may be controlled by an enable signal labeled E4. For example, if integrated circuit 10 is in a low leakage or inactive mode, transistor 85 may be enabled so that transistors 83-84 provide a Vss voltage potential that is greater than Vsssup voltage potential 40.

In this particular embodiment, the Vss voltage potential may be at least 0.4 volts greater than the Vsssup voltage potential 40. However, it should be understood that the scope of the present invention is not limited in this respect. The difference in voltage potential between the voltage potential applied to channel region 24 and the corresponding source region 21 may be changed as desired, for example, by sizing transistors 83 and 84 differently. The use of transistors 83 an 84 in this particular embodiment may provide a Vss voltage potential that is about two Vt's (threshold voltage potentials) above Vsssup voltage potential 40. However, it should be understood that this is not intended as a limitation of the present invention as in alternative embodiments devices with low threshold voltages may be used. Alternatively, the scope of the present invention is not limited to embodiments that use two transistors as a single or a plurality of transistors may be used in alternative embodiments.

Alternatively, Vss generator 60 may be provided with a feedback circuit 61 (see FIG. 2). Although the scope of the present invention is not limited to this particular configuration, FIG. 4 is provided as an example of an implementation for a feedback circuit 61 using a differential amplifier 45 connected to a transistor 86 and resistive elements Rl and R2. Differential amplifier 45 may be implemented with transistors 102- 106 and resistive elements Rl and R2 may be provided by a series of transistors 100 as shown in FIG. 4. The consumption of current by transistors 20 and 30 (see FIG. 2) may result in the Vss voltage potential rising above Vsssup voltage potential 40. Feedback circuit 61 may limit how high Vss may rise relative to a reference voltage provided by Rl and R2.

The output signal of differential amplifier 45 may be used to drive the gate of transistor 86. This, in turn, may source an amount of current sufficient to stabilize the Vss voltage potential if it is driven above the Vsssup voltage potential 40 by transistors 83 and 84. As shown in FIGs. 2 and 4, this embodiment may also include enable transistors 87 and 107 that may be controlled by an enable signal labeled E3. Enable signal E3 in conjunction an ACTIVE signal (see FIG. 2) may be used to determine when the Vss voltage potential is provided by transistor 88 or by transistor 86 in conjunction with transistors 83 and 84. One advantage of this particular embodiment is that transistor 86 may provide additional current to integrated circuit 10 if the Vss potential would otherwise be driven up too high. This may occur, for example, when integrated circuit 10 transitions from an inactive to active state (e.g. the core of integrated circuit 10 is "hot" immediately after high frequency operation and the leakage, and thus the overall current demand, may be high).

In the particular embodiment shown in FIG. 4, it may be desirable to operate transistors 102-107 in sub-threshold mode. However, this is not intended as a limitation of the present invention. In alternative embodiments, a capacitor may be placed between the gate and drain of feedback transistor 86 to provide stability to feedback amplifier 45. By now it should be appreciated that the present invention provides circuits and methods by which the leakage current of an integrated circuit may be reduced. In particular embodiments, the channel region of a transistor may be reverse biased with respect to its current carrying electrodes to reduce the flow of leakage current. The reverse biasing of the channel or body region relative to the current carrying electrodes may increase the potential barrier created by the channel region. Consequently, this may make it more difficult for electrons to pass between the current carrying electrodes of the transistor. While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. For example, in the embodiments described above, a voltage potential may be selectively applied to the channel region of a p-channel device or to the source region of a n-channel device to reduce the amount of leakage current. It should also be understood that a voltage potential may also be selectively applied to other terminals of a transistor. Furthermore, some of the embodiments described above included raising a voltage potential that was provided to the integrated circuit so that the channel region of a transistor may be reversed biased with respect to its source region. In alternative embodiments, it may also be desirable to lower a voltage potential and reverse where the voltage potentials are applied so that the channel region is still reversed biased with respect to the source region to reduce leakage current. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

Claims:What is claimed is:

1. An apparatus having an integrated circuit, the integrated circuit comprising; a first transistor having a source region and a body region; a first circuit adapted to provide a first voltage potential to the source region of the first transistor; and a second circuit adapted to selectively provide a second voltage potential to the body region of the first transistor, wherein the second voltage potential is greater than the first voltage potential.

2. The apparatus of claim 1, wherein the second circuit is further adapted to selectively provide a second voltage potential that is at least approximately 0.4 volts greater than the first voltage potential.

3. The apparatus of claim 1, wherein the second circuit is further adapted to selectively provide the second voltage potential when the first transistor is in an inactive state.

4. The apparatus of claim 1, wherein the second circuit includes a transistor adapted to be coupled to a third voltage potential, the third voltage potential being greater than the first voltage potential.

5. The apparatus of claim 4, wherein the transistor of the second circuit has a gate terminal, and the second circuit includes a voltage reference circuit adapted to apply a voltage to the gate terminal of the transistor of the second circuit.

6. The apparatus of claim 5, wherein the transistor of the second circuit has a drain terminal, and the second circuit is further adapted to provide the second voltage potential with the drain terminal of the transistor.

7. The apparatus of claim 6, further comprising a transistor adapted to selectively provide the second voltage potential.

8. The apparatus of claim 1, further comprising: a second transistor having a source region and a body region; a third circuit adapted to selectively provide a third voltage potential to the source region of the second logic transistor; and a fourth circuit adapted to provide a fourth voltage potential to the body region of the second transistor, wherein the fourth voltage potential is less than the third voltage potential.

9. The apparatus of claim 8, wherein the first voltage potential is greater than the fourth voltage potential.

10. The apparatus of claim 9, wherein the first transistor is a p-channel transistor and the second transistor is an n-channel device.

11. The apparatus of claim 9 wherein the fourth circuit comprises a differential amplifier coupled to a resistive element.

12. The apparatus of claim 11, wherein the resistive element comprises a plurality of transistors.

13. The apparatus of claim 8, wherein the integrated circuit is adapted to receive the first voltage potential, the second voltage potential, and the fourth voltage potential from an external source.

14. The apparatus of claim 4, wherein the second circuit is further adapted to maintain the second voltage potential at a substantially constant value if the third voltage potential is increased.

15. An integrated circuit comprising: a first transistor and a second transistor, each comprising a current carrying electrode and a channel region; a first circuit adapted to receive a first voltage potential and provide the first voltage potential to the current carrying electrode of the first transistor; a second circuit adapted to provide a second voltage potential to the channel region of the first transistor; the second voltage being greater than the first voltage potential; a third circuit adapted to receive a third voltage potential and provide the third voltage potential to the current carrying electrode of the second transistor; and a fourth circuit adapted to provide a fourth voltage potential to the channel region of the second transistor.

16. The integrated circuit of claim 15, wherein the second circuit is further adapted to selectively provide the second voltage potential to the channel region of the first transistor.

17. The integrated circuit of claim 16, wherein the third circuit is further adapted to selectively provide the third voltage potential to the source region of the second transistor.

18. The integrated circuit of claim 15, wherein the second circuit comprises a charge pump.

19. A method comprising: providing a first voltage potential to a current carrying electrode of a first transistor; generating a second voltage potential; providing the second voltage potential to a channel region of the first transistor; generating a third voltage potential; providing the third voltage potential to a current carrying electrode of a second transistor; and providing a fourth voltage potential to the channel region of a second transistor.

20. The method of claim 19, wherein generating the second voltage potential includes generating a voltage potential that is greater than the first voltage potential.

21. The method of claim 20, wherein generating the third voltage potential includes generating a voltage potential that is greater than the fourth voltage potential.

22. The method of claim 19, wherein generating the second voltage potential includes receiving a fifth voltage potential to raise the second voltage potential above the first voltage potential.

23. The method of claim 19, wherein generating the third voltage potential includes raising the fourth voltage potential.

24. The method of claim 19, further comprising selectively removing the second voltage potential from the channel region of the first transistor.

25. The method of claim 24, further comprising selectively removing the fourth voltage potential from the channel region of the second transistor.

26. The method of claim 25, wherein selectively removing the fourth voltage potential occurs substantially simultaneously with selectively removing the second voltage potential.

27. A method of reducing the leakage current in a transistor having a channel region and a source region, the method comprising: providing a first voltage potential to the source region of the transistor; generating a second voltage potential using the first voltage potential, the second voltage potential being greater than the first voltage potential; and selectively applying the second voltage potential to the channel region of the transistor.

28. The method of claim 27, wherein generating the second voltage includes receiving a third voltage potential.

29. The method of claim 28, wherein generating the second voltage includes generating a voltage that is substantially constant if the third voltage potential varies.

30. The method of claim 27, wherein providing the first voltage potential includes receiving a voltage potential from an external source.

31. A portable communication device having an integrated circuit, the integrated circuit comprising; a first logic transistor having a source region and a body region; a first circuit adapted to selectively provide a first voltage potential to the source region of the first logic transistor; and a second circuit adapted to provide a second voltage potential to the body region of the first logic transistor, wherein the second voltage potential is less than the first voltage potential.

32. The portable communication device of claim 31 , wherein the first circuit is further adapted to provide a first voltage potential that is at least 0.4 volts greater than the second voltage potential.

33. The portable communication device of claim 31, wherein the first circuit is further adapted to provide the first voltage potential when the transistor is in an inactive state.

34. A portable communication device having an integrated circuit, the integrated circuit comprising; a first logic transistor having a source region and a body region; a first circuit adapted to provide a first voltage potential to the source region of the first logic transistor; and a second circuit adapted to selectively provide a second voltage potential to the body region of the first logic transistor, wherein the first voltage potential is greater than the second voltage potential.

35. The portable communication device of claim 34, wherein the first circuit is further adapted to provide a voltage potential that is at least 0.4 volts greater than the second voltage potential.

36. The portable communication device of claim 34, wherein the second circuit is further adapted to provide the second voltage potential when the transistor is in an inactive state.

37. A method of reducing the leakage current across a channel region of a transistor comprising: selectively applying a voltage potential to the channel region, wherein the voltage potential is greater than a voltage potential on a current carrying electrode of the transistor.

38. The method of claim 37, further comprising providing the voltage potential to the current carrying electrode of the transistor.

39. The method of claim 38, further comprising generating the voltage potential applied to the channel region using the voltage potential applied to the current carrying electrode.