[go: up one dir, main page]

WO2001082664A1 - Printed wiring board and method of mounting circuit element on this wiring board - Google Patents

Printed wiring board and method of mounting circuit element on this wiring board Download PDF

Info

Publication number
WO2001082664A1
WO2001082664A1 PCT/JP2000/002661 JP0002661W WO0182664A1 WO 2001082664 A1 WO2001082664 A1 WO 2001082664A1 JP 0002661 W JP0002661 W JP 0002661W WO 0182664 A1 WO0182664 A1 WO 0182664A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
circuit
printed wiring
conductor
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2000/002661
Other languages
French (fr)
Japanese (ja)
Inventor
Kouichiro Asou
Yasuhiro Mikasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2000/002661 priority Critical patent/WO2001082664A1/en
Publication of WO2001082664A1 publication Critical patent/WO2001082664A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0292Programmable, customizable or modifiable circuits having a modifiable lay-out, i.e. adapted for engineering changes or repair
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0295Programmable, customizable or modifiable circuits adapted for choosing between different types or different locations of mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09954More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10689Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a printed wiring board and a method for mounting a circuit element using the printed wiring board. Background technology
  • electronic circuits are realized by mounting electronic components on printed wiring boards.
  • Ic integrated circuit
  • the leads of the IC chip are soldered to the land formed on the surface of the printed wiring board
  • Another electronic component is soldered to another land that is conductive by the conductor pattern, thereby making an electrical connection between the IC chip and the other electronic component.
  • an insulating layer is interposed between the conductor pattern on one surface and the conductor pattern on the other surface, and the insulating layer is interposed between the conductor patterns.
  • Japanese Unexamined Patent Publication No. Sho 60-222396 discloses a specific terminal of an IC chip mounted on the front surface after manufacturing a wiring board and an input / output on the back surface of the board. For repairs on the surface of the board with the aim of relieving faulty wiring without changing the wiring board even if the wiring connection between the terminal pins and the through-hole wiring is broken. It discloses a circuit board including a pad, a spare terminal on the back surface, and a spare wiring portion for connecting these. Using this circuit board, high-density mounting of many IC chips Degree LSI package can be provided.
  • this circuit board can relieve a wiring failure when a break occurs in a wiring connection or a through-hole wiring, but cannot change an electronic circuit when remodeling an electronic device.
  • Japanese Unexamined Patent Publication No. 5-243553 / 1993 discloses that each element is formed by performing wiring of two layers mutually insulated by an insulating film on a master slice that has been formed up to a transistor on a semiconductor substrate. It discloses a master slice type semiconductor integrated circuit in which connections are made. In this semiconductor integrated circuit, a spare wiring that is not connected to any element is provided in a vacant area where the basic wiring is not wired, so that a desired circuit can be modified and changed with only one wiring layer. I have. However, it is difficult to apply this technology to printed wiring boards as it is necessary to make a new mask to change the wiring layer.
  • Japanese Utility Model No. 419/97974 is an auxiliary circuit board that is additionally provided on a remodeled board as a pre-designed circuit board, and the electronic circuit is changed using strap wires.
  • a circuit board is disclosed.
  • this technique has a problem in that the number of components increases because an auxiliary circuit board needs to be additionally provided to remodel the electronic circuit.
  • No. 58-1 4 4 8 7 1 provided a plurality of spare through holes interconnected by a spare pattern formed on the outer layer, and directly connected the circuit pattern formed on the inner layer to the spare through hole. It discloses a repair pattern for a multi-layer printed wiring board that is connected. However, when changing the electronic circuit using this repair pattern, it is necessary to additionally provide other electronic circuit components or to perform connection work with an external circuit using strap wires. There is a problem that the work for remodeling becomes complicated.
  • an object of the present invention is to provide a printed wiring board in which an electronic circuit can be easily changed when remodeling an electronic device.
  • Another object of the present invention is to provide a method for mounting a circuit element (electronic component) using the printed wiring board.
  • a printed wiring board on which a circuit element having a plurality of terminals is to be mounted.
  • the printed wiring board includes a plurality of conductor lands that can selectively connect a plurality of types of circuit elements, and a plurality of wirings that connect a part of the plurality of conductor lands to the ground.
  • Wiring should be cut when at least one of the circuit's terminals in the connected circuit element is connected to dulland, and at least one of the circuit's terminals is connected to ground As much as possible, they are provided corresponding to a plurality of types of circuit elements.
  • the conductor land is provided such that a part of the conductor land is connected to a terminal of the circuit element.
  • the conductor lands are desirably provided so that the conductor lands used for the connection differ depending on the type of the circuit element.
  • a plurality of conductor lands that can selectively connect a plurality of types of circuit elements, and a plurality of wirings that connect a part of the plurality of conductor lands to the ground.
  • a step of connecting one to a ground
  • the present invention provides a printed wiring board on which a transistor, a transistor, and a logic element (TTL element) having a plurality of terminals are to be mounted.
  • the printed wiring board includes first to sixteenth conductor lands corresponding to the plurality of terminals and the third, fifth, sixth, eighth, tenth, eleventh, and eleventh, respectively.
  • a plurality of conductor patterns respectively connected to the 13th, 14th and 16th conductor lands; a connection pattern for connecting between the 7th and 8th conductor lands; And a connection pattern for connecting between the sixteenth conductor patterns.
  • the first to eighth conductor lands are arranged in a line at equal intervals, and the ninth to sixteenth conductor lands are arranged such that the first and ninth conductor lands are diagonally arranged. And the eighth and sixteenth conductor lands are arranged at regular intervals in a row so as to be diagonally aligned.
  • the third, fifth, sixth, eighth, tenth, eleventh, thirteenth, and thirteenth above are described.
  • the plurality of conductor patterns respectively connected to the first and fourth conductor lands are connected to the ground, and the conductor patterns connected to the sixteenth conductor lands are connected to the power supply line.
  • a method for modifying an electronic device includes a step of mounting a circuit element (more specifically, a TTL element) on a printed wiring board according to the present invention, and a step of cutting at least one of the conductor pattern and the connection pattern.
  • FIG. 1 is a plan view showing an embodiment of a printed wiring board according to the present invention
  • FIGS 2A-2E show TTL elements as circuit elements (electronic components) that can be mounted on the printed wiring board shown in Figure 1;
  • Fig. 3 shows an example of the connection state when the "08" type TTL element shown in Fig. 2D is mounted on the printed wiring board shown in Fig. 1;
  • Fig. 4 shows another example of the connection state when the "08" type TTL element shown in Fig. 2D is mounted on the printed wiring board shown in Fig. 1;
  • Fig. 5 is a diagram showing an example of the connection state when the "04" type TTL element shown in Fig. 2C is mounted on the printed wiring board shown in Fig. 1;
  • Fig. 6 shows an example of the connection state when the "02" type TTL element shown in Fig. 2B is mounted on the printed wiring board shown in Fig. 1;
  • FIG. 7 is a plan view showing an example of a conventional printed wiring board.
  • FIG. 8 is a diagram showing an example of a connection state when the “08” type TTL element shown in FIG. 2D is mounted on the printed wiring board shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a plan view showing an embodiment of a printed wiring board according to the present invention.
  • This printed wiring board has first to sixteenth conductor lands formed on an outer layer of a single-layer or multi-layer circuit board (not shown; which is to be understood as paper itself). Circle in each figure The number described in the mark is the number of each conductor land.
  • the shape of the conductor land is rectangular, but may be circular or any other shape as long as it can be electrically connected to the electronic component (circuit component) to be mounted. .
  • the first to eighth conductor lands are arranged in a line at equal intervals.
  • the ninth to sixteenth conductor lands are arranged such that the first and ninth conductor lands are on a diagonal and the eighth and sixteenth conductor lands are on a diagonal. They are arranged in a line at intervals.
  • the eighth conductor land is connected to ground (GND) via conductor pattern 8A, and the 16th conductor land is connected to power supply line (Vcc) via conductor pattern 16A.
  • the seventh and eighth conductor lands are connected by a connection pattern 20, and the 15th and 16th conductor lands are connected by a connection pattern 22.
  • the third, fifth, sixth, tenth, eleventh, thirteenth, and fourteenth conductor lands are Patterns 3 A, 5 A, 6 A, 10 A, 11 A, 13 A, and 14 A are connected to ground.
  • connection between the seventh and eighth conductor lands by the connection pattern 20 and the connection between the 15th and 16th conductor lands by the connection pattern 22 are caused by various circuit components. This is because it is possible to respond to Specifically, for example, there are many types of TTL elements frequently used for changing an electronic circuit, and the arrangement of the ground and the power supply line differs depending on the TTL element used. While the TTL element has 14 pins (7 ⁇ 2 rows), in the present embodiment, as shown in FIG. 1, the printed wiring board has 16 conductor lands (8 ⁇ 2 rows). ), The mounting position can be changed according to the type of TTL element, so that differences in the layout of ground and power supply lines can be easily accommodated.
  • the first to sixteenth conductor lands are a part of them (the first to seventh and tenth to sixteenth conductor lands, or the second to eighth and ninth conductor lands).
  • the ninth to fifteenth conductor lands are provided so as to be connected to the circuit elements (14-pin TTL elements). More specifically, the first to sixteenth conductor lands are provided such that the conductor lands to be connected are different depending on the type of the circuit element. Therefore, by changing the mounting position on the printed wiring board according to the type of circuit element, It is possible to easily cope with the difference in arrangement of the ground and the power supply line.
  • a TTL element is illustrated as a circuit element (electronic component) mountable on the printed wiring board shown in FIG.
  • the package of each element is common, and here, terminals 1 to 14 are provided.
  • the terminals 1 to 7 are arranged in a line at equal intervals.
  • the terminals 8 to 14 are arranged in a line at equal intervals so that the terminals 1 and 8 are on a diagonal and the terminals 7 and 14 are on a diagonal.
  • Terminal 7 is connected to ground (GND), and terminal 14 is connected to the power supply line (Vcc), and each element is used.
  • FIG. 2A shows a “00” type TTL device having four NAND gates as circuits in the circuit device, for example, SN 7 4AS 00 (QUAD RUP LE 2—I NP UT POSITI VE— NAND GAT ES) is equivalent to this.
  • FIG. 2B shows a “02” type TTL element having four NOR gates as circuits in the circuit element, for example, SN 74 AS 02 (QUAD RU PLE 2—I NP UT POSITI VE—NO R GAT ES) corresponds to this.
  • Figure 2C shows a ⁇ 04 '' type TTL element with six impellers each as a circuit in the circuit element, for example, SN 74A S 04 (HEX I NV ERTERS) I do.
  • FIG. 2D shows a “08” type TTL element having four AND gates as circuits in the circuit element, for example, SN 7 4A S 08 (QUAD RUP LE 2—I NP UT POSITI VE — AND GAT ES) is the equivalent.
  • FIG. 2E shows a “32” type TTL device having four OR gates each as a circuit in the circuit device.
  • SN 7 4A S 3 2 (QUAD RUP LE 2—I NP UT POSITIVE) — OR GAT ES) is equivalent to this.
  • Fig. 3 is a diagram showing an example of the connection state when the "08" type TTL element shown in Fig. 2D is mounted on the printed wiring board shown in Fig. 1. An example of a method for mounting a circuit element according to the present invention will be described.
  • terminals 1 to 7 are respectively connected to the second to eighth conductor lands, and terminals 8 to 14 are respectively connected to ninth to 15th conductor lands.
  • the pattern of the printed wiring board is configured in consideration of the free terminal processing of the TTL element (at least one input terminal of each AND gate is always connected to ground). Since the connection pattern 20 is simply cut to open the seventh conductor land (terminal 6), preparation for remodeling is completed.
  • FIG. 4 is a diagram showing another example of a connection state when the “08” type TTL element shown in FIG. 2D is mounted on the printed wiring board shown in FIG.
  • the circuit is embodied on this printed wiring board using one AND gate connected to the second to fourth conductor lands (terminals 1 to 3). If one of the inputs connected to the third conductor land (terminal 2) of the AND gate is constant at the mouth level, the conductor pattern is The cutting of A and the wiring to the third conductor land become unnecessary. Therefore, the work for the remodeling can be performed by cutting the connection pattern 20 and arranging the second and fourth conductor lands, thereby making it easier to change the electronic circuit.
  • FIG. 5 is a diagram showing an example of a connection state when the “04” type TTL element shown in FIG. 2C is mounted on the printed wiring board shown in FIG.
  • the TTL element has terminals 1 to 7 connected to the first to seventh conductor lands, respectively, and terminals 8 to 14 connected to the 10th to 16th conductor lands, respectively. Then, it is mounted on the printed wiring board.
  • the processing of the empty terminals of the TTL element (each inverter)
  • the input and output terminals at least one of them should always be connected to the ground), and the conductor pattern 6 A, 1 OA and Just cut the 14 A and you're ready to convert.
  • the electronic circuit embodied on the printed wiring board can be extremely easily changed by simply performing wiring for an arbitrary inverter using the inverter.
  • electronic devices such as computer terminals can be easily remodeled.
  • FIG. 6 is a diagram showing an example of a connection state when the “02” type TTL element shown in FIG. 2B is mounted on the printed wiring board shown in FIG.
  • the TTL element has terminals 1 to 7 connected to the first to seventh conductor lands, respectively, and terminals 8 to 14 connected to the 10th to 16th conductor lands, respectively. Mounted on the printed wiring board as shown.
  • the pattern of the printed wiring board is configured in consideration of the TTL element free terminal processing (at least one input terminal of each NOR gate must be connected to the ground). Since the connection pattern 22 is cut to open the 15th conductor land (terminal 13), the preparation for remodeling is completed.
  • wiring can be performed only on an arbitrary N ⁇ R gate (not shown, but the conductor pattern is cut off as necessary), and the NOR gate is used on this printed wiring board.
  • the embodied electronic circuit can be changed very easily. As a result, electronic devices such as computer terminals can be easily remodeled.
  • FIGS. 7 and 8 one example of a conventional printed wiring board and an example of a method for mounting circuit components using the printed wiring board are shown. The technical advantages of the present invention will be described more specifically.
  • This printed wiring board has first to sixteenth conductor lands formed on the outer layer of the circuit board, as shown in FIG.
  • the first to eighth conductor lands are arranged in a line at equal intervals, and the ninth to sixteenth conductor lands are arranged such that the first and ninth conductor lands are on a diagonal and the eighth to eighth conductor lands.
  • the 16th conductor lands are arranged in a line at equal intervals so that they are diagonally arranged.
  • the eighth conductor land is connected to the ground (GND) via the conductor pattern 8A, and the 16th conductor land is connected to the conductor pattern. It is connected to the power line (V cc) via pin 16A.
  • FIG. 8 is a diagram showing an example of a connection state when, for example, the TTL element shown in FIG. 2D is mounted on the printed wiring board shown in FIG. 7 as a circuit component.
  • the TTL element has terminals 1 to 7 connected to the second to eighth conductor lands, respectively, and terminals 8 to 14 connected to the ninth to 15th conductor lands, respectively. , Mounted on the printed wiring board.
  • the present invention it is possible to provide a printed wiring board in which an electronic circuit can be easily changed when remodeling an electronic device, and a method for mounting a circuit element using the printed wiring board. become. Further, according to the present invention, an electronic device such as a computer terminal can be easily remodeled using the printed wiring board, which greatly contributes to an improvement in the speed of product development.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A printed wiring board on which a plurality of circuit elements having a plurality of terminals is to be mounted. This wiring board has a plurality of conductive lands for selectively connecting a plural kinds of circuit elements and a plurality of wirings for connecting a part of the conductive lands to the ground. The wirings are adapted to the circuit elements so that one of the wirings is disconnected and at least one of the terminals of the circuit can be connected to the ground when at least one of the terminals of the circuit in the circuit element to be connected is connected to the ground. By using this wiring board, an electronic circuit embodied thereon can be easily changed and an electronic apparatus such as a computer terminal can be easily modified.

Description

明 細 書 プリ ン ト配線板及びそのプリ ン ト配線板を用いた回路素子の実装方法 技 術 分 野  Description Printed circuit board and method for mounting circuit elements using the printed circuit board

本発明はプリ ン ト配線板及びそのプリ ント配線板を用いた回路素子の実装方法 に関する。 背 景 技 術  The present invention relates to a printed wiring board and a method for mounting a circuit element using the printed wiring board. Background technology

電子機器製造の分野においては、 プリ ン ト配線板に電子部品を実装することに よって、 電子回路が具現化される。 例えば、 I c (集積回路) チップをプリ ン ト 配線板に表面実装する場合、 I Cチップのリードがプリ ン ト配線板の表面上に形 成されたラン ドに半田付けされ、 そのラン ドに導体パターンにより導通している 他のラン ドに他の電子部品が半田付けされ、 それによ りその I Cチップと他の電 子部品との間の電気的な接続がなされる。 多層プリ ン ト配線板が採用されている 場合には、 ある面上の導体パターンと他の面上の導体パターンとの間には絶縁層 が介在しており、 両導体パターン間は、 絶縁層を貫通するビアにより接続される ( 一旦、 電子部品がプリ ン ト配線板に実装されると、 その電子部品に関連して具 現化された電子回路を変更するのは容易ではない。 近年、 パーソナルコンピュー 夕等の電子機器の開発期間はますます短縮化されてきており、 開発工程の高速化 が求められている。 1つの製品は幾度もの改造を絰て巿場に提供されるので、 改 造時間の短縮化が製品の開発スピードの向上に直結する。 従って、 電子機器を改 造する上で電子回路の変更が容易なプリ ン ト配線板が要望されている。 In the field of electronic device manufacturing, electronic circuits are realized by mounting electronic components on printed wiring boards. For example, when mounting an Ic (integrated circuit) chip on a printed wiring board, the leads of the IC chip are soldered to the land formed on the surface of the printed wiring board, Another electronic component is soldered to another land that is conductive by the conductor pattern, thereby making an electrical connection between the IC chip and the other electronic component. When a multilayer printed wiring board is employed, an insulating layer is interposed between the conductor pattern on one surface and the conductor pattern on the other surface, and the insulating layer is interposed between the conductor patterns. ( Once an electronic component is mounted on a printed wiring board, it is not easy to change the electronic circuit embodied in connection with the electronic component. The development period of electronic devices such as personal computers is becoming shorter and shorter, and the development process is required to be accelerated Since one product is provided to the factory after many modifications, Shorter remodeling time is directly linked to faster product development, so there is a need for printed wiring boards that allow easy modification of electronic circuits when remodeling electronic equipment.

特開昭 6 0— 2 2 3 9 6号 (米国特許第 4 , 8 9 4 , 7 0 8号) は、 配線基板 の製造後に表面に実装される I Cチップの特定端子と基板裏面の入出力端子ピン との間の配線接続やスルーホール配線に断線が生じた場合であっても配線基板に 何ら手を加えることなく配線不良を救済することを目的と して、 基板表面上の修 理用パッ ドと、 裏面の予備端子と、 これらを接続する予備配線部とを備えた回路 基板を開示している。 この回路基板を用いて、 多数の I Cチップを実装した高密 度 L S Iパッケージを提供することができる。 Japanese Unexamined Patent Publication No. Sho 60-222396 (U.S. Pat. No. 4,894,708) discloses a specific terminal of an IC chip mounted on the front surface after manufacturing a wiring board and an input / output on the back surface of the board. For repairs on the surface of the board with the aim of relieving faulty wiring without changing the wiring board even if the wiring connection between the terminal pins and the through-hole wiring is broken. It discloses a circuit board including a pad, a spare terminal on the back surface, and a spare wiring portion for connecting these. Using this circuit board, high-density mounting of many IC chips Degree LSI package can be provided.

しかし、 この回路基板では、 配線接続やスルーホール配線に断線が生じた場合 に配線不良を救済することはできるものの、 電子機器を改造する上で電子回路を 変更することはできない。  However, this circuit board can relieve a wiring failure when a break occurs in a wiring connection or a through-hole wiring, but cannot change an electronic circuit when remodeling an electronic device.

特開平 5— 2 4 3 5 3 5号は、 半導体基板上への トランジス夕形成までを済ま せたマスタ一スライス上に、 絶縁膜によって相互に絶縁された 2層からなる配線 を行って各素子間を接続するようにしたマスタースライス型の半導体集積回路を 開示している。 この半導体集積回路では、 基本配線が配線されていない空き領域 にいずれの素子にも接続されていない予備配線を設けることによって、 1つの配 線層のみで所望の回路の修正及び変更を可能にしている。 しかし、 その配線層を 変更するために新たにマスクを作製する必要があるので、 この技術をそのままプ リ ン ト配線板に適用するのは困難である。  Japanese Unexamined Patent Publication No. 5-243553 / 1993 discloses that each element is formed by performing wiring of two layers mutually insulated by an insulating film on a master slice that has been formed up to a transistor on a semiconductor substrate. It discloses a master slice type semiconductor integrated circuit in which connections are made. In this semiconductor integrated circuit, a spare wiring that is not connected to any element is provided in a vacant area where the basic wiring is not wired, so that a desired circuit can be modified and changed with only one wiring layer. I have. However, it is difficult to apply this technology to printed wiring boards as it is necessary to make a new mask to change the wiring layer.

実開平 4 一 5 9 9 7 4号は、 既設計の回路基板としての改造基板上に補助回路 基板を付加的に設け、 ス トラップ線を用いて電子回路を変更するようにした改造 用の補助回路基板を開示している。 しかし、 この技術では、 電子回路を改造する ために補助回路基板を付加的に設ける必要があるので、 構成部品数が増えるとい う問題がある。  Japanese Utility Model No. 419/97974 is an auxiliary circuit board that is additionally provided on a remodeled board as a pre-designed circuit board, and the electronic circuit is changed using strap wires. A circuit board is disclosed. However, this technique has a problem in that the number of components increases because an auxiliary circuit board needs to be additionally provided to remodel the electronic circuit.

実開昭 5 8 - 1 4 4 8 7 1号は、 外層に形成された予備パターンにより相互に 接続された複数の予備スルーホールを設け、 内層に形成された回路パターンを予 備スルーホールに直接接続してなる多層プリ ン ト配線板の修復用パターンを開示 している。 しかし、 この修復用パターンを用いて電子回路を変更する場合、 他の 電子回路部品を付加的に設けるかあるいはス トラップ線を用いた外部回路との接 続作業を行う必要があり、 電子機器を改造するための作業が煩雑になるという問 題がある。  Actually, No. 58-1 4 4 8 7 1 provided a plurality of spare through holes interconnected by a spare pattern formed on the outer layer, and directly connected the circuit pattern formed on the inner layer to the spare through hole. It discloses a repair pattern for a multi-layer printed wiring board that is connected. However, when changing the electronic circuit using this repair pattern, it is necessary to additionally provide other electronic circuit components or to perform connection work with an external circuit using strap wires. There is a problem that the work for remodeling becomes complicated.

よって、 本発明の目的は、 電子機器を改造する上で電子回路の変更が容易なプ リ ン ト配線板を提供することである。  Therefore, an object of the present invention is to provide a printed wiring board in which an electronic circuit can be easily changed when remodeling an electronic device.

本発明の他の目的は、 そのプリ ン ト配線板を用いた回路素子 (電子部品) の実 装方法を提供することである。  Another object of the present invention is to provide a method for mounting a circuit element (electronic component) using the printed wiring board.

発明の開示 本発明によると、 複数の端子を有する回路素子が実装されるべきプリ ン ト配線 板が提供される。 このプリ ン ト配線板は、 複数種類の回路素子を択一的に接続可 能な複数の導体ラン ドと、 複数の導体ラン ドのうちの一部とグラン ドとを接続す る複数の配線とを有している。 配線は、 接続される回路素子内の回路の端子の少 なく とも 1つがダラン ドに接続されるようにするときに、 配線のいずれかを切断 して回路の端子の少なく とも 1つがグランドに接続可能なように、 複数種類の回 路素子に対応して設けられている。 Disclosure of the invention According to the present invention, there is provided a printed wiring board on which a circuit element having a plurality of terminals is to be mounted. The printed wiring board includes a plurality of conductor lands that can selectively connect a plurality of types of circuit elements, and a plurality of wirings that connect a part of the plurality of conductor lands to the ground. And Wiring should be cut when at least one of the circuit's terminals in the connected circuit element is connected to dulland, and at least one of the circuit's terminals is connected to ground As much as possible, they are provided corresponding to a plurality of types of circuit elements.

望ましくは、 導体ラン ドは、 導体ラン ドの一部が回路素子の端子と接続される ように設けられている。  Preferably, the conductor land is provided such that a part of the conductor land is connected to a terminal of the circuit element.

この場合、 望ま しくは、 導体ランドは、 回路素子の種類に応じて接続に使用さ れる導体ラン ドが異なるように設けられている。  In this case, the conductor lands are desirably provided so that the conductor lands used for the connection differ depending on the type of the circuit element.

本発明の他の側面による と、 複数種類の回路素子を択一的に接続可能な複数の 導体ラン ドと、 複数の導体ラン ドのうちの一部とグラン ドとを接続する複数の配 線.とを有し、 複数の端子を有する回路素子が実装されるべきプリ ン ト配線板に回 路素子を実装する工程と、 配線のいずれかを切断して回路素子内の回路の端子の 少なく とも 1つをグラン ドに接続する工程とを有する回路素子の実装方法が提供 される。  According to another aspect of the present invention, a plurality of conductor lands that can selectively connect a plurality of types of circuit elements, and a plurality of wirings that connect a part of the plurality of conductor lands to the ground. Mounting a circuit element on a printed wiring board on which a circuit element having a plurality of terminals is to be mounted; and cutting one of the wires to reduce the number of circuit terminals in the circuit element. And a step of connecting one to a ground.

より特定的には、 本発明による と、 複数の端子を有する トランジスタ · トラン ジス夕 · ロジック素子 (T T L素子) が実装されるべきプリ ン ト配線板が提供さ れる。 このプリ ン ト配線板は、 上記複数の端子にそれそれ対応する第 1乃至第 1 6の導体ラン ドと、 上記第 3、 第 5、 第 6、 第 8、 第 1 0、 第 1 1、 第 1 3、 第 1 4及び第 1 6の導体ラン ドにそれそれ接続される複数の導体パターンと、 上記 第 7及び第 8の導体ラン ド間を接続する接続パターンと、 上記第 1 5及び第 1 6 の導体パターン間を接続する接続パターンとを備えている。  More specifically, the present invention provides a printed wiring board on which a transistor, a transistor, and a logic element (TTL element) having a plurality of terminals are to be mounted. The printed wiring board includes first to sixteenth conductor lands corresponding to the plurality of terminals and the third, fifth, sixth, eighth, tenth, eleventh, and eleventh, respectively. A plurality of conductor patterns respectively connected to the 13th, 14th and 16th conductor lands; a connection pattern for connecting between the 7th and 8th conductor lands; And a connection pattern for connecting between the sixteenth conductor patterns.

望ましくは、 上記第 1乃至第 8の導体ラン ドは等間隔で一列に配置され、 上記 第 9乃至第 1 6の導体ラン ドは、 上記第 1及び第 9の導体ラン ドが対角上にあ り 且つ上記第 8及び第 1 6の導体ランドが対角上にあるように、 等間隔で一列に配 置される。  Preferably, the first to eighth conductor lands are arranged in a line at equal intervals, and the ninth to sixteenth conductor lands are arranged such that the first and ninth conductor lands are diagonally arranged. And the eighth and sixteenth conductor lands are arranged at regular intervals in a row so as to be diagonally aligned.

また、 望ましく は、 上記第 3、 第 5、 第 6、 第 8、 第 1 0、 第 1 1、 第 1 3及 び第 1 4の導体ラン ドにそれぞれ接続される複数の導体パターンはグラン ドに接 続され、 上記第 1 6の導体ランドに接続される導体パターンは電源線に接続され る。 Also, desirably, the third, fifth, sixth, eighth, tenth, eleventh, thirteenth, and thirteenth above are described. The plurality of conductor patterns respectively connected to the first and fourth conductor lands are connected to the ground, and the conductor patterns connected to the sixteenth conductor lands are connected to the power supply line.

更に、 本発明によると、 電子機器の改造方法が提供される。 この方法は、 本発 明によるプリ ン ト配線板に回路素子 (より特定的には T T L素子) を実装するス テツプと、 上記導体パターン及び上記接続パターンの少なく ともいずれかを切断 するステップとを備えている。 図面の簡単な説明  Further, according to the present invention, there is provided a method for modifying an electronic device. This method includes a step of mounting a circuit element (more specifically, a TTL element) on a printed wiring board according to the present invention, and a step of cutting at least one of the conductor pattern and the connection pattern. Have. BRIEF DESCRIPTION OF THE FIGURES

図 1は本発明によるプリ ン ト配線板の実施形態を示す平面図 ;  FIG. 1 is a plan view showing an embodiment of a printed wiring board according to the present invention;

図 2 A— 2 Eは図 1に示されるプリ ン ト配線板に実装可能な回路素子 (電子部 品) としての T T L素子を例示する図 ;  Figures 2A-2E show TTL elements as circuit elements (electronic components) that can be mounted on the printed wiring board shown in Figure 1;

図 3は図 2 Dに示される 「 0 8」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す図 ;  Fig. 3 shows an example of the connection state when the "08" type TTL element shown in Fig. 2D is mounted on the printed wiring board shown in Fig. 1;

図 4は図 2 Dに示される 「0 8」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の他の例を示す図 ;  Fig. 4 shows another example of the connection state when the "08" type TTL element shown in Fig. 2D is mounted on the printed wiring board shown in Fig. 1;

図 5は図 2 Cに示される 「 0 4」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す図 ;  Fig. 5 is a diagram showing an example of the connection state when the "04" type TTL element shown in Fig. 2C is mounted on the printed wiring board shown in Fig. 1;

図 6は図 2 Bに示される 「 0 2」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す'図 ;  Fig. 6 shows an example of the connection state when the "02" type TTL element shown in Fig. 2B is mounted on the printed wiring board shown in Fig. 1;

図 7は従来のプリ ン ト配線板の一例を示す平面図 ; そして  FIG. 7 is a plan view showing an example of a conventional printed wiring board; and

図 8は図 2 Dに示される 「 0 8」 型の T T L素子を図 7に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す図である。 発明を実施するための最良の態様  FIG. 8 is a diagram showing an example of a connection state when the “08” type TTL element shown in FIG. 2D is mounted on the printed wiring board shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

以下、 添付図面を参照して、 本発明の望ま しい実施形態を詳細に説明する。 図 1は本発明によるプリ ン ト配線板の実施形態を示す平面図である。 このプリ ン ト配線板は、 単層又は多層の回路基板 (図示せず ; 紙面そのものと理解された い) の外層上に形成された第 1乃至第 1 6の導体ランドを有している。 各図で丸 印の中に記載されている番号は各導体ランドの番号である。 図示された例では、 導体ラン ドの形状は長方形であるが、 実装されるべき電子部品 (回路部品) との 電気的な接続が可能であれば、 円形その他どのような形状であってもよい。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a plan view showing an embodiment of a printed wiring board according to the present invention. This printed wiring board has first to sixteenth conductor lands formed on an outer layer of a single-layer or multi-layer circuit board (not shown; which is to be understood as paper itself). Circle in each figure The number described in the mark is the number of each conductor land. In the illustrated example, the shape of the conductor land is rectangular, but may be circular or any other shape as long as it can be electrically connected to the electronic component (circuit component) to be mounted. .

第 1乃至第 8の導体ラン ドは等間隔で一列に配置されている。 また、 第 9乃至 第 1 6の導体ラン ドは、 第 1及び第 9の導体ラン ドが対角上にあり且つ第 8及び 第 1 6の導体ラン ドが対角上にあるように、 等間隔で一列に配置される。  The first to eighth conductor lands are arranged in a line at equal intervals. The ninth to sixteenth conductor lands are arranged such that the first and ninth conductor lands are on a diagonal and the eighth and sixteenth conductor lands are on a diagonal. They are arranged in a line at intervals.

第 8の導体ラン ドは導体パターン 8 Aを介してグランド (G N D ) に接続され ており、 第 1 6の導体ラン ドは導体パターン 1 6 Aを介して電源線 (V c c ) に 接続されている。 第 7及び第 8の導体ラン ド間は接続パターン 2 0により接続さ れており、 第 1 5及び第 1 6の導体ラン ド間は接続パターン 2 2により接続され ている。 また、 後述する各種 T T L素子の空き端子処理に対応すべく、 第 3、 第 5、 第 6、 第 1 0、 第 1 1、 第 1 3及び第 1 4の導体ラン ドは、 それそれ、 導体 パターン 3 A , 5 A , 6 A , 1 0 Α , 1 1 A , 1 3 A及び 1 4 Aによりグラン ド に接続されている。  The eighth conductor land is connected to ground (GND) via conductor pattern 8A, and the 16th conductor land is connected to power supply line (Vcc) via conductor pattern 16A. I have. The seventh and eighth conductor lands are connected by a connection pattern 20, and the 15th and 16th conductor lands are connected by a connection pattern 22. Also, in order to cope with the processing of vacant terminals of various TTL elements described later, the third, fifth, sixth, tenth, eleventh, thirteenth, and fourteenth conductor lands are Patterns 3 A, 5 A, 6 A, 10 A, 11 A, 13 A, and 14 A are connected to ground.

ここで、 第 7及び第 8の導体ラン ド間を接続パターン 2 0により接続し、 第 1 5及び第 1 6の導体ランド間を接続パターン 2 2 により接続しているのは、 種々 の回路部品に対応することを可能にするためである。 具体的には、 例えば電子回 路の変更に良く用いられる T T L素子には多くの種類があり、 用いられる T T L 素子に応じてグランド及び電源線の配置が異なる。 T T L素子は 1 4ピン ( 7 X 2列) であるのに対して、 本実施形態では、 図 1 に示されるように、 プリ ン ト配 線板は 1 6の導体ラン ド ( 8 X 2列) を有しているので、 T T L素子の種類に応 じて実装位置を変えることによって、 容易にグラン ド及び電源線の配置の違いに 対応することができる。  The connection between the seventh and eighth conductor lands by the connection pattern 20 and the connection between the 15th and 16th conductor lands by the connection pattern 22 are caused by various circuit components. This is because it is possible to respond to Specifically, for example, there are many types of TTL elements frequently used for changing an electronic circuit, and the arrangement of the ground and the power supply line differs depending on the TTL element used. While the TTL element has 14 pins (7 × 2 rows), in the present embodiment, as shown in FIG. 1, the printed wiring board has 16 conductor lands (8 × 2 rows). ), The mounting position can be changed according to the type of TTL element, so that differences in the layout of ground and power supply lines can be easily accommodated.

このように本実施形態では、 第 1乃至第 1 6の導体ラン ドは、 これらの一部 (第 1乃至第 7並びに第 1 0乃至第 1 6の導体ラン ド又は第 2乃至第 8並びに第 9乃至第 1 5の導体ランド) が回路素子 ( 1 4ピンの T T L素子) と接続される ように設けられている。 よ り特定的には、 第 1乃至第 1 6の導体ランドは、 回路 素子の種類に応じて接続される導体ラン ドが異なるように設けられている。 従つ て、 回路素子の種類に応じてプリ ント配線板への実装位置を変えることによって- 容易にグランド及び電源線の配置の違いに対応することができる。 As described above, in the present embodiment, the first to sixteenth conductor lands are a part of them (the first to seventh and tenth to sixteenth conductor lands, or the second to eighth and ninth conductor lands). The ninth to fifteenth conductor lands are provided so as to be connected to the circuit elements (14-pin TTL elements). More specifically, the first to sixteenth conductor lands are provided such that the conductor lands to be connected are different depending on the type of the circuit element. Therefore, by changing the mounting position on the printed wiring board according to the type of circuit element, It is possible to easily cope with the difference in arrangement of the ground and the power supply line.

図 2 A— 2 Eを参照すると、 図 1に示されるプリ ン ト配線板に実装可能な回路 素子 (電子部品) として、 T T L素子が例示されている。 各素子のパッケージは 共通であり、 ここでは、 端子 1乃至 1 4が設けられている。 端子 1乃至 7は等間 隔で一列に配置されている。 また、 端子 8乃至 1 4は、 端子 1及び 8が対角上に あり且つ端子 7及び 1 4が対角上にあるように、 等間隔で一列に配置される。 端 子 7はグランド ( GND ) に接続され、 端子 1 4は電源線 ( V c c ) に接続され て各素子は使用される。  Referring to FIGS. 2A-2E, a TTL element is illustrated as a circuit element (electronic component) mountable on the printed wiring board shown in FIG. The package of each element is common, and here, terminals 1 to 14 are provided. The terminals 1 to 7 are arranged in a line at equal intervals. Also, the terminals 8 to 14 are arranged in a line at equal intervals so that the terminals 1 and 8 are on a diagonal and the terminals 7 and 14 are on a diagonal. Terminal 7 is connected to ground (GND), and terminal 14 is connected to the power supply line (Vcc), and each element is used.

図 2 Aは各々回路素子内の回路としての 4つの NANDゲートを有する 「 0 0」 型の T T L素子を示しており、 例えば、 S N 7 4AS 0 0 (QUAD RUP L E 2— I NP UT P O S I T I VE— NAND GAT E S) がこれに相 当する。  FIG. 2A shows a “00” type TTL device having four NAND gates as circuits in the circuit device, for example, SN 7 4AS 00 (QUAD RUP LE 2—I NP UT POSITI VE— NAND GAT ES) is equivalent to this.

図 2 Bは各々回路素子内の回路としての 4つの NORゲ一トを有する 「 0 2」 型の T T L素子を示しており、 例えば、 S N 7 4 A S 0 2 (QUAD RU P L E 2— I NP UT P O S I T I VE— NO R GAT E S ) がこれに相当する。 図 2 Cは各々回路素子内の回路としての 6つのインパ一タを有する 「 0 4」 型 の T T L素子を示しており、 例えば、 S N 7 4A S 0 4 (HEX I NV E R T E R S ) がこれに相当する。  FIG. 2B shows a “02” type TTL element having four NOR gates as circuits in the circuit element, for example, SN 74 AS 02 (QUAD RU PLE 2—I NP UT POSITI VE—NO R GAT ES) corresponds to this. Figure 2C shows a `` 04 '' type TTL element with six impellers each as a circuit in the circuit element, for example, SN 74A S 04 (HEX I NV ERTERS) I do.

図 2 Dは各々回路素子内の回路としての 4つの ANDゲートを有する 「 0 8」 型の T T L素子を示しており、 例えば、 S N 7 4A S 0 8 (QUAD RUP L E 2— I NP UT P O S I T I VE— AND GAT E S) がこれに相当する。 図 2 Eは各々回路素子内の回路としての 4つの ORゲー トを有する 「3 2」 型 の T T L素子を示しており、 例えば、 S N 7 4A S 3 2 (QUAD RUP L E 2— I NP UT P O S I T I V E— O R GAT E S) がこれに相当する。 図 3は図 2 Dに示される 「0 8」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す図であり、 この図を用いて本発 明による回路素子の実装方法の一例を説明する。  FIG. 2D shows a “08” type TTL element having four AND gates as circuits in the circuit element, for example, SN 7 4A S 08 (QUAD RUP LE 2—I NP UT POSITI VE — AND GAT ES) is the equivalent. FIG. 2E shows a “32” type TTL device having four OR gates each as a circuit in the circuit device. For example, SN 7 4A S 3 2 (QUAD RUP LE 2—I NP UT POSITIVE) — OR GAT ES) is equivalent to this. Fig. 3 is a diagram showing an example of the connection state when the "08" type TTL element shown in Fig. 2D is mounted on the printed wiring board shown in Fig. 1. An example of a method for mounting a circuit element according to the present invention will be described.

T T L素子は、 その端子 1乃至 7がそれそれ第 2乃至第 8の導体ラン ドに接続 され、 且つ、 端子 8乃至 1 4がそれぞれ第 9乃至第 1 5の導体ラン ドに接続され るように、 プリ ン ト配線板に実装される。 本実施形態では、 T T L素子の空き端 子処理 (各 ANDゲートの少なく とも一方の入力端子が必ずグラン ドに接続され るようにすること) を考慮してプリ ン ト配線板のパターンが構成されているので、 第 7の導体ラン ド (端子 6 ) を開放するために接続パターン 2 0を切断するだけ で、 改造の準備が完了する。 In the TTL element, terminals 1 to 7 are respectively connected to the second to eighth conductor lands, and terminals 8 to 14 are respectively connected to ninth to 15th conductor lands. Mounted on the printed wiring board as shown. In the present embodiment, the pattern of the printed wiring board is configured in consideration of the free terminal processing of the TTL element (at least one input terminal of each AND gate is always connected to ground). Since the connection pattern 20 is simply cut to open the seventh conductor land (terminal 6), preparation for remodeling is completed.

例えば、 第 2乃至第 4の導体ラン ド (端子 1乃至 3 ) に接続されている 1つの ANDゲートを用いてこのプリ ン ト配線板上に具現化されている電子回路を変更 しょう とする場合には、 前述した改造の準備の完了後に、 導体パターン 3 Aを切 断すると共に、 第 2乃至第 4の導体ラン ドに対して図中破線で示されるようにそ れそれ布線を行う。 このように本実施形態では、 極めて容易に電子回路の変更を 行うことができ、 それによ りコンピュー夕端末等の電子機器を簡単に改造するこ とができる。  For example, when an electronic circuit embodied on this printed wiring board is to be modified using one AND gate connected to the second to fourth conductor lands (terminals 1 to 3) After completion of the preparation for the above-described modification, the conductor pattern 3A is cut off, and the second to fourth conductor lands are individually wired as indicated by broken lines in the figure. As described above, in the present embodiment, the electronic circuit can be very easily changed, and thereby the electronic device such as the computer terminal can be easily remodeled.

図 4は図 2 Dに示される 「 0 8」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の他の例を示す図である。 図 3に示されて いる例と同様に、 第 2乃至第 4の導体ラン ド (端子 1乃至 3 ) に接続されている 1つの ANDゲートを用いてこのプリ ント配線板上に具現化されている電子回路 を変更しょう とする場合において、 その AN Dゲートの第 3の導体ラン ド (端子 2 ) に接続されている一方の入力が口一レベルで一定であるときには、 導体パ夕 —ン 3 Aの切断及び第 3の導体ラン ドへの布線が不要になる。 従って、 改造のた めの作業は、 接続パターン 2 0の切断並びに第 2及び第 4の導体ラン ドへの布線 で足り、 電子回路の変更が更に容易になる。  FIG. 4 is a diagram showing another example of a connection state when the “08” type TTL element shown in FIG. 2D is mounted on the printed wiring board shown in FIG. As in the example shown in FIG. 3, the circuit is embodied on this printed wiring board using one AND gate connected to the second to fourth conductor lands (terminals 1 to 3). If one of the inputs connected to the third conductor land (terminal 2) of the AND gate is constant at the mouth level, the conductor pattern is The cutting of A and the wiring to the third conductor land become unnecessary. Therefore, the work for the remodeling can be performed by cutting the connection pattern 20 and arranging the second and fourth conductor lands, thereby making it easier to change the electronic circuit.

図 3及び 4の実施形態では、 「 0 8」 型の T T L素子の場合について説明した が、 「 0 0」 型あるいは 「 3 2」 型の T T L素子の場合でも同様に本発明を実施 することができる。  In the embodiments of FIGS. 3 and 4, the case of the “08” type TTL element has been described. However, the present invention can be similarly applied to the case of the “08” type or “32” type TTL element. it can.

図 5は図 2 Cに示される 「 0 4」 型の T T L素子を図 1に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す図である。 T T L素子は、 その 端子 1乃至 7がそれぞれ第 1乃至第 7の導体ラン ドに接続され、 且つ、 端子 8乃 至 1 4がそれぞれ第 1 0乃至第 1 6の導体ラン ドに接続されるように、 プリ ント 配線板に実装される。 本実施形態では、 T T L素子の空き端子処理 (各イ ンバー 夕の入力端子及び出力端子の少なく とも一方が必ずグラン ドに接続されるように すること) を考慮してプリ ント配線板のパターンが構成されているので、 導体パ ターン 6 A , 1 O A及び 1 4 Aを切断するだけで、 改造の準備が完了する。 これ により、 任意のイ ンバー夕に対する布線を行うだけで、 そのインバー夕を用いて、 このプリ ン ト配線板上に具現化されている電子回路を極めて容易に変更すること ができる。 その結果、 コンピュータ端末等の電子機器を簡単に改造することがで きる。 FIG. 5 is a diagram showing an example of a connection state when the “04” type TTL element shown in FIG. 2C is mounted on the printed wiring board shown in FIG. The TTL element has terminals 1 to 7 connected to the first to seventh conductor lands, respectively, and terminals 8 to 14 connected to the 10th to 16th conductor lands, respectively. Then, it is mounted on the printed wiring board. In the present embodiment, the processing of the empty terminals of the TTL element (each inverter) The input and output terminals at least one of them should always be connected to the ground), and the conductor pattern 6 A, 1 OA and Just cut the 14 A and you're ready to convert. Thus, the electronic circuit embodied on the printed wiring board can be extremely easily changed by simply performing wiring for an arbitrary inverter using the inverter. As a result, electronic devices such as computer terminals can be easily remodeled.

図 6は図 2 Bに示される 「 0 2」 型の T T L素子を図 1 に示されるプリ ン ト配 線板に実装した場合における接続状態の例を示す図である。 T T L素子は、 その 端子 1乃至 7がそれそれ第 1乃至第 7の導体ラン ドに接続され、 且つ、 端子 8乃 至 1 4がそれそれ第 1 0乃至第 1 6の導体ラン ドに接続されるように、 プリ ン ト 配線板に実装される。 本実施形態では、 T T L素子の空き端子処理 (各 N O Rゲ 一トの少なく とも一方の入力端子が必ずグラン ドに接続されるようにすること) を考慮してプリ ン ト配線板のパターンが構成されているので、 第 1 5の導体ラン ド (端子 1 3 ) を開放するために接続パターン 2 2を切断するだけで、 改造の準 備が完了する。 これにより、 任意の N〇 Rゲートに対する布線を行うだけで (図 示はしないが必要に応じて導体パターンの切断が行われる) 、 その N O Rゲート を用いて、 このプリ ン ト配線板上に具現化されている電子回路を極めて容易に変 更することができる。 その結果、 コンピュータ端末等の電子機器を簡単に改造す ることができる。  FIG. 6 is a diagram showing an example of a connection state when the “02” type TTL element shown in FIG. 2B is mounted on the printed wiring board shown in FIG. The TTL element has terminals 1 to 7 connected to the first to seventh conductor lands, respectively, and terminals 8 to 14 connected to the 10th to 16th conductor lands, respectively. Mounted on the printed wiring board as shown. In the present embodiment, the pattern of the printed wiring board is configured in consideration of the TTL element free terminal processing (at least one input terminal of each NOR gate must be connected to the ground). Since the connection pattern 22 is cut to open the 15th conductor land (terminal 13), the preparation for remodeling is completed. As a result, wiring can be performed only on an arbitrary N〇R gate (not shown, but the conductor pattern is cut off as necessary), and the NOR gate is used on this printed wiring board. The embodied electronic circuit can be changed very easily. As a result, electronic devices such as computer terminals can be easily remodeled.

図 7及び図 8を参照する と、 従来のプリ ン ト配線板の一例及びそのプリ ン ト配 線板を用いた回路部品の実装方法の一例がそれそれ示されており、 これらの図を 用いて本発明の技術的優位性をよ り特定的に説明する。  Referring to FIGS. 7 and 8, one example of a conventional printed wiring board and an example of a method for mounting circuit components using the printed wiring board are shown. The technical advantages of the present invention will be described more specifically.

このプリ ント配線板は、 図 1 に示されるのと同様に、 回路基板の外層上に形成 された第 1乃至第 1 6の導体ラン ドを有している。 第 1乃至第 8の導体ラン ドは 等間隔で一列に配置されており、 第 9乃至第 1 6の導体ラン ドは、 第 1及び第 9 の導体ラン ドが対角上にあり且つ第 8及び第 1 6の導体ラン ドが対角上にあるよ うに、 等間隔で一列に配置されている。 第 8の導体ラン ドは導体パターン 8 Aを 介してグランド ( G N D ) に接続されており、 第 1 6の導体ランドは導体パター ン 1 6 Aを介して電源線 (V c c ) に接続されている。 This printed wiring board has first to sixteenth conductor lands formed on the outer layer of the circuit board, as shown in FIG. The first to eighth conductor lands are arranged in a line at equal intervals, and the ninth to sixteenth conductor lands are arranged such that the first and ninth conductor lands are on a diagonal and the eighth to eighth conductor lands. And the 16th conductor lands are arranged in a line at equal intervals so that they are diagonally arranged. The eighth conductor land is connected to the ground (GND) via the conductor pattern 8A, and the 16th conductor land is connected to the conductor pattern. It is connected to the power line (V cc) via pin 16A.

図 8は回路部品として例えば図 2 Dに示される T T L素子を図 7に示されるプ リ ン ト配線板に実装した場合における接続状態の例を示す図である。 T T L素子 は、 その端子 1乃至 7がそれそれ第 2乃至第 8の導体ラン ドに接続され、 且つ、 端子 8乃至 1 4がそれぞれ第 9乃至第 1 5の導体ラン ドに接続されるように、 プ リ ン ト配線板に実装される。  FIG. 8 is a diagram showing an example of a connection state when, for example, the TTL element shown in FIG. 2D is mounted on the printed wiring board shown in FIG. 7 as a circuit component. The TTL element has terminals 1 to 7 connected to the second to eighth conductor lands, respectively, and terminals 8 to 14 connected to the ninth to 15th conductor lands, respectively. , Mounted on the printed wiring board.

例えば、 第 2乃至第 4の導体ラン ド (端子 1乃至 3 ) に接続されている 1つの A N Dゲー トを用いてこのプリ ン ト配線板上に具現化されている電子回路を変更 しょう とする場合には、 先ず、 その回路 (当該 A N Dゲー ト) の電源を確保する ために、 第 1 5の導体ラン ドと第 1 6の導体ラン ドの間の布線が必要になる。 ま た、 その回路自体の配線と して第 2乃至第 4の導体ランドへの布線が必要になる と共に、 未使用回路の空き端子処理のために、 第 5、 第 6、 第 1 0、 第 1 1、 第 1 3及び第 1 4の導体ラン ドへの布線が必要になる。 従って、 図 8に破線で示さ れるように、 全部で 1 0の布線が必要になる。  For example, try to change the electronic circuit embodied on this printed circuit board using one AND gate connected to the second to fourth conductor lands (terminals 1 to 3) In such a case, first, wiring between the 15th conductor land and the 16th conductor land is required to secure the power supply of the circuit (the AND gate). In addition, wiring to the second to fourth conductor lands is required as wiring for the circuit itself, and the fifth, sixth, tenth, Wiring to the 11th, 13th and 14th conductor lands is required. Therefore, as shown by the broken line in FIG. 8, a total of 10 wirings are required.

これに対して、 本発明では、 例えば図 3の実施形態では、 第 2乃至第 4の導体 ラン ドに対する 3本の布線並びにパターン 3 A及び 2 0のカッ トのみで足り、 極 めて容易に電子回路を変更することができる。 更に、 図 4の実施形態では、 第 3 の導体ラン ドへの布線及びパターン 3 Aのカッ トも不要になり、 2本の布線及び 1つのパターンカツ トで足り、 更に電子回路の変更が容易になる。 産業上の利用可能性  On the other hand, in the present invention, for example, in the embodiment of FIG. 3, only the three wirings and the cuts of the patterns 3A and 20 for the second to fourth conductor lands are sufficient, which is extremely easy. The electronic circuit can be changed. Further, in the embodiment of FIG. 4, the wiring to the third conductor land and the cutting of the pattern 3A are not required, and two wirings and one pattern cut are sufficient, and furthermore, the electronic circuit is changed. Becomes easier. Industrial applicability

以上説明したように、 本発明によると、 電子機器を改造する上で電子回路の変 更が容易なプリ ン ト配線板及びそのプリ ン ト配線板を用いた回路素子の実装方法 の提供が可能になる。 また、 本発明によると、 そのプリ ン ト配線板を用いてコン ピュー夕端末等の電子機器を簡単に改造することができるので、 製品の開発スピ ―ドの向上に寄与するところが大きい。  As described above, according to the present invention, it is possible to provide a printed wiring board in which an electronic circuit can be easily changed when remodeling an electronic device, and a method for mounting a circuit element using the printed wiring board. become. Further, according to the present invention, an electronic device such as a computer terminal can be easily remodeled using the printed wiring board, which greatly contributes to an improvement in the speed of product development.

Claims

請 求 の 範 囲 The scope of the claims 1 . 複数の端子を有する回路素子が実装されるべきプリ ン ト配線板において、 前記プリ ン ト配線板は、 複数種類の回路素子を択一的に接続可能な複数の導体 ラン ドと、 前記複数の導体ランドのうちの一部とグラン ドとを接続する複数の配 線とを有し、 1. In a printed wiring board on which a circuit element having a plurality of terminals is to be mounted, the printed wiring board includes a plurality of conductor lands capable of selectively connecting a plurality of types of circuit elements; A plurality of wires connecting a part of the plurality of conductor lands and the ground, 前記配線は、 前記接続される回路素子内の回路の端子の少なく とも 1つがグラ ン ドに接続されるようにするときに、 前記配線のいずれかを切断して前記回路の 端子の少な く とも 1つがグラン ドに接続可能なように、 前記複数種類の回路素子 に対応して設けられていることを特徴とするプリ ン ト配線板。  When at least one of the terminals of the circuit in the circuit element to be connected is connected to the ground, at least one of the wirings is cut to disconnect at least one of the terminals of the circuit. A printed wiring board, which is provided corresponding to the plurality of types of circuit elements so that one can be connected to a ground. 2 . 前記導体ラン ドは前記導体ラン ドの一部が前記回路素子の端子と接続される ように設けられていることを特徴とする請求の範囲第 1項記載のプリ ン ト配線板, 2. The printed wiring board according to claim 1, wherein the conductor land is provided such that a part of the conductor land is connected to a terminal of the circuit element. 3 . 前記導体ラン ドは回路素子の種類に応じて接続に使用される導体ラン ドが異 なるように設けられていることを特徴とする請求の範囲第 2項記載のプリ ン ト配 線板。 3. The printed wiring board according to claim 2, wherein the conductor land is provided so that a conductor land used for connection differs according to a type of a circuit element. . 4 . 複数種類の回路素子を択一的に接続可能な複数の導体ラン ドと、 前記複数の 導体ランドのうちの一部とグラン ドとを接続する複数の配線とを有し、 複数の端 子を有する回路素子が実装されるべきプリ ン ト配線板に前記回路素子を実装する 工程と、 4. A plurality of terminals having a plurality of conductor lands capable of selectively connecting a plurality of types of circuit elements, and a plurality of wirings connecting a part of the plurality of conductor lands and the ground. Mounting the circuit element on a printed wiring board on which the circuit element having the chip is to be mounted; 前記配線のいずれかを切断して前記回路素子内の回路の端子の少なく とも 1つ をグラン ドに接続する工程とを有する回路素子の実装方法。  Cutting at least one of the wirings and connecting at least one of the circuit terminals in the circuit element to ground.
PCT/JP2000/002661 2000-04-24 2000-04-24 Printed wiring board and method of mounting circuit element on this wiring board Ceased WO2001082664A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/002661 WO2001082664A1 (en) 2000-04-24 2000-04-24 Printed wiring board and method of mounting circuit element on this wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/002661 WO2001082664A1 (en) 2000-04-24 2000-04-24 Printed wiring board and method of mounting circuit element on this wiring board

Publications (1)

Publication Number Publication Date
WO2001082664A1 true WO2001082664A1 (en) 2001-11-01

Family

ID=11735960

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/002661 Ceased WO2001082664A1 (en) 2000-04-24 2000-04-24 Printed wiring board and method of mounting circuit element on this wiring board

Country Status (1)

Country Link
WO (1) WO2001082664A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497589A (en) * 1990-08-16 1992-03-30 Nec Corp Printed wiring board
JPH0582958A (en) * 1991-09-19 1993-04-02 Fuji Electric Co Ltd Circuit formation method on printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497589A (en) * 1990-08-16 1992-03-30 Nec Corp Printed wiring board
JPH0582958A (en) * 1991-09-19 1993-04-02 Fuji Electric Co Ltd Circuit formation method on printed circuit board

Similar Documents

Publication Publication Date Title
TWI725902B (en) Semiconductor package structure and manufacturing method thereof
KR100258263B1 (en) ARRANGEMENT OF PADS AND THROUGH-HOLES FOR SEMICONDUCTOR PACKAGES
US6992376B2 (en) Electronic package having a folded package substrate
JPH07111971B2 (en) Method of manufacturing integrated circuit device
US20020139571A1 (en) Semiconductor device and process for fabricating the same
US6449170B1 (en) Integrated circuit package incorporating camouflaged programmable elements
TWI751630B (en) Printed circuit board connection for integrated circuits using two routing layers
US7384566B2 (en) Fabrication method for printed circuit board
JP2000349191A (en) Semiconductor device and wiring circuit device
WO2001082664A1 (en) Printed wiring board and method of mounting circuit element on this wiring board
JPWO2001082664A1 (en) Printed wiring board and method for mounting circuit elements using the printed wiring board
JP2837521B2 (en) Semiconductor integrated circuit device and wiring change method thereof
TWI586231B (en) Power and signal extenders and boards
KR20070076188A (en) Semiconductor chip package equipped with an electronic device and integrated circuit module having the same
JPH0230176A (en) Semiconductor integrated circuit
JPS60160641A (en) Mounting of leadless package ic for board
US7663894B2 (en) Multilayer printed wiring board
KR20090016257A (en) Package Substrate Removed Plating Leads and Manufacturing Method Thereof
KR100349561B1 (en) Lsi package and inner lead wiring method thereof
WO2003049183A2 (en) Optimum power and ground bump pad and bump patterns for flip chip packaging
JP2000114378A (en) Semiconductor circuit element having easily changeable circuit wiring and method of manufacturing the same
JPH04246857A (en) Semiconductor integrated circuit device
JPS6225437A (en) Multilayer interconnection substrate
JPH1187909A (en) Ic connecting apparatus and auxiliary board for connecting ic
HK40064093A (en) Printed circuit board connection for integrated circuits using two routing layers

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 578164

Kind code of ref document: A

Format of ref document f/p: F