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WO2001079867A1 - Procede de fabrication d'une carte de test de sondes - Google Patents

Procede de fabrication d'une carte de test de sondes Download PDF

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Publication number
WO2001079867A1
WO2001079867A1 PCT/US2000/009710 US0009710W WO0179867A1 WO 2001079867 A1 WO2001079867 A1 WO 2001079867A1 US 0009710 W US0009710 W US 0009710W WO 0179867 A1 WO0179867 A1 WO 0179867A1
Authority
WO
WIPO (PCT)
Prior art keywords
vias
exit
probe
routing
junctions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/009710
Other languages
English (en)
Inventor
Stephen Evans
A. Paul Martel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wentworth Laboratories Inc
Original Assignee
Wentworth Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wentworth Laboratories Inc filed Critical Wentworth Laboratories Inc
Priority to PCT/US2000/009710 priority Critical patent/WO2001079867A1/fr
Publication of WO2001079867A1 publication Critical patent/WO2001079867A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/029—Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Definitions

  • This invention relates generally to a method of making a probe test board for vertical pin probing of semiconductors and integrated circuits, and more particularly a method for customizing a universal interface for vertical pin probing of a particular semiconductor device or integrated circuit.
  • Printed circuit boards are manufactured by creating an artwork and etching copper away from the non-current carrying portions of the board. This process is non-reversible; hence, once the printed circuit board is etched it is then customized or "dedicated” to a certain semiconductor device/integrated circuit and cannot be changed without modification of the artwork and re- fabrication of the printed circuit board.
  • This type of probe holder which is sometimes referred to as a vertical-pin integrated circuit probing device and sometimes as a hybrid buckling beam probe has been improved by IBM and other manufacturers.
  • Such a device is manufactured and sold by applicant's assignee as a COBRA® probe, and is used in conjunction with a printed circuit test board, which is connected in test circuit relationship with the external test equipment for testing the integrated circuit.
  • an interconnection device commonly known as a "space transformer” is generally employed.
  • space transformers are shown in the prior art, for example in U.S. Patent 4,038,599 issued July 26, 1977 to Bove et al., U.S. Patent 3,654,585 issued April 4, 1972 to Wickersham, U.S. Patent 3,911,361 issued October 7, 1975 to Bove et al., and U.S. Patent 4,901,013 issued February 13, 1990 to Benedetto et al.
  • a common type of prior art space transformer comprises a wired interface used together with an etched "dedicated" printed circuit board is depicted in FiGS. la and lb of the present application.
  • FIG. la and FlG. lb schematically illustrate a silicon wafer 10 having a number of integrated circuit devices thereon with contact pads 12 to be probed.
  • Multiple power, ground and signal potentials are supplied from test equipment through connectors 14 to "pogo pads" on the outer periphery of a printed circuit board 16.
  • a particular pattern of test circuit dedicated to a particular pattern of contact pads 12 on the integrated circuit device is provided by means of traces 18 etched into or deposited on the printed circuit board.
  • a second set of wire leads 20 connected to the etched traces 18 terminate on the underside of board 16, so as to make contact at 19 with the upper ends of probe pins 22 held in a probe assembly 24.
  • FIGS, la and lb While the simple construction of FIGS, la and lb may have been adequate for integrated circuit devices in the past, the complexity of the test circuits and density of the devices on the silicon wafer has greatly challenged the probe card manufacturer. As the probe card designs become more complex, they become more expensive. Once dedicated to a particular integrated circuit, they can no longer be used if the integrated circuit is modified.
  • the new tester is capable of 1024 signals in addition to all required power supplies and grounds.
  • the older generation of testers may have been capable of 512 signals and required power supplies and grounds.
  • the new tester dictates that the layout of vias must now be capable of routing 1024 signals rather than 512 signals and therefore the printed circuit must be capable of routing any of 1024 signals to any of 1024 pin locations.
  • the aforementioned space transformer designs require a separate member to be attached to the center of the printed circuit board, and provision made for a conductive path between the trace termination on the printed circuit board to the underside of the board.
  • the conductive path terminates at a pin location in a contact pattern or "footprint", where contact is made with the probe pins of the probe assembly. It would be desirable to simplify the process for running the final conductive path to the footprint or probe pin contact location.
  • one object of the present invention is to provide an improved method for customizing a multiple layer electrical interface for vertical pin probing of semiconductors and integrated circuits.
  • Another object of the invention is to provide an improved method of manufacturing a customized electrical interface/ space transformer for use with vertical pin probe devices. Another object of the invention is to reduce the cost associated with converting from one pin-out configuration to another when testing integrated circuits.
  • Another object of the invention is to reduce the cost of increasingly complex test circuit designs on a printed circuit probe card.
  • a universal design of a multiple layer printed circuit board incorporates a series of entry vias leading to internal trace layers, a series of exit vias located in a central portion of the board having a conductive coating, and a series of routing vias universally interconnecting the entry vias with the exit vias through spaced junctions.
  • the junctions are located on the routing vias so that junctions may be selectively severed by means of a laser or high pressure water cutting system or other fine line cutting tool or mechanism to customize the circuit design.
  • the coating is similarly cut to provide traces to probe pin contact points.
  • the preferred method for making a probe test board for vertical pin probing comprises: providing a laminated structure of alternating insulating layers and trace layers, including an exterior insulating layer with a central portion having a continuous conductive coating thereon, the laminated structure having entry vias, routing vias and exit vias, the exit vias being disposed within the central portion, all of the entry vias being connected to all of the exit vias through spaced junctions on the routing vias; establishing circuit connections between entry vias and exit vias by severing all junctions but two on each of the routing vias; establishing probe pin contact points at a preselected location within the central portion which correspond to the positions of contact pads of an integrated circuit device to be probed; and providing probe contact traces between exit vias and probe pin contact points by cutting through the continuous conductive layer to leave conductive areas enclosing an exit via, a probe contact trace and a probe pin contact point.
  • FlG. la is a schematic side elevational view in cross section of a prior art wafer probe test apparatus utilizing a wired space transformer and vertical pin probing device,
  • FlG. lb is a plan view of the prior art wired space transformer printed circuit board
  • FlGS. 2 - 6 are drawings of the invention before customizing or dedicating to test a specific integrated circuit or semiconductor device, in which:
  • FlG. 2 is a top plan view of a universal multilayer electrical interface according to the present invention.
  • FlG. 3 is a bottom plan view of the electrical interface of FlG. 2
  • FlG. 4 is a side elevational view in cross section of a portion of the interface of FlG. 2 taken through the routing vias
  • FlG. 5a through FlG. 5f are top plan views of successive layers of traces on and within the multiple layer interface of FlG. 2, confined to the portion within phantom line V of FlG. 2,
  • FlG. 6 is a schematic perspective view of routing vias and connected traces in successive layers
  • FlGS. 7 - 10 are drawings of the invention after dedicating the interface to a particular integrated circuit, in which:
  • FlG. 7 is a side elevational view in cross section similar to FlG. 4
  • FlG. 8 is a perspective view of the routing vias similar to FlG. 6
  • FlG. 9 is a bottom plan view of a portion of the interface continued to the portion enclosed by phantom line IX in FlG. 3,
  • FlG. 9a is an enlarged detail view of a portion of FlG. 9, and FlG. 10 is a schematic circuit diagram, showing the interconnections between traces.
  • the space transformer 16 provides a test circuit connection between connectors 14 of the test equipment at the periphery of the board 16 to contact points 19 on the underside of the board, which make contact with the probe pins 22.
  • the circuit connections between the upper ends of probe pins 22 and the contact pads 12 of the device under test are preselected and dedicated to the particular device under test, these being in usual practice a group of integrated circuits on a silicon wafer 10.
  • the present invention is an improvement over the board 16 with its dedicated circuit and wired connections to contact points 19.
  • Interface 26 is designed to provide a particular layout of vias and internal trace layers which provide the ability to customize the printed circuit board for optimum performance associated with the testing of semiconductors and integrated circuits.
  • Interface 26 comprises an outer ring of groups of "pogo" pads 28, which are arranged to interface with a specific semiconductor, test equipment model and type, so as to provide multiple power, ground and signal sources to pogo pads 28.
  • Concentrically disposed inside of the ring of pogo pads 28 is a ring of groups of entry vias 30, each pogo pad in group 28 being connected to an entry via in group 30 by a respective trace 29 deposited on the insulating surface of interface 26.
  • a concentric ring of groups of routing vias 32 Disposed inside of the ring of entry vias 30 is a concentric ring of groups of routing vias 32, which are universally interconnected with the entry vias 30 in a manner to be explained.
  • Inward of the group of routing vias 32 is a concentric ring of groups of exit vias 34.
  • Each of the routing vias in 32 is connected only to a respective exit via 34 by means of a conductive trace such as the 36 applied to the surface of the interface 26 in the conventional manner.
  • interface 26 shown in FlG. 3 shows the same concentric rings of groups of pogo pads 28, entry vias 30, routing vias 32 and exit vias 34.
  • the exit vias 34 lie inside a circle of copper cladding 38 which is applied on the surface of the insulating layer 40 of interface 26.
  • a series of mounting holes 42 provide means to bolt a vertical pin probe device to interface 26.
  • the interface 26 shown in the drawings is greatly simplified in order to reduce the complexity of the drawings so that the invention may be more clearly understood.
  • the number of layers in the multiple layer electrical interface has been reduced in the description to depict only four internal layers, whereas eight or more internal layers may be used in actual practice.
  • Reference to FlG. 4 illustrates a simplified form of multiple layer interface, taken through the group of routing vias 32 along lines IV - IV of FlG. 2.
  • the interface 26 is a laminated structure of insulating layers including exterior layers 42, 43 and interior layers 44, 45, 46.
  • the insulating layers may be composed of fiberglass, having a thickness on the order of .006 inches.
  • Interposed between the insulating layers are interior trace layers of multiple individual traces 47, 48, 49, 50.
  • the trace layers may be composed of copper, having a thickness on the order of .002 inches.
  • On top of the top exterior insulating layer 42 is a layer of traces, such as the previously described trace 36 leading from a routing via to an exit via.
  • Each of the group of routing vias 32 comprises electrically conductive posts 51 - 54, preferably hollow tubes, extending through the insulation and held in place by expanded or swaged heads on either end.
  • Vias 51 - 54 serve not only to provide a transition connection from layer to layer, but also serve as universally connected, selectively disconnectable circuit routing devices according to the present invention.
  • Each of the internal trace layers is comprised of separate traces, such as the traces 47 - 50.
  • One of the traces 47 in the first internal layer depicted in FlG. 4 is connected to each of the four routing vias 51 - 54 at internal junctions 51a - 54a respectively.
  • One of the traces 48 in the second internal trace layer is connected to each of the routing vias 51 - 54 at internal junctions
  • One of the traces 49 in the third internal layer is connected to each of the routing vias 51 - 54 at internal junctions 51c - 54c respectively.
  • one of the traces 50 in the fourth internal layer is connected to each of the routing vias 51 - 54 at internal junctions 51d - 54d respectively (see FlG. 6).
  • the internal junctions are axially spaced along the via and also circumferentially spaced around the via.
  • FlG. 5a is the top exterior layer of traces, which are seen from the outside of the board.
  • FlG. 5b is the first interior layer showing that one of the entry vias 30 is connected by trace 47 to all of the routing vias 32.
  • FlG. 5C is the second interior layer showing that a different entry via 30 is connected by trace 48 to all of the routing vias 32.
  • FlG. 5d and 5e illustrate the connections by means of traces 49 and 50 from one of the entry vias to all of the routing vias 32 in that layer.
  • FlG. 5f illustrates the bottom exterior layer appearance. No connections are provided by traces prior to customization. However it should be noted that the group of exit vias 34 lie within the copper layer 38, whereon traces will be provided by laser cutting and removal of copper when the interface 26 is customized.
  • routing vias 51 - 54 are illustrated schematically to show the arrangement of the internal junctions 51a. -.54d which are spaced both circumferentially and axially on the vias.
  • the routing vias 51 - 54 are universally connected to the entry vias in each internal layer, so as to permit any of the internal traces 47 - 50 to be connected to any of the external traces 36 without interference with other circuit paths.
  • the universally connected vias are selectively disconnected by means of severing the unwanted internal junctions.
  • FlGS. 7 - 10 depict the same board after customization or dedication to a particular integrated circuit.
  • the interface 26 is customized by means of a laser or high pressure water cutting system or other fine line cutting tool or mechanism.
  • the design of the routing vias with internal junctions spaced along and around the via facilitates this process.
  • the routing via is designed such that a cutting tool may sever the via from one or all of the inner layers of the printed circuit board.
  • both the depth and the X- Y position of the laser beam or high pressure water cutting tool may be used to penetrate the laminated structure from the underside, as illustrated by the laser drilled opening 56, which severs junction 51a connecting via 51 to trace 47. (See also FlG. 8).
  • FlG. 9 depicts a portion of the interface enclosed by phantom line IX in FlG. 3.
  • FlG. 9 illustrates the path left by a computer guided laser cutting tool at reference numeral 56.
  • the path cut by the laser may be arcuate or along the lines of a polygon, as guided by a computer aided positioning device, and depending upon the circumferential spacing of internal junctions and upon the number and thickness of layers in the interface.
  • exit vias While selective severing of internal junctions at the routing vias enables a selected connection between one of the entry vias 30 and one of the exit vias 34, there remains the job of connecting an exit via to the pin-out pattern or "footprint" of the device under test. As previously noted, exit vias
  • the traces connecting an exit via 34 to a precise pin location which will be contacted by the vertical pin probing device is done by using laser, water or other means of cutting the continuous copper coating 38 to leave a trace between cuts.
  • Present printed circuit board technology is limited to an approximately .004 inches wide trace.
  • laser cutting technology to remove copper, leaving a trace, the width of the trace may be reduced to less than 50 microns.
  • the laser beam leaves a space between traces that is also less than 50 microns.
  • the pitch and trace width of a laser or water cut interface/printed circuit board is dictated by the minimum cutting beam width and the power of the laser cutting system itself.
  • individual traces are provided for each of the exit vias 34, one of which is shown at 58.
  • a customized interface 26 shows that one of the exit vias in group 34, indicated by reference numeral 60 is connected to a probe pin contact point 62.
  • Contact point 62 forms part of the "footprint" of the device under test, and will be contacted by the head of the probe pin in the vertical pin probing device attached to interface 26.
  • the trace 58 connects exit via 60 to probe pin contact point 62.
  • the trace 58 is formed by laser cutting on either side of the trace, around the contact point 62 and around the end of the exit via 60, so as to leave 60 and 62 connected together.
  • FIG. 10 A schematic circuit diagram is shown in FlG. 10. Four entry vias are shown as 30a, 30b, 30c, 30d. Four exit vias are shown as 34a, 34b, 34c, 34d.
  • the illustrated embodiment of the invention in the universally connected interface connects all of the routing vias to each of the entry vias, and then connects each of the routing vias only to a respective exit via.
  • the concept is equally applicable if all of the routing vias are connected to each of the exit vias, and then each of the routing vias is connected only to a respective entry via. In this case, the circuit paths between exit vias and routing vias would be laid out in separate layers while the connections between entry vias and routing vias could be laid out on one layer.
  • the universal interface may be customized for a particular "footprint" of the device under test, so as to connect any of the pogo pads at the periphery of the board to any of the probe pin contact locations.
  • the layout of the vias is consistent from one universal design to another. This is done to minimize the amount of custom software and maximize the output of the custom routing program. This consistency also minimizes the amount of tooling required to change from one universal interface blank to another, as all the mounting and tooling holes are consistent from one universal interface blank to another.
  • the universal interface is designed to the specifications of each semiconductor tester model.
  • the outer layers of the universal blank are all
  • plane which electrically shorts together all vias on the universal interface blank.
  • the routing vias also connect to any or all inner layers of the universal blank.
  • the output file from the auto-routing software, driving the cutting system, is then used to sever the vias from the "plane” and the inner layers of the universal interface blank.
  • Signal power and ground paths are then cut into the universal blank using the layout of vias as described. This enables the universal blank to be specifically dedicated to the pin-out of the semiconductor device by post-fabrication and customization of the universal interface blank, in such a manner that each signal, power and ground path is optimized for electrical performance.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Une conception universelle d'une carte de circuit imprimé à couches multiples comprend une série de trous de routage (51, 52, 53, 54) qui interconnectent une série de trous d'entrée (30a, 30b, 30c, 30d) avec une série de trous de sortie (34a, 34b, 34c, 34d). Les trous de routage connectent tous les trous d'entrée avec tous les trous de sortie à travers les jonctions (a, b, c, d) espacées sur les trous de routage. Les trous de sortie se trouvent dans une partie centrale (38) de la carte de circuit, qui comporte un revêtement en cuivre sur l'un des côtés. Les jonctions sont disposées sur le trou de manière à ce que les jonctions puissent être sélectivement détachées au moyen d'un système de coupe à laser ou à eau sous haute pression ou de tout autre outil ou mécanisme de coupe fine, et ce pour individualiser la conception du circuit en fonction d'un dispositif semi-conducteur ou circuit intégré particulier. Des tracés (58) sont créés, qui mènent depuis les trous de sortie (34) vers les points de contact de la pointe de sonde (62) grâce au découpage à travers le revêtement en cuivre au moyen d'outils de coupe fine similaires.
PCT/US2000/009710 2000-04-12 2000-04-12 Procede de fabrication d'une carte de test de sondes Ceased WO2001079867A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2000/009710 WO2001079867A1 (fr) 2000-04-12 2000-04-12 Procede de fabrication d'une carte de test de sondes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2000/009710 WO2001079867A1 (fr) 2000-04-12 2000-04-12 Procede de fabrication d'une carte de test de sondes

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Publication Number Publication Date
WO2001079867A1 true WO2001079867A1 (fr) 2001-10-25

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016139054A1 (fr) * 2015-03-03 2016-09-09 Feinmetall Gmbh Dispositif de contact électrique
CN113484560A (zh) * 2021-07-07 2021-10-08 上海泽丰半导体科技有限公司 一种晶圆及成品测试共用电路板及其设计方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0288801A2 (fr) * 1987-04-29 1988-11-02 International Business Machines Corporation Carte à sondes et procédé pour la prévoir avec des circuits reconfigurables
US5856636A (en) * 1997-03-03 1999-01-05 Sanso; David W. Electronic circuit prototype wiring board with visually distinctive contact pads

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0288801A2 (fr) * 1987-04-29 1988-11-02 International Business Machines Corporation Carte à sondes et procédé pour la prévoir avec des circuits reconfigurables
US5856636A (en) * 1997-03-03 1999-01-05 Sanso; David W. Electronic circuit prototype wiring board with visually distinctive contact pads

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016139054A1 (fr) * 2015-03-03 2016-09-09 Feinmetall Gmbh Dispositif de contact électrique
CN107407709A (zh) * 2015-03-03 2017-11-28 精炼金属股份有限公司 电接触装置
US10197620B2 (en) 2015-03-03 2019-02-05 Feinmetall Gmbh Electric contact device
CN113484560A (zh) * 2021-07-07 2021-10-08 上海泽丰半导体科技有限公司 一种晶圆及成品测试共用电路板及其设计方法

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