WO2001075789A1 - Method of manufacturing cof package - Google Patents

Abstract

A method of manufacturing a COF package comprises providing a resin film substrate with a hole for receiving a chip, providing an IC chip having electrodes, inserting the IC chip into the hole and fixing it with its electrodes exposed at the substrate surface, and forming a circuit pattern on the substrate surface for connection with the electrodes. The hole and the IC chip are tapered, and the IC chip is secured in the hole with sealant or adhesive.

Description

 Akeita »

 Manufacturing method of C 0 F package

 Technical field

 The present invention relates to a method for manufacturing a COF package such as a contactless ID card.

 Background technology

 Conventionally, C 0 F (Chip on Film), such as non-contact ID force and non-contact time. Packages are manufactured by various methods.

 As an example, the bumps (protrusion electrodes) of the IC chip are aligned with the electrodes of the antenna circuit formed on the resin film substrate, and then the IC chip is pressed to perform flip chip bonding. A method of filling the minute gaps (or minute gaps) between chips with a resin and sealing, that is, underfilling, may be mentioned.

 As another example, a semi-cured anisotropic conductive film is adhered to an electrode portion of an antenna circuit formed on a resin film substrate, and then a bump (projection electrode) of an IC chip is attached to an electrode of the antenna circuit. Alignment is performed, and then the IC chip is heated and pressed to join and harden the anisotropic conductive film.

 As described above, all of these manufacturing methods mount the IC chips in a form of being stacked on the substrate surface on which the antenna circuit is formed.c Therefore, depending on them, the package is thinned. There was a limit.

Thus, for example, as disclosed in Japanese Patent Publication No. 3-72072, a resin film substrate provided with a chip mounting hole and an IC chip formed with electrodes are prepared, and Exposing the electrode on the substrate surface After the IC chip is inserted into the chip mounting hole and fixed as described above, a circuit pattern connected to the @@ is formed on the substrate surface (hereinafter, this method is referred to as an IC chip embedded manufacturing method). ) It was strongly proposed.

 However, in this known IC chip embedded manufacturing method, the chip mounting hole must be larger than the IC chip because the IC chip is inserted into the chip mounting hole provided on the resin film substrate. Therefore, a minute gap (or a minute gap) is formed between the inserted IC chip and the chip mounting hole, so that the minute gap is filled with a resin of the same quality as the substrate, and Both are fused by pressing.

 For this reason, the thin resin film substrate itself is liable to deform during the fusion, and the IC chip moves due to the calo pressure, causing the chip position to fluctuate and become unstable. When the circuit pattern is formed on the board surface after the IC chip is inserted and fixed in the chip mounting hole, it is accurately formed with respect to the electrode of the IC chip, that is, the position is not displaced more than specified. However, it was troublesome to form circuit patterns in such a way, and the quality was not sufficiently stabilized.

 As a solution to this problem, a resin casting method has been adopted instead of the hot press.However, any of these methods is complicated because the process is complicated and a long processing time is required. However, it was not suitable for mass production of COF packages and was difficult to adopt.

The present invention has been made in view of the above-mentioned drawbacks, and a first object of the present invention is to place an IC chip at a position higher than a specified value when obtaining a COF package by an IC chip embedded manufacturing method. It is possible to obtain a C0F package of constant quality that can be embedded in And to be able to The second purpose is to provide C 0 F with constant quality. An object of the present invention is to enable mass production of a package.

 Disclosure of the invention

 In order to achieve the first object, in the present invention, a resin film substrate provided with a chip mounting hole and an IC chip having electrodes formed thereon are prepared, and the electrodes are exposed on a substrate surface. After the IC chip is inserted into the chip mounting hole and fixed, a circuit pattern connected to the electrode is formed on the substrate surface. The hole and the IC chip are provided in a tapered shape, and the IC chip is fixed to the chip mounting hole with a sealant or an adhesive. Further, in order to achieve the second object, the resin film substrate is pressed with a heated taper die to form the chip mounting hole, or a wafer on which a conductive pattern is formed is formed. The cutting is performed by a grinding rotary cutter so that the cutting surface forms a tapered surface, and the IC chip formed with S is prepared.

 BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a view showing a mode in which a tapered IC chip is inserted into a chip mounting taper hole of a resin film substrate.

 FIG. 2 is a diagram showing a tapered IC chip obtained by cutting the wafer of FIG.

 FIG. 3 is a view showing a tapered IC chip obtained by cutting the wafer of FIG.

FIG. 4 is a diagram showing a mode of cutting a wafer to a chip size. Figure 5 shows an example of a wafer for manufacturing tapered IC chips It is.

 Figure 6 is a diagram showing another example of a Ueno for producing a taper type IC chip.

 FIG. 7 is a diagram showing a mode of forming a passivation film.

 FIG. 8 is an enlarged view of a part of FIG.

 FIG. 9 is an enlarged view of a part of FIG.

 FIG. L0 is a diagram showing an aspect in which a protrusion is formed in a tapered hole for chip mounting.

 FIG. 11 is a diagram showing a COF package.

 FIG. 12 is a diagram showing a refilling mode of a sealant or an adhesive, in which (a) shows a state before refilling, and (b) shows a refilling mode by child U printing. FIG.

 FIGS. 13A and 13B are diagrams showing another refilling mode of the sealant or the adhesive, in which (a) shows a state before refilling, and (b) shows a sealing state on a resin film substrate. (C) shows a state in which the sealant or adhesive applied to the resin film substrate is partially removed to expose the electrodes of the tapered IC chip. It is.

 BEST MODE FOR CARRYING OUT THE INVENTION

 In the present invention, as shown in FIG. 1, a tapered IC chip 4 having an electrode 3 formed therein is inserted into a chip mounting tapeper hole 2 provided on a resin film substrate 1. And fix it with a sealant or an adhesive 5 to produce a COF package.

Therefore, the resin film substrate 1 may be made of any resin as long as it is an insulating material. Therefore, a material suitable for such processing, for example, a polyester alloy film substrate or the like is selected. As for the processing method, a predetermined processing method is selected in relation to the selected resin film substrate 1. For example, in the case of a polyester alloy film substrate, a method of pressing it with a heated taper mold is selected. According to this method, a taper hole 2 for chip mounting with a certain precision is quickly formed. can do.

 More specifically, a nickel mold having a plurality of protrusions similar in shape to the taper type IC chip 4 is heated to 240 ° C. and pressed onto a polyester alloy film substrate. After pressing and pressing for 10 seconds, the mold is rapidly cooled and 80. After cooling to C, remove the mold to process the chip mounting taper hole 2 with a hole pitch of 1 O mm (vertical and horizontal), an opening of 1.2 mm 1.6 mm, and a depth of 50 m. Can be.

 The tapered hole 2 for chip mounting is provided in a non-through hole. The non-through hole referred to here is formed by first forming a through hole in the resin film substrate 1 and then opening one end of the through hole by a predetermined method. It may be a closed non-through hole. The tapered hole 2 for chip mounting has a force provided in a predetermined shape corresponding to the shape of the tapered IC chip 4, and is generally provided in a square or rectangular shape in plan view.

Also, the depth D of the tapered hole 2 for chip mounting is selected to be a predetermined depth corresponding to the thickness of the tapered IC chip 4 on which the electrodes 3 are formed, that is, only the electrodes 3 are exposed on the substrate surface. The depth is selected so that the tapered IC chip 4 can be inserted into the chip mounting hole 2 so as to make it tighter. One angle a is generally selected by a force of 45 degrees. And a predetermined angle can be selected from a range of 45 degrees to 60 degrees according to A predetermined pattern is selected as a processing pattern as needed.

 On the other hand, the taper angle 0 b (see FIGS. 2 and 3) of the tapered IC chip 4 on which the electrodes 3 are formed is provided at the same angle as that of the tapered hole 2 for chip mounting (S a). The die IC chip 4 may be manufactured by any method.

 For example, as shown in FIG. 4, a wafer 7 on which a conductor pattern 6 for forming an electrode of an IC chip is formed is cut into a chip size so that its power surface forms a tapered surface. A rotary cutter 16 for grinding a disk body may be used as an example of the cutting means that can be manufactured and used in that case. Although any other cutting means may be used, such a cutting method is suitable for mass production of the tapered IC chip 4 on which the electrode 3 is formed.

 The tapered IC chip 4 is provided in a square or rectangular shape in plan view, and all four side surfaces are provided at a taper angle Sb. As shown in FIGS. 5 and 6, the wafer 7 on which the conductor pattern 6 is formed has an insulating pattern 8 for insulating the conductor pattern 6 formed through a passivation film. Although it is preferable, it may not be formed. In this case, it is necessary to fix the IC chip 4 obtained by cutting the wafer 7 to the substrate before forming the insulating pattern 8. The passivation film is a passivation film 15 covering the wafer surface (that is, the chip surface), as shown in FIG.

In addition, as shown in FIG. 8, which is a partially enlarged view of FIG. 5, the conductor pattern 6 is formed on the lower first conductor layer 9 (conductor pattern electrode). As shown in FIG. 9 which is an enlarged view of a part of FIG. 6 or a two-layer structure having an under barrier-metal layer 10 formed thereon, as shown in FIG. The electrode may have any structure, such as a three-layer structure in which an under-barrier metal layer 10 is formed on the underlayer and a second conductor layer 11 is formed on the under-barrier metal layer 10.

 In these, the deterioration of the first conductor layer 9 can be prevented by the under barrier metal layer 10, but the under barrier metal layer 10 ensures the connection between the electrode of the Ic chip and the external layer. It also has the role of Accordingly, the wafer 7 shown in FIGS. 5 and 6 can be cut to a chip size to obtain tapered IC chips 4 a and 4 b (see FIGS. 2 and 3) in which the electrodes 3 are formed.

 Before inserting the tapered IC chip 4 a or 4 b on which the electrode 3 is formed into the chip mounting tapered hole 2 of the resin film substrate 1, a sealant or an adhesive is attached to the chip mounting tapered hole 2. Preferably, a predetermined amount of agent 5 is applied. If necessary, it may be applied to the lower end surface of the tapered IC chip 4 on which the electrode 3 is formed (the lower surface on the side inserted into the tapered hole 2 for chip mounting).

 Also, in order to improve the liquid flow of the sealant or the adhesive 5, a bottom protrusion 12 and a side protrusion 13 are formed in the hole 2 for the chip mounting tape as shown in FIG. The power to do is preferable. Alternatively, it is preferable to provide a bleed hole 20 in the bottom wall of the hole as shown in FIG. By providing the bleed hole 20, the tapered hole 2 for chip mounting can be tapered.

After the IC chip 4 is inserted, air can be released when the sealing agent or the adhesive 5 is heated and hardened. In addition, a predetermined material such as an epoxy-based, acrylic-based, or polyimide-based sealant or adhesive 5 can be selected, and is generally applied only to the bottom wall of the hole (see FIG. 1). do it. However, if necessary, only the side wall of the hole or L may be applied to both of them, and the coating method may be any method such as a method using a transfer pin.

 Further, the method of inserting the tapered IC chip 4 into the chip mounting tapered hole 2 may be either batch insertion into the chip mounting taper hole 2 or individual insertion. Generally, the latter is chosen in view of the difficulty of the former. For example, the taper type IC chip 4 may be sucked and held by an intake type nozzle, transferred, and sequentially inserted into the tapered hole 2 for chip mounting at a predetermined location.

Through the above-described steps, a taper type IC chip 4 having a chip 3 is inserted into a chip mounting taper hole 2 provided in the resin film substrate 1 and both are sealed. If it can be fixed with an adhesive or an adhesive 5, then, as shown in FIG. 11, a circuit pattern connected to the electrode 3 of the tapered IC chip 4 is applied. It is formed on the resin film substrate 1 by an appropriate method, and the entire substrate surface on which the circuit pattern 14 is formed is sealed with a shelf film or the like. As described above, in the present invention, the chip mounting hole and the IC chip are provided in a tapered shape, and the IC chip is fixed to the chip mounting hole with a sealant or an adhesive. As a result, the IC chip can be buried in a state where it does not deviate more than specified, so that when forming a circuit pattern on the substrate surface, it is accurately formed with respect to the electrodes of the IC chip, that is, specified. If there is no misalignment as described above, a circuit can be formed in the state, You can get a quality C 0 F package.

 If the sealing agent or the adhesive 5 is applied excessively to the above-mentioned tapered hole 2 for chip mounting, etc., when the tapered IC chip 4 is inserted, an excessive amount of the sealing agent or the adhesive is used when the tapered IC chip 4 is inserted. It is pushed out on the surface and obstructs the formation of circuit pattern 14 (see Fig. 11). To prevent this, a small amount of sealing agent is required to temporarily fix the tapered IC chip 4 with L, without applying a sealing agent or adhesive 5 over the entire surface of the tapered hole 2 for chip mounting. Alternatively, it is preferable to locally apply the adhesive 5 to the tapered hole 2 for chip mounting.

 However, in this case, a small gap force is formed between the taper type IC chip 4 inserted therein and temporarily fixed, and the tapered hole 2 for chip mounting. It is preferable to refill 5 in a vacuum atmosphere.

For example, in FIG. 12 (a), the tapered chip mounting hole 2 and the tapered IC chip 4 are brought into contact with each other with a tapered surface, and at the bottom corner of the chip mounting tapered hole 2 The taper type IC chip 4 is temporarily fixed by the sealant or adhesive 5a and 5b which are separated and applied, etc., but in such a case, as shown in FIG. 1 2 (b), may be supplemented Takashi塡by stencil printing in a vacuum atmosphere sealant or adhesive 5 by using the charge塡孔2 1 provided in the hole bottom wall _c In the figure, the sealant or adhesive 5 supplied onto the stencil 22 is pushed into the filling hole 21 from the opening 24 of the mosquito U 22 by the movement of the squeegee 23, and Will be charged to Note that the filling hole 21 may also serve as the pread hole 20. Although another example is shown in FIG. 13, this example differs from the example of FIG. 12 described above in that the taper hole 2 for chip mounting and the tapered IC chip 4 are tapered to each other. They are not in contact with each other, and a sealant or adhesive IJ5 is interposed between them.

 In this case, a sealant or an adhesive 5 is applied in a vacuum atmosphere to a predetermined thickness on the surface of the resin finolem substrate 1 where the S3 of the taper type IC chip 4 is exposed, and Accordingly, the gap between the taper hole 2 for chip mounting and the tapered IC chip 4 is filled.

 Then, the sealing agent or the adhesive 5 at that portion is removed so that the electrode 3 of the tapered IC chip 4 covered with the sealing agent or the adhesive 5 is exposed. In the latter case, a photosensitive insulating material is preferable as the sealing agent or the adhesive 5, but when this is used, it is removed by developing so that the electrode 3 of the tapered IC chip 4 is exposed. .

 In any of the examples described above, the vacuum atmosphere is kept in the range of 13.3 Pa to 665 Pa. As described above, in the present invention, as long as the chip mounting hole and the IC chip are provided in a tapered shape, the sealing agent or the adhesive may be applied in any form.

 As described above, the IC chip embedded manufacturing method according to the present invention will be described in more detail with reference to the following examples.

 [Example 1]

A wafer 7 having a thickness of 50 μm was obtained by polishing the back surface of the wafer on which the aluminum electrode (the first conductor layer 9 of the conductor pattern 6) was formed. The area of one IC chip on the surface is 1.6 mm x 2.0 mm, and a 100 / im square aluminum electrode is located diagonally on the outer periphery. Are paired.

 The wafer 7 is treated with a weak acidic solution to remove the oxide film on the surface of the aluminum electrode. After the activation treatment, the wafer 7 is immersed in an electroless nickel bath at 90 ° C. for 20 minutes to leave only the aluminum electrode. A nickel plating layer of about 3 m was formed, and then immersed in an electroless gold plating bath at 90 ° C for 10 minutes to form a gold plating layer of about 0.1 ^ πι on the nickel plating layer.

 The nickel-Z gold plating layer prevents the aluminum from deteriorating, and also ensures that the connection between the IC chip and the external terminals is maintained under the barrier-metal layer 10 (generally called UBM). It is.

 Next, a solder resist was printed on the upper surface of the wafer except for the aluminum electrode forming portion using a screen printing machine, and then cured by irradiating ultraviolet rays with a UV lamp to form an insulating pattern 8 having a thickness of 20 μπι.

 Next, using a screen printing machine, a conductive paste in which silver particles are dispersed is printed and filled in the opening of the aluminum electrode forming portion (where the insulating pattern 8 is not formed), and the conductor is cured by heating. The second conductor layer 11 of the pattern 6 was formed (see FIGS. 6 and 9).

 Next, after the front surface of the wafer 7 (the surface on which the conductive pattern 6 is formed) is adhered to a support film, 1.6 mm from the rear surface side is used using a diamond blade whose tip is beveled. A full-cut (cut only the wafer) to a chip size of x2. O mm was obtained to obtain a taper type IC chip 4b with a taper angle of 0b and a force of 45 degrees forming a «3 (see Fig. 3). ). Next, the tapered IC chip 4b was removed from the support film, and aligned on a pallet manufactured by a nickel electrode method.

On the other hand, it is composed of a polyester alloy film with a thickness of 100 μm. A plurality of tapered holes 2 for chip mounting were formed on the resin film substrate 1 using a nickel-made mold in which protrusions corresponding to chip shapes were formed in a predetermined pattern. At this time, the nickel mold was heated to 240 ° C, pressed against the resin film substrate 1 and pressed for 10 seconds, and then the nickel mold was rapidly cooled to 80 ° C. At the time of cooling, the mold was separated.

 The tapered hole 2 for chip mounting formed in this way has an opening size of 1.6 mm X 2.0 mm, a depth D of 70 μππ, a taper angle 4a of 45 degrees, and a hole pitch. However, it was 1 O mm in the vertical direction and 5 O mm in the horizontal direction.

 Next, a sealant or adhesive 5 made of a low-viscosity epoxy resin was applied to the chip mounting tapered hole 2 (see Fig. 1). Applied.

 Next, the above-mentioned tapered IC chip 4b of the pallet is sucked and held and transferred by a nozzle with a diameter of 1.5 mm, which has an intake hole opened at the center of the tip, and is transferred to the chip mounting tapered hole 2. It was inserted and fixed.

 At this time, the upper surface of the tapered IC chip 4b (the substrate surface on which the electrode 3 is formed) and the upper surface of the resin film substrate 1 can be connected so that no victory is formed between them. At the same time, it could be quickly inserted and fixed.

In this way, the tapered IC chip 4 could be easily mounted on the resin film substrate 1 with only the electrodes 3 exposed on the substrate surface (see Fig. 11). Then, a circuit pattern 14 connected to the electrode 3 of the tapered IC chip 4 is formed on such a substrate surface, that is, a conductive paste in which silver particles are dispersed by about 70% using a screen printer. Was printed to form a circuit pattern 14 having a circuit width of l mm and a thickness of about 25 / m.

 Therefore, both ends of the circuit pattern 14 were extended over the plurality of electrodes 3 of the tapered IC chip 4 to form a closed-circuit antenna that was electrically connected to the chip.

 Finally, a cover film made of a polyester alloy film having a thickness of 100 m is formed on the upper surface of the resin film substrate 1 on which the tapered IC chip 4 is embedded and mounted. The resultant was subjected to thermal lamination with C, and then pressed to a card size of 100 mm x 50 mm to obtain a thin contactless tag having a thickness of approximately 200 m.

 Example 2]

 A resist is applied to the wafer 7 having a thickness of 50 m obtained by the same method as in Example 1 described above and dried, and then the aluminum electrode portion (the first conductor layer of the conductor pattern 6) is formed using a photomask. 9) was exposed and developed and removed to expose only the aluminum electrode.

 Next, after subjecting the wafer 7 to plasma treatment to remove the oxide film on the aluminum electrode surface, Ti W and Au are laminated by sputtering to a thickness of about 0.5 / m and 0.05 μm, respectively. Finally, the resist was separated. The laminated metal layers other than the aluminum electrode (the first conductor layer 9) were removed, and an underbarrier metal layer 10 having a total thickness of about 0.55 m was formed only on the aluminum electrode.

Next, a photosensitive epoxy resin is coated on the entire surface of the wafer 7, and through the exposure and development process and the heat curing process again, an insulating pattern 8 having a thickness of 15 m is formed on the entire surface of the wafer excluding the aluminum electrode forming portion. (See Figure 5). Next, a teno in which the electrode 3 was formed by full cutting (cutting only the wafer) to a chip size in the same manner as in Example 1. A tape type IC chip 4a with an angle b of 45 degrees was obtained (see Fig. 2).

 Next, through the same steps as in Example 1, the resin film substrate 1 was inserted and fixed in the tapered hole 2 for chip mounting. At this time, the upper surface of the taper type IC chip 4a (the surface on which the electrode 3 is formed) and the upper surface of the resin film substrate 1 can be connected so that no step is formed between them. At the same time, it could be inserted and fixed quickly.

 In this manner, the tapered IC chip 4a was easily mounted on the resin film substrate 1 with the electrodes 3 exposed on the substrate surface (see FIG. 11).

 Bow (Continuously, a circuit pattern 14 connected to the electrode 3 is formed on the resin film substrate 1, that is, a conductive paste in which silver particles are dispersed by about 70% using a screen printing machine. Was printed to form a circuit pattern 14 having a thickness of about 30. At that time, the above-mentioned conductive paste was also filled and printed on the under barrier-methanol layer 10 at the same time.

 Therefore, also in this case, both ends of the circuit pattern 14 were extended over the plurality of electrodes 3 of the tapered IC chip 4a, and a closed-circuit one-turn antenna electrically connected to the chip electrode could be formed.

 Next, a cover film similar to that of Example 1 was heat-laminated at 220 ° C and cut into a force size of 1 Omm x 5 Omm to obtain a thickness of approximately 200 μm. A thin non-contact tag of ιη was obtained.

 [Example 3]

Only the aluminum electrode (first conductor layer 9 of conductor pattern 6) is formed on the surface. After the wafer 7 is attached to the sabot film, a diamond blade with a beveled tip is used to make a full cut (cut only the wafer) to a chip size of 0.6 mm x 0.8 mm from the back side. Thus, a tapered IC chip 4 having a taper angle 6b of 45 degrees and the electrode 3 formed thereon was obtained. In this case, 16 electrodes 50 of 50 / m square are formed at a pitch of 100〃m, but no insulating pattern is formed.

 Next, the tapered IC chip 4 was separated from the support film and aligned on a pallet manufactured by the nickel method.

 On the other hand, a taper hole 2 for chip mounting with a taper angle 0a of 45 degrees was formed on a resin film substrate 1 made of a polyester film with a thickness of 100 by the UV laser method. After that, a small amount of epoxy-based sealant 5 with low viscosity is transferred to the chip mounting taper hole 2 with a transfer pin at the bottom of the hole, and the tip diameter is 0.5 mm and 0.2 mm at the center. The above-mentioned tapered IC chip 4 of the pallet was sucked and held and transferred by a nozzle having an intake hole, and was inserted and fixed in the tapered hole 2 for chip mounting.

 Also in this case, the upper surface of the tapered IC chip 4 (the surface on which S3 is formed) and the upper surface of the resin film substrate 1 could be connected so that no butterfly was formed between them. At the same time, it was possible to quickly insert and fix.

 Next, the entire surface of the resin film substrate 1 is coated with a photosensitive epoxy resin, and exposed and developed. After a heat-curing step, a 10-μm-thick insulating layer 8 was formed on the entire surface of the wafer except for the aluminum electrode part (the first conductive layer 9).

In the next L ヽ, the resin film substrate 1 is treated with an alkaline liquid to After removing the oxide film on the surface and activating, immersion in an electroless nickel bath at 85 ° C for 15 minutes to form a nickel plating layer of about 2 m only on the aluminum electrode ± 90 It was immersed in an electroless gold plating bath at 5 ° C. for 5 minutes to form a gold plating layer of 0.05 / m on the nickel plating layer, that is, an underbarrier metal layer 10 was formed.

 Next, aluminum is applied to the entire surface of the resin film substrate 1 by 0.6 ° πιβ by means of snowboarding and heating, then a resist is applied thereon and dried, followed by exposure and development to form a wiring circuit image. After that, the aluminum in the opening of the resist was removed using an aluminum etchant to form an aluminum circuit pattern 14.

 [Example 4]

 The steps up to the step of forming an insulating pattern 8 having a thickness of 10 μm on the entire surface of the wafer excluding the aluminum electrode portion were performed in the same manner as in Example 3.

 Next, after removing the oxide film on the surface of the aluminum electrode by plasma treatment, Ni is deposited to a thickness of 0.05 μππ, and aluminum is deposited to a thickness of 0.6 m, and a resist is applied on the aluminum 'and dried. After forming an SB-exceeded circuit image by exposure and development, the aluminum in the opening of the resist was removed using an aluminum etchant to form an aluminum circuit pattern 14.

 Industrial use

As described above, according to the present fiber, when a COF package is to be obtained by an IC chip embedded manufacturing method, the IC chip can be embedded in a V state in which the position of the IC chip is displaced more than specified. Correct the circuit pattern with respect to the tip electrode. It is possible to obtain a constant quality C0F package that can be formed.

 In addition, the resin film substrate is pressed with a heated taper mold to form holes for chip mounting, or the wafer on which the conductor pattern is formed is formed into a tapered cutting surface with a rotary cutter for grinding. In this way, mass production of COF packages of a certain quality can be achieved by preparing an IC chip formed by cutting into a shape.

Claims

The scope of the claims  1. A resin film substrate provided with a chip mounting hole and an IC chip having electrodes formed thereon were prepared, and the IC chip was inserted into the chip mounting hole and fixed so that the electrodes were exposed on the substrate surface. Then, in a method of manufacturing a C 0 F package in which a circuit pattern connected to the electrode is formed on the substrate surface, the chip mounting hole and the IC chip are provided in a taper type; and A method of manufacturing a C 0 F package, comprising: fixing the chip mounting hole to the chip mounting hole with a sealant or an adhesive.  2. The gap between the IC chip fixed to the chip mounting hole and the chip mounting hole is filled with a sealant or an adhesive under a vacuum atmosphere. 2. The method for producing a C 0 F package according to item 1.  3. The package according to claim 1, wherein said resin film substrate is pressed with a heated taper mold to form said chip mounting hole. Manufacturing method.  4. A wafer having a conductive pattern formed thereon is cut to a chip size, and when preparing an IC chip having an electrode formed thereon, the cut surface is cut so as to form a tapered surface. A method for manufacturing a C 0 F package according to paragraph 1, paragraph 2 or paragraph 3.  5. The method for manufacturing a C 0 F knock cage according to claim 4, wherein the cutting is performed using a turning torque cutter for grinding so that the force surface forms a tapered surface. 6. The C 0 F package according to claim 5, wherein the chip mounting hole and the IC chip have the same taper angle. Production method.  7. The method for manufacturing a C 0 F package according to claim 6, wherein the conductor pattern has an under-barrier metal layer.  8. The method for manufacturing a C 0 F package according to claim 7, wherein an insulating pattern for insulating the conductor pattern is formed.